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M CONCEPT
II. SYSTEM
I. INTRODUCTION
N OF MODULES
III. DISCUSSION
A. ARM 7TDM-S
An ARM7TDM-S processor core acts as the logical brain
of the FPGA based system for handling data processing and
s
delegates USB 2.0
manipulation. The ARM7 system
communication to the USB conntroller, therefore it does not
have direct influence on USB data
d transfers.
689
TENCON 2011
2
CL)
E.1 USB Core Logic (UC
C. Bus Arbiter
The Bus Arbiter module gives control to either the USB
n
to access the
Controller or the ARM7 whenever one needs
Main Memory. It prioritizes the USB Controller
C
over the
ARM7. The Bus Arbiter sets the ARM7 on hold whenever it
t
as the USB
requires memory access at the same time
Controller to prevent bus contention.
D. USB Interface Module (USBI)
The USB Interface Module providdes compatibility
between the USB Controller and the ZBT
T SRAM. The USB
Controller accepts and sends data in byttes while the ZBT
SRAM receives and gives data in 32 bits.
m for USBI
Figure 3. STORE Timing Diagram
Endpoint
EP0
EP1
EP2
m for USBI
Figure 4. LOAD Timing Diagram
EP3
o the STORE and
Fig. 3 & 4 shows the timing diagrams of
LOAD operations of USBI respectively.
Functionality
Control Endpoint; for Control transfers
IN Endpoint; conttains USB data to be
transmitted to Host
OUT Endpoint; coontains SRAM Address for
both transmit andd receive operations
OUT Endpoint; coontains Data to be written to
SRAM for receivee operations
Table 1. Functionalitiess of Endpoints in ERF'
E. USB Controller(USBC)
F. USB Transceiver
B
Diagram
Figure 5. USB Controller Top Level Block
USB communication on the ARM7 syystem side is fully
handled by the USB Controller while the ARM7 core
U
Controller has
focuses entirely on data processing. The USB
three main components: the USB Core Logic, the Endpoint
Register File, and the USB Function.
Figure 7. EVB-U
USB3300 [14]
690
3
The USB Transceiver hardware is exteernal to the FPGAbased system. It handles the electrical andd physical layer of
the USB communication. Shown in Fig. 7 is the Evaluation
board of the SMSC USB3300 transceiver.
G. Software
G.1 Application Software
Figure 10. USB Transceiverr Detection and High Speed
Initializzation
YSIS
IV. RESULTS AND ANALY
4
daughter card of the FPGA board. Since the Virtex-5 FPGA
does not have this connector, copper wires were used to
connect the transceiver pins to the Virtex-5 IO header pins,
as shown in Figure 9. This design decision introduced some
unwanted delays to the system.
2. Clock Reliability
Clock reliability poses a challenge to the whole system
design. The architecture of the design is built so that it
receives clock signal from one source, that of the external
transceiver. However, since this clock source drives the
clock signal of the whole system including the transceiver,
clock skews and clock signal attenuations provide
considerable drawbacks.
3. FPGA Internal Logic Delay
Figure 14 shows the post-route synthesis simulation of an
8-bit register with a 60 MHz clock implemented on a
Virtex-5 FPGA board. It can be deduced from the figure that
the latch delay from the time the positive edge of the clock
has triggered to the changing of the output signal is
approximately 6 ns, which is very near to the negative edge
of the clock. This design constraint has many repercussions.
First, since the system operates at a 60 MHz clock or 16.67
ns period, a 6 ns delay can induce setup and hold time
violations. Also, because of this inherent delay, overall
timing and synchronization between the transceiver
hardware and FPGA-based system is compromised. The
system will suffer unwarranted data errors and misaligned
control signals (i.e dir, nxt, stp) that will eventually lead to
miscommunication and faulty operation.
VI. REFERENCES
[1] Fatemeh Arbab Jolfaei et al., High Speed USB 2.0
Interface for FPGA Based Embedded Systems, Isfahan
University of Technology, Department of Electrical &
Computer Engineering
[2] Universal Serial Bus Specifications Revision 2.0
[3] www.usb.org [online]
[4] CY7C68001 EZ-USB SX2 High-Speed USB Interface
Device Datasheet, Cypress Corp., Jun 2005
[5] Jan Axelson, USB Complete - Everything you need to
develop custom USB peripherals, Lakeview research, 3rd
Edition, Aug 2005
[6] Virtex 5 ML507 Evaluation Platform, Xilinx Corp.
[7] Luna et al., Implementation of the Complete
ARM7TDMI-S Instruction Set on a Debug Capable
Core, Department of Electrical and Electronics
Engineering, University of the Philippines,
Diliman,
October 2008.
[8] Posada-Gomez et al., USB bulk transfers between a PC
and a PIC microcontroller for
embedded
applications, Instituto Tecnologico de Orizaba, Division
of Research and Postgraduate Studies, Orizaba,
Veracruz, Mexico, 2008
[9] Cypress TX2 USB 2.0 UTMI Transceiver Datasheet,
May 2 2006, Cypress Semiconductor Corp.
[10] Kouyama et al., The Design of a USB Device Controller
IYOYOYO, Graduate School of Engineering, Tokai
University
[11] Rudolf Usselmann, USB Function IP Core Revision 1.5,
January 27, 2002
[12] ISP1505A; ISP1505C ULPI Hi-Speed Universal Serial
Bus host and peripheral transceiver Rev. 01, October
19, 2006
[13] CY3688 MoBL-USB TX32UL USB 2.0 ULPI
Transceiver, September 22, 2010
[14] EVB-USB3300 User Manual Rev. 4.0, Dec 18, 2006
[15] UTMI + Low Pin Interface (ULPI) Specification
Revision 1.1, Oct. 20, 2004