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L P(n)
D R(n)
Bridge
rectifier
diode
V DC
+
CDC
R sn
Vsn
+
C sn
Np
N S(n)
CO(n)
VO(n)
CP(n)
Dsn
D R1
FPS
L P1
Drain 1
N S1
AC line
GND 2
FB
4
Vcc
3
Ra
Da
CO1
Rd
Rbias
H11A817A
CB
Ca
Na
V O1
CP1
H11A817A
R1
RF
KA431
CF
R2
1. Introduction
Figure 1 shows the schematic of the basic off-line flyback
converter using FPS, which also serves as the reference
circuit for the design process described in this paper.
Because the MOSFET and PWM controller together with
various additional circuits are integrated into a single
package, the design of SMPS is much easier than the discrete
MOSFET and PWM controller solution. This paper provides
a step-by-step design procedure for a FPS based off-line
flyback converter, which includes designing the transformer
AN4137
APPLICATION NOTE
P
Pin = ------oE ff
(1)
Po (n )
KL ( n ) = -----------Po
Y
(2)
where Po(n) is the maximum output power for the n-th output. For single output SMPS, KL(1)=1.
Y
Is it possible to change the core ?
V DC
min
2 ( V line
(3)
Design finished
P in ( 1 D ch )
) -----------------------------------C DC f L
min 2
max
2V line
max
(4)
APPLICATION NOTE
AN4137
DC link voltage
T1
Dch = T1 / T2
= 0.2
T2
VDC
+
VRO
+
F PS
D rain
GND
V ds
-
V RO
Rectifier
Diode
Current
Rectifier
Diode
Current
V DC
0V
When the MOSFET in the FPS is turned off, the input voltage (VDC) together with the output voltage reflected to the
primary (VRO) are imposed on the MOSFET as shown in figure 5. After determining Dmax, VRO and the maximum nominal MOSFET voltage (Vdsnom) are obtained as
D max
min
V RO = ----------------------- V DC
1 D max
V ds
nom
= V DC
max
+ VRO
(5)
(6)
AN4137
APPLICATION NOTE
V DC
CCM
1
1 -
= --------------------------- ---------
2L m f s P in VRO
(12)
where Pin, VRO and Lm are specified in equations (1), (5) and
(7), respectively, and fs is the FPS switching frequency.
If the result of equation (12) has a negative value, the converter is always in CCM under the full load condition regardless of the input voltage variation.
I ds peak
I EDC
K RF =
I
2I EDC
min
( VDC
D max )
L m = --------------------------------------------2Pin f s KRF
(7)
I ds peak
rms
where
and
peak
I
= I EDC + ----2
2
I 2 D max
3 ( IEDC ) + ----- ------------2
3
P in
I EDC = ------------------------------------min
V DC
D max
V
min
DC
max
I = -----------------------------------
Lm fs
(8)
(9)
(10)
(11)
I EDC
K RF =
I
2I EDC
With the resulting maximum peak drain current of the MOSFET (Idspeak) from equation (8), choose the proper FPS of
which the pulse-by-pulse current limit level (Iover) is higher
than Idspeak. Since FPS has 12% tolerance of Iover, there
should be some margin in choosing the proper FPS
device.The FPS lineup with proper power rating is also
included in the software design tool.
APPLICATION NOTE
AN4137
With the chosen core, the minimum number of turns for the
transformer primary side to avoid the core saturation is given
by
NP
min
L m Iover
6
= ------------------- 10
B sat A e
(turns)
(13)
where Lm is specified in equation (7), Iover is the FPS pulseby-pulse current limit level, Ae is the cross-sectional area of
the core as shown in figure 7 and Bsat is the saturation flux
density in tesla. Figure 8 shows the typical characteristics of
ferrite core from TDK (PC40). Since the saturation flux density (Bsat) decreases as the temperature goes high, the high
temperature characteristics should be considered.
If there is no reference data, use Bsat =0.3~0.35 T. Since the
MOSFET drain current exceeds Idspeak and reaches Iover in a
transition or fault condition, Iover is used in equation (13)
instead of Idspeak to prevent core saturation during transition.
Output
Power
EI core
EE core
EPC core
0-10W
EI12.5
EI16
EI19
EE8
EE10
EE13
EE16
EPC10
EPC13
EPC17
10-20W
EI22
EE19
EPC19
EE22
EPC25
EER25.5
EE25
EPC30
EER28
20-30W
EER core
EI25
30-50W
EI28
EI30
50-70W
EI35
EE30
EER28L
70-100W
EI40
EE35
EER35
100-150W EI50
EE40
EER40
EER42
150-200W EI60
EE50
EE60
EER49
Aw
(7) STEP-7 : Determine the number of turns for each
output
Ae
Figure 7. Window Area and Cross Sectional Area
500
60
100
400
Flux density B (mT)
120
(14)
where Np and Ns1 are the number of turns for primary side
and reference output, respectively, Vo1 is the output voltage
and VF1 is the diode (DR1) forward voltage drop of the reference output.
Then, determine the proper integer for Ns1 so that the resulting Np is larger than Npmin obtained from equation (13).
The number of turns for the other output (n-th output) is
determined as
Vo (n ) + VF ( n)
Ns1
N s ( n ) = --------------------------------V o1 + V F1
( turns )
( 15 )
300
V cc * + V Fa
- N s1
N a = --------------------------V o1 + VF1
100
0
0
800
M agnetic field H (A/m )
1600
( turns )
( 16 )
AN4137
APPLICATION NOTE
+ V F(n) -
D R(n)
Np
V RO
+
V O(n)
N S(n)
A w r = Ac K F
Da
+
V cc *
+ V F1 -
- V Fa +
+
V O1
D R1
N S1
Na
(19)
With the determined turns of the primary side, the gap length
of the core is obtained as
The maximum reverse voltage and the rms current of the rectifier diode (DR(n)) of the n-th output are obtained as
NP
1
G = 40 A e -------------------- ------
1000L
A
m
L
( mm )
( 17 )
I sec ( n )
rms
= I ds
rms
rms
V RO K L ( n )
1 D max
----------------------- -------------------------------------( Vo (n ) + VF ( n) )
D max
( 18 )
max
V DC
( Vo ( n) + VF ( n ) )
V D ( n ) = Vo ( n ) + --------------------------------------------------------------V RO
( 20 )
V RO K L ( n )
1 Dmax
----------------------- -------------------------------------( Vo( n) + VF ( n) )
D max
( 21 )
ID ( n)
rms
= I ds
rms
rms
(22)
(23)
APPLICATION NOTE
AN4137
VRRM
IF
trr
Package
SB330
30 V
3A
TO-210AD
SB530
30 V
5A
TO-210AD
MBR1035
35 V
10 A
TO-220AC
MBR1635
35 V
16 A
TO-220AC
SB340
40 V
3A
TO-210AD
SB540
40 V
5A
TO-210AD
SB350
50 V
3A
TO-210AD
SB550
50 V
5A
TO-210AD
SB360
60 V
3A
TO-210AD
SB560
60 V
5A
TO-210AD
MBR1060
60 V
10 A
TO-220AC
MBR1660
60 V
16 A
TO-220AC
VRRM
IF
trr
Package
EGP10B
100 V
1A
50 ns
DO-41
UF4002
100 V
1A
50 ns
DO-41
EGP20B
100 V
2A
50 ns
DO-15
EGP30B
100 V
3A
50 ns
DO-210AD
I cap ( n )
rms
( ID ( n )
rms 2
) Io ( n)
(24)
where Io(n) is the load current of the n-th output and ID(n)rms
is specified in equation (21). The ripple current should be
smaller than the ripple current specification of the capacitor.
The voltage ripple on the n-th output is given by
I
peak
V R
K
( V o ( n ) + VF ( n ) )
o ( n ) max
ds
RO C ( n ) L ( n )
V o ( n ) = ------------------------ + ---------------------------------------------------------- (25)
C o ( n ) fs
FES16BT
100 V
16 A
35 ns
TO-220AC
EGP10C
150 V
1A
50 ns
DO-41
EGP20C
150 V
2A
50 ns
DO-15
EGP30C
150 V
3A
50 ns
DO-210AD
FES16CT
150 V
16 A
35 ns
TO-220AC
EGP10D
200 V
1A
50 ns
DO-41
UF4003
200 V
1A
50 ns
DO-41
EGP20D
200 V
2A
50 ns
DO-15
When the power MOSFET is turned off, there is a high voltage spike on the drain due to the transformer leakage inductance. This excessive voltage on the MOSFET may lead to
an avalanche breakdown and eventually failure of FPS.
Therefore, it is necessary to use an additional network to
clamp the voltage.
EGP30D
200 V
3A
50 ns
DO-210AD
FES16DT
200 V
16 A
35 ns
TO-220AC
EGP10F
300 V
1A
50 ns
DO-41
EGP20F
300 V
2A
50 ns
DO-15
EGP30F
300 V
3A
50 ns
DO-210AD
EGP10G
400 V
1A
50 ns
DO-41
UF4004
400 V
1A
50 ns
DO-41
EGP20G
400 V
2A
50 ns
DO-15
EGP30G
400 V
3A
50 ns
DO-210AD
UF4005
600 V
1A
75 ns
DO-41
EGP10J
600 V
1A
50 ns
DO-41
EGP20J
600 V
2A
50 ns
DO-15
EGP30J
600 V
3A
50 ns
DO-210AD
UF4006
800 V
1A
75 ns
TO-41
UF4007
1000 V
1A
75 ns
TO-41
The RCD snubber circuit and MOSFET drain voltage waveform are shown in figure 10 and 11, respectively. The RCD
snubber network absorbs the current in the leakage inductance by turning on the snubber diode (Dsn) once the MOSFET drain voltage exceeds the voltage of node X as depicted
in figure 10. In the analysis of snubber network, it is
assumed that the snubber capacitor is large enough that its
voltage does not change significantly during one switching
cycle.
The first step in designing the snubber circuit is to determine
the snubber capacitor voltage at the minimum input voltage
and full load condition (Vsn). Once Vsn is determined, the
power dissipated in the snubber network at the minimum
input voltage and full load condition is obtained as
AN4137
APPLICATION NOTE
From equation (28), the maximum voltage stress on the internal MOSFET is given by
V
( V sn )
peak 2
sn
1
- = --- fs L lK ( I ds
) --------------------------P sn = ---------------2
R sn
Vsn V RO
(26)
peak
where Ids
is specified in equation (8), fs is the FPS
switching frequency, Llk is the leakage inductance, Vsn is the
snubber capacitor voltage at the minimum input voltage and
full load condition, VRO is the reflected output voltage and
Rsn is the snubber resistor. Vsn should be larger than VRO
and it is typical to set Vsn to be 2~2.5 times of VRO. Too
small a Vsn results in a severe loss in the snubber network as
shown in equation (26). The leakage inductance is measured
at the switching frequency on the primary winding with all
other windings shorted.
Then, the snubber resistor with proper rated wattage should
be chosen based on the power loss. The maximum ripple of
the snubber capacitor voltage is obtained as
V sn
V sn1
= ----------------------C sn R sn f s
V ds
(31)
VDC
+
CDC
Rsn
Csn
X
VX
Vsn
+
Np
VRO
+
Dsn
FPS
Llk
Drain
GND
+
Vds
-
(28)
(29)
BVdss
Vsn2
When the converter operates in DCM at the maximum input
voltage and full load condition (refer to equation (12)), the
Ids2 of equation (28) is obtained as
2 P in
---------------fs Lm
+ V sn2
V RO + ( VRO ) + 2R sn L lk fs ( I ds2 )
V sn2 = ------------------------------------------------------------------------------------------2
I ds2 =
max
= V DC
(27)
max
VDC max
(30)
VRO
0V
Figure 11. MOSFET drain voltage and snubber capacitor
voltage
2003 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4137
(32)
where Ipk is the peak drain current and VFB is the feedback
voltage, respectively for a given operating condition, Iover is
the current limit of the FPS and VFBsat is the feedback saturation voltage, which is typically 2.5V.
vo1'
FPS
vFB
RB
CB
RD
vo1
ibias
Rbias
iD
1:1
CF
RF
R1
KA431
R2
RL ( 1 D )
1
(1 + D)
- and w p = ------------------w z = -------------------- , w rz = ---------------------------------------2
R c1 C o1
R L C o1
DL m ( N s1 N p )
Ipk
MOSFET
current
where
(34)
1
wz = -------------------- , w p = 2 R L C o1
R c1 C o1
v o1
= -------v
FB
K R L V DC ( N p N s1 ) ( 1 + s w z ) ( 1 s w rz )
= ----------------------------------------------------- ---------------------------------------------------------1 + s wp
2V RO + v DC
( 33 )
Vo1 is the reference output voltage, VFB is the feedback voltage for a given condition, RL is the effective total resistance
of the controlled output, Co1 is the controlled output capacitance and Rc1 is the ESR of Co1.
Figure 15 shows the variation of the control-to-output transfer function of a flyback converter in DCM for different
loads. Contrary to the flyback converter in CCM, there is no
RHP zero and the DC gain does not change as the input voltage varies. As can be seen, the overall gain except for the DC
gain is highest at the full load condition.
The feedback compensation network transfer function of figure 12 is obtained as
AN4137
APPLICATION NOTE
w i 1 + s w zc
v FB
-------- = - ----- --------------------------
s 1 + 1 w pc
v o1
(35)
RB
1
1
- , w zc = --------------------------------- , w pc = --------------where w i = ---------------------R1 RD CF
( R F + R 1 )C F
RB CB
40 dB
fp
20 dB
fp
0 dB
fz
-20 dB
frz
fz
frz
When the input voltage and the load current vary over a wide
range, it is not easy to determine the worst case for the feedback loop design. The gain together with zeros and poles
vary according to the operating condition. Moreover, even
though the converter is designed to operate in CCM or at the
boundary of DCM and CCM in the minimum input voltage
and full load condition, the converter enters into DCM
changing the system transfer functions as the load current
decreases and/or input voltage increases.
One simple and practical way to this problem is designing
the feedback loop for low input voltage and full load condition with enough phase and gain margin. When the converter
operates in CCM, the RHP zero is lowest in low input voltage and full load condition. The gain increases only about
6dB as the operating condition is changed from the lowest
input voltage to the highest input voltage condition under
universal input condition. When the operating mode changes
from CCM to DCM, the RHP zero disappears making the
system stable. Therefore, by designing the feedback loop
with more than 45 degrees phase margin in low input voltage
and full load condition, the stability over all the operating
ranges can be guaranteed.
-40 dB
10Hz
100Hz
1kHz
10kHz
100kHz
Figure 13. CCM flyback converter control-to output transfer function variation for different input voltages
40 dB
fp
Light load
20 dB
fp
0 dB
Heavy load
-20 dB
fz
frz
f rz
-40 dB
1Hz
10Hz
100Hz
1kHz
10kHz
100kHz
Figure 14. CCM flyback converter control-to output transfer function variation for different loads
40 dB
Loop gain T
40 dB
fp
fp
20 dB
fzc
20 dB
Heavy load
0 dB
0 dB
-20 dB
Control to output
fz
Light load
Compensator
fpc
fp
fc
frz
-20 dB
fz
-40 dB
1Hz
fz
10Hz
100Hz
1kHz
10kHz
100kHz
Figure 15. DCM flyback converter control-to output transfer function variation for different loads
-40 dB
1Hz
10Hz
100Hz
1kHz
10kHz
100kHz
10
APPLICATION NOTE
AN4137
ing the startup. While, too large a capacitor may increase the
startup time.
(b) Vcc resistor (Ra) : The typical value for Ra is 5-20. In
the case of multiple outputs flyback converter, the voltage of
the lightly loaded output such as Vcc varies as the load currents of other outputs change due to the imperfect coupling
of the transformer. Ra reduces the sensitivity of Vcc to other
outputs and improves the regulations of Vcc.
(36)
(37
(38)
(39)
11
AN4137
APPLICATION NOTE
- Summary of symbols Aw
Ae
Bsat
Co(n)
Dmax
Eff
fL
fs
Idspeak
Idsrms
Ids2
Iover
Isec(n)rms
ID(n)rms
Icap(n)rms
Io(n)
KL(n)
KRF
Lm
Llk
Losssn
Npmin
Np
Ns1
Ns(n)
Po
Pin
Rc(n)
Rsn
RL
Vlinemin
Vlinemax
VDCmin
VDCmax
Vdsnom
Vo1
VF1
Vcc*
VFa
VD(n)
Vo(n)
VRO
Vsn
Vsn2
Vsn
Vdsmax
12
APPLICATION NOTE
AN4137
Set-top Box
Output
Input voltage Output voltage (Max Current)
Power
Device
FSDM07652R
47W
5%
5%
5%
5%
5%
3.3V (2A)
5V (2A)
12V (1.5A)
18V (0.5A)
33V (0.1A)
85V-265VAC
85 V.rms
265 V.rms
Ripple
spec
60 Hz
Vo(n)
3.3
5
12
18
33
V
V
V
V
V
V
46.9 W
70 %
Io(n)
2.00
2.00
1.50
0.50
0.10
Po(n)
A
A
A
A
A
A
7
10
18
9
3
0
W
W
W
W
W
W
KL(n)
14
21
38
19
7
0
%
%
%
%
%
%
67.0 W
Maximum input power (Pin) =
The estimated efficiency (Eff) is set to be 0.7 considering the low voltage outputs (3.3V and 5V)
2. Determine DC link capacitor and DC link voltage range
DC link capacitor (CDC)
150 uF
min
min
Minimum DC link voltage (VDC ) =
92 V
(VDCmax)=
375 V
Since the input power is 67 W, the DC link capacitor is set to be 150uF by 2uF/Watt.
3. Determine Maximum duty ratio (Dmax)
Maximum duty ratio (Dmax)
(Vdsnom)
0.48
460 V
85 V
Dmax is set to be 0.48 so that Vdsnom would be about 70% of BVdss (650V
0.7=455V)
4. Determine transformer primary inductance (Lm)
Switching frequency of FPS (fs)
66 kHz
0.33
Ripple factor (KRF)
671 uH
Primary side inductance (Lm) =
Maximum peak drain current (Idspeak) =
RMS drain current
rms
(Ids )
K RF = 1 ( DCM )
K RF < 1 (CCM )
I EDC
2.01 A
1.07 A
##
K RF =
I
2 I EDC
375 V
13
AN4137
APPLICATION NOTE
5. Choose the proper FPS considering the input power and current limit
2.50 A
Typical current limit of FPS (Iover)
Minimum Iover considering tolerance of 12%
2.20 A
> 2.01
A
->O.K.
Since the maximum peak drain current (Idspeak) is 2.0A, FSDM07652R is chosen, whose current limit
level (Iover) is 2.5A. The current limit tolerance (12%) is considered.
6. Determine the proper core and the minimum primary turns
Saturation flux density (Bsat)
0.35 T
Cross sectional area of core (Ae)
Minimum primary turns
109.4 mm
(Npmin)=
43.8 T
VF(n)
# of turns
1.2 V
6.9 =>
7T
0.5 V
2 =>
2T
0.5 V
2.9 =>
3T
1.2 V
6.9 =>
7T
1.2 V
10 T
10.1 =>
1.2 V
18.0 =>
18 T
0V
0.0 =>
0T
Primary turns (Np)=
45 T
--->enough turns
2130 nH/T2
0.34631 mm
12
3.3
5
12
18
33
0
V
V
V
V
V
V
V
In general, the optimum turn ratio between 5V and 3.3V is 3/2, considering the diode forward voltage
drop.
Primary winding
Vcc winding
1st output winding
2nd output winding
3rd output winding
4th output winding
5th output winding
6th output winding
Copper area (Ac) =
Fill factor (KF)
Required window area (Awr)
Diameter
0.5
0.3
0.4
0.4
0.4
0.4
0.4
Parallel
1T
mm
mm
2T
mm
4T
mm
4T
mm
3T
mm
2T
mm
1T
mm
T
2
19.70 mm
0.15
rms
ID(n)rms
1.1
0.1
3.5
3.7
2.8
0.9
0.2
#####
A
A
A
A
A
A
A
A
(A/mm2)
5.44
0.71
6.97
7.30
7.30
3.76
1.55
#####
2
131.33 mm
Since the windings for 3.3V and 5V are short with small number of turns, relatively large current
densities (> 5A/mm2) are allowed. The fill factor is set to be 0.15 due to multiple outputs.
14
APPLICATION NOTE
AN4137
VD(n)
Vcc diode
1st output diode
2nd output diode
3rd output diode
4th output diode
5th output diode
6th output diode
70
20
29
70
103
184
0
V
V
V
V
V
V
V
A
A
A
A
A
A
A
Vcc winding
Co(n)
1st output capacitor
2nd output capacitor
3rd output capacitor
4th output capacitor
5th output capacitor
6th output capacitor
2000
2000
330
470
47
uF
uF
uF
uF
uF
uF
100
100
300
300
480
Icap(n)
m
2.9
m
3.1
m
2.3
m
0.8
m
0.2
m #####
A
A
A
A
A
A
Vo(n)
0.64
0.67
1.53
0.52
0.18
#####
V
V
V
V
V
V
Since the voltage ripples for 3.3V, 5V and 12V exceed the ripple spec of 5%, additional LC filter stage
should be used for these three outputs. 220uF capacitor together with 2.2uH inductor are used for the post
filter. To attenuate the voltage ripple caused by switching, the corner frequency of the post filter (fo) is set
at about one decade below the switching frequency.
fo =
1
2 L p1C p1
10 6
2 2.2 220
= 7.2kHz
4.5 uH
190
5
33.1
9.2
1.1
max
(Ids2) =
Peak drain current at VDC
1.75 A
VDCmax
(Vsn2)=
max
(Vds )=
V
%
0.185
nF
W (In Normal Operation)
172 V
547 V
The snubber capacitor and snubber resistor are chosen as 10nF and 33k
, respectively. The maximum
voltage stress on the MOSFET is designed to be 84% of 650V BVdss voltage of the FSDM07652R. The
actual Vdsmax would be lower than this.
15
AN4137
APPLICATION NOTE
DC gain =
zero (wz) =
RHP zero (wrz)=
pole (wp)=
2
5000 rad/s => fz=
694765 rad/s => frz=
2153 rad/s => fp=
5.6
18
1
1.2
33
47
1.2
nF
nF
796 Hz
110,631 Hz
343 Hz
vo1'
FPS
vFB
CB
vo1
RD
ibias
Rbias
iD
1:1
B
CF
R1
RF
KA431
R2
1,815 Hz
498 Hz
1,608 Hz
60
Gain (dB)
40
20
0
10
100
-20
-40
0
10
Phase (degree)
-30
-60
100
16 3.64105
25
3.63
40 3.60099
63 3.53167
100 3.36222
160 2.96516
250 2.20575
400 1000
0.89557
630 -0.6501
1000 -2.0185
1600 -2.9016
2500 -3.3275
4000
-3.5257
frequency
(Hz)
6300 -3.5983
10000 -3.6107
16000 -3.5697
1000
25000 -3.4485
40000 -3.1334
63000
-2.448
100000 -1.0745
41
37
33
29
25
21
18
15
13
11
9
6
3
-1
-5
-9
#
#
#
#
44.7
16 -2 -88.7
Control-to-output
40.9
25 -2
-88
36.8 Compensator
40 -4 -86.8
32.8 T (Closed
63loop
-6 gain)-85
28.7
100 -9 -82.2
24.4
160 ## -77.9
20.3
250 ## -72.2
15.9
400 ## 100000
-65.2
10000
12.1
630 ## -59.7
8.75
1000 ## -58.3
5.74
1600 ## -62.1
2.74
2500 ## -68.5
-0.8
4000 -8 -75.2
-4.5
6300 -7 -80.2
-8.4
10000 -8 -83.7
-12
16000 ##
-86
10000
100000
-16
25000 ## -87.5
-20
40000 ## -88.4
-23
63000 ##
-89
-26
1E+05 ## -89.4
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
-90
-120
-150
-180
frequency (Hz)
The control bandwidth is 4kHz. Since the crossover frequency is too close to the corner frequency of the
post filter (fo=7.2 kHz), the controller is designed to have enough phase margin when ignoring the effect of
the post filter.
16
APPLICATION NOTE
AN4137
Design Summary
For the FPS, FSDM07652R is chosen. This device has a fixed switching frequency of 66kHz. Startup and soft-start circuits
are implemented inside the device.
To limit the current, 10 ohms resistors (Ra and Rdamp) are used in series with Da and DR5. These damping resistors improve
the regulations of the very lightly loaded outputs.
Figure 17 shows the final schematic of the flyback converter designed by FPS Design Assistant.
VO5 33V
Rdamp 10
DR5
NS5
Co5
UF4004
47uF/ 50V
VO4 18V
DR4
NS4
EGP20D
470uF/25V
Rsn
CDC
10nF
1kV
Csn
Dsn
Cp3
Co3
220uF/ 25V
330uF/25V
Np
Lp2
DR2
150uF/400V
2.2 uH
EGP30D
NS3
33k
2W
VO3 12V
Lp3
DR3
GBLA06
Co4
VO2 5V
2.2 uH
SB560
NS2
Cp2
Co2
UF4007
220uF/ 10V
1000uF 2 /10V
6
Vstr
1.5nF/275Vac
CL2
Lp1
Vcc
GND
FB
Line Filter
(33mH)
Da
VO1 3.3V
2.2 uH
SB540
Cp1
Co1
NS1
220uF/ 10V
1000uF 2 /10V
Ca
33uF/35V
CL1
DR1
UF4003
R a 10
FPS
(DM07652R)
CL2
Drain
Na
1k
Rd
Rbias
0.47uF/275Vac
1k
H11A817A
5.6k
R1
RL1
CB
1.5M
NTC
5D-13
H11A817A
1.2k
47nF
RF
CF
33nF
Fuse
KA431
18k
AC line
R2
17
AN4137
APPLICATION NOTE
Experimental Verification
In order to show the validity of the design procedure presented in this paper, the converter of the design example has
been built and tested. All the circuit components are used as
designed in the design example and the measured transformer characteristics are shown in table 3.
Figure 18 shows the FPS drain current and DC link voltage
waveforms at the minimum input voltage and full load condition. As can be seen, the maximum peak drain current
(Idspeak) is 2A and the minimum DC link voltage (VDCmin) is
about 90V. The designed values are 2.01A and 92V, respectively.
Figure 19 shows the FPS drain current and voltage waveforms at the minimum input voltage and full load condition.
As designed, the maximum duty ratio (Dmax) is about 0.5
and the maximum peak drain current (Idspeak) is 2A.
Figure 20 shows the FPS drain current and voltage waveforms at the maximum input voltage and full load condition.
The maximum voltage stress on the MOSFET is about 520V,
which is lower than the designed value (547V). This is
because of the lossy discharge of the inductor or the stray
capacitance. Another reason is that the power conversion
efficiency at the maximum input voltage is higher than the
estimated efficiency used in step-1.
Core
Primary side
inductance
682 uH @ 70kHz
Leakage
inductance
Resistance
18
APPLICATION NOTE
AN4137
Efficiency
0.81
0.80
0.79
0.78
0.77
0.76
0.75
0.74
0.73
0.72
85
115
145
175
205
235
265
Input
voltage
Vo1
(3.3V)
Vo2
(5V)
Vo3
(12V)
Vo4
(18V)
Vo5
(33V)
85Vac
3.21 V
5.18 V
12.88 V
19.7 V
35.7 V
-2.7 %
3.6 %
7.3 %
9.4 %
8.2 %
3.21 V
5.14 V
12.77 V
19.4 V
34.6 V
-2.7 %
2.8 %
6.4 %
7.8 %
4.8 %
3.21 V
5.11 V
12.67 V
19.2 V
34.1 V
-2.7 %
2.2 %
5.6 %
6.7 %
3.2 %
3.21 V
5.09 V
12.57 V
19.1 V
33.8 V
-2.7 %
1.8 %
4.8 %
5.9 %
2.4 %
3.21 V
5.08 V
12.52 V
19.0 V
33.6 V
-2.7 %
1.6 %
4.3 %
5.4 %
1.9 %
3.21 V
5.07 V
12.48 V
18.9 V
33.5 V
-2.7 %
1.4 %
4.0 %
5.1 %
1.6 %
3.21 V
5.06 V
12.47 V
18.9 V
33.5 V
-2.7 %
1.2 %
3.9 %
5.1 %
1.4 %
115Vac
145Vac
175Vac
205Vac
235Vac
265Vac
19
AN4137
APPLICATION NOTE
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPROATION. As used herein:
www.fairchildsemi.com
1/13/04 0.0m 002
Stock#ANxxxxxxxxx
2003 Fairchild Semiconductor Corporation