MHL

26/2/2015

Xilinx FPGA
Configurable
Logic
Blocks
Block RAMs

Block RAMs

I/O
Blocks
Block
RAMs

Simplified view of a Xilinx Logic Cell

16-bit SR
16x1 RAM

a
b
c
d
e
clock
clock enable
set/reset

4-input
LUT

y
mux
flip-flop
q

Design process (1)

Specification
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be able
to perform an encryption algorithm by itself,
executing 32 rounds..

VHDL description (Your VHDL Source Files)

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Functional simulation

entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;

Synthesis

Post-synthesis simulation

Design process (2)

Implementation
(Mapping, Placing & Routing)
Timing simulation

Configuration

On chip testing

Logic Synthesis
VHDL description
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;
signal B1:STD_LOGIC;
signal Y1:STD_LOGIC;
signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
begin
A1<=A when (NEG_A='0') else
not A;
B1<=B when (NEG_B='0') else
not B;
Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;
MUX_1<=A1 or B1;
MUX_2<=A1 xor B1;
MUX_3<=A1 xnor B1;
with (L1 & L0) select
Y1<=MUX_0 when "00",
MUX_1 when "01",
MUX_2 when "10",
MUX_3 when others;
end MLU_DATAFLOW;

Circuit netlist

Mapping
LUT0
LUT4
LUT1

FF1
LUT5

LUT2
FF2
LUT3

Placing

FPGA

CLB SLICES

Routing
Programmable Connections

FPGA

 VHDL

MHL

26/2/2015

VHDL
VHSIC (Very High Speed Integrated Circuit)
Hardware Description Language

VHDL for Specification

VHDL for Simulation

VHDL for Synthesis

Entity Declaration
Entity Declaration describes the interface of the component,

i.e. input and output ports.

Entity name

Port names

Port type

ENTITY nand_gate IS
PORT(
a
: IN STD_LOGIC;
b
: IN STD_LOGIC;
z
: OUT STD_LOGIC
);
END nand_gate;

Reserved words

Port modes (data flow directions)

Semicolon

No Semicolon

Entity declaration simplified syntax

ENTITY entity_name IS
PORT (
port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
.
port_name : signal_mode signal_type);
END entity_name;

Architecture
Describes an implementation of a design entity.
Architecture example:

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;

Architecture simplified syntax

ARCHITECTURE architecture_name OF entity_name IS

[ declarations ]
BEGIN
code
END architecture_name;

Entity Declaration & Architecture

nand_gate.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a
: IN STD_LOGIC;
b
: IN STD_LOGIC;
z
: OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;

Library declarations
Library declaration
LIBRARY ieee;
USE ieee.std_logic_1164.all;

Use all definitions from the package

std_logic_1164

ENTITY nand_gate IS
PORT(
a
: IN STD_LOGIC;
b
: IN STD_LOGIC;
z
: OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;

Library declarations - syntax

LIBRARY library_name;
USE library_name.package_name.package_parts;

STD_LOGIC type demystified

Value

Meaning

Forcing (Strong driven) Unknown

Forcing (Strong driven) 0

Forcing (Strong driven) 1

High Impedance

Weak (Weakly driven) Unknown

Weak (Weakly driven) 0.

Models a pull down.

Weak (Weakly driven) 1.

Models a pull up.

Don't Care

Standard Logic Vectors

SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0);
.
a <= 1;
b <= 0000;
-- Binary base assumed by default
c <= B0000;
-- Binary base explicitly specified
d <= 0110_0111; -- You can use _ to increase readability
e <= XAF67;
-- Hexadecimal base
f <= O723;
-- Octal base

Structural VHDL

Structural Architecture (xor3 gate)

ARCHITECTURE structural OF xor3 IS
SIGNAL U1_OUT: STD_LOGIC;

I1
I2

COMPONENT xor2 IS
PORT(
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
U1: xor2 PORT MAP (I1 => A,
I2 => B,
Y => U1_OUT);
U2: xor2 PORT MAP (I1 => U1_OUT,
I2 => C,
Y => Result);
END structural;

Y
XOR2

A
B
C

XOR3

Result

U1_OUT

A
B

C
XOR3

RESULT

Component and Instantiation (1)

Named association connectivity (recommended)

COMPONENT xor2 IS
PORT(
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;
U1: xor2 PORT MAP (I1 => A,
I2 => B,
Y => U1_OUT);

For Generate Statement

For - Generate
label: FOR identifier IN range GENERATE
BEGIN
{Concurrent Statements} eg Port Map
END GENERATE;

ECE 545 Introduction

to VHDL

ARCHITECTURE structural OF or6 IS

SIGNAL temp: STD_LOGIC_VECTOR (0 to 3);

COMPONENT or5 IS
PORT(
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
U0: or2 PORT MAP ( I1 => A(0),
I2 => A(1),
Y => temp(0)
For i in 0 to 3 generate
U1: or2 PORT MAP ( I1 => A(i+2),
I2 => temp(i),
Y => temp(i+1)
end generate;

U0: or2 PORT MAP ( I1 => A(6),

I2 => temp(4),
Y => result
END structural;

For Generate
Statement
);

);

);

Conditional concurrent signal assignment

When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;

Value N
Value N-1

0
1

0
1

0
1

Value 2
Value 1
Condition N-1
Condition 2

ECE 545 Introduction

to VHDL

Condition 1

Target Signal

When - Else
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux_4X1
Port ( sel
a :
b :
c :
d :
y :
end test;

is
: in STD_LOGIC_VECTOR (1 downto 0);
in STD_LOGIC;
in STD_LOGIC;
in STD_LOGIC;
in STD_LOGIC;
out STD_LOGIC);

architecture Behavioral of Mux_4X1 is

Begin
Y <=

end Behavioral;

A when SEL = "00" else

B when SEL = "01" else
C when SEL = "10" else
D;

When - Else
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Mux_4X1
Port ( sel
a :
b :
c :
d :
y :
end test;

is
: in STD_LOGIC_VECTOR (1 downto 0);
in STD_LOGIC;
in STD_LOGIC;
in STD_LOGIC;
in STD_LOGIC;
out STD_LOGIC);

architecture Behavioral of Mux_4X1 is

Begin
Y <=

end Behavioral;

A when SEL = "00" else

B when SEL = "01" else
C when SEL = "10" else
D;

When - Else
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Mux_4X1
Port ( sel
a :
b :
c :
d :
y :
end test;

is
: in STD_LOGIC_VECTOR (1 downto 0);
in STD_LOGIC;
in STD_LOGIC;
in STD_LOGIC;
in STD_LOGIC;
out STD_LOGIC);

architecture Behavioral of Mux_4X1 is

Begin
Y <=

end Behavioral;

A when SEL = "00" else

B when SEL = "01" else
C when SEL = "10" else
D;

VHDL Example Half adder

library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port (x, y : in std_logic;
s, c : out std_logic);
end half_adder;
architecture dataflow_3 of half_adder is
begin
s <= x xor y;
c <= x and y;
end dataflow_3;

VHDL Example Full adder

library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port (x, y, z : in std_logic;
s, c : out std_logic);
end full_adder;
architecture struc_dataflow_3 of full_adder is
component half_adder
port (x, y : in std_logic;
s, c : out std_logic);
end component;
signal hs, hc, tc: std_logic;

VHDL Example Full adder

begin

HA1: half_adder
port map ( x => x,
y => y,
s => hs,
c => hc);
HA2: half_adder
port map ( x => hs,
y => z,
s => s,
c => tc);
c <= tc or hc;
end struc_dataflow_3;

Sites
www.xilinx.com
www.digilentinc.com