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EXISTING SYSTEM:
APPROXIMATE computing has become a promising technique to reduce the
power, area and delay constraints in VLSI design, albeit at the expense of a loss in
computational accuracy [1]. This technique is applicable to error tolerant
applications such as multimedia, mining and recognition [2]. Generally, there are
two methodologies for reducing accuracy by approximation. The first methodology
uses a voltage-over-scaling (VOS) technique for CMOS circuits to save power,
while also introducing errors into the circuit [3], [4], [5]. The second methodology
is based on redesigning a logic circuit into an approximate version. While the VOS
technique is applicable to most circuits for error-tolerant applications, an
approximate redesign requires to consider the different functionalities of logic
circuits. As one of the simplest, but key components of arithmetic circuits, adders
have attracted an extensive interest for redesigning and implementing approximate
schemes.
PROPOSED SYSTEM:
In this paper, an analytical framework is proposed to assess the arithmetic
accuracy, i.e. the error rate and mean error distance (MED), of approximate adders.
Three types of approximate adders are considered and their error features are
compared using the proposed analysis. The revealed error characteristics provide
insights into the quality of an appropriate adder for achieving a desired operational
accuracy. As an example of ASMs, the PSNR in image processing is considered. A
model is presented for estimating the PSNR from the MED obtained from the
proposed framework; experimental results show that the estimated PSNRs are very
close to the PSNRs obtained by simulation. The utilization of the proposed
framework to PSNR estimate provides an analytical approach for assessing and
designing a feasible approximate image processing system based on approximate
adders. The major contributions of this paper are as follows:
An analytical framework is developed for modeling and evaluating
the error characteristics of three types of approximate adders found in
the
technical
literature.
Fig. 3. Block diagram of error-tolerant adder type II. n: the adder size; k: half of
the maximum carry chain length.
SOFTWARE IMPLEMENTATION:
Modelsim 6.0
Xilinx 14.2
HARDWARE IMPLEMENTATION:
SPARTAN-III, SPARTAN-VI