Lab Report Name Here

Summer 2014, CPE 133-80

LabPartner 1, LabPartner2

Top Level Block Diagram

Part 1
Figure 1 below shows the top level block diagram of the circuit for the example lab
report. The circuit takes in inputs A and B (from the switches) and performs
different operations of the inputs depending on which button is pressed. If button 0
is pressed, A and B is displayed, if button 1 is pressed, A or B is displayed, if button
2 is pressed, A xor B, and if button 3 is pressed A xnor B is displayed on the seven
segment display.

Figure 1: Top Level Block Diagram

Part 2

Structural Model
Figure 2 below shows the structural model for the circuit of the example lab report.
The circuit consists of a process, My_proc, that handles selecting what data to be
displayed, the component, sseg_dec, which acts as a binary to seven segment
decoder, and a mux, which selects whether or not the seven segment display
should be on or off.

Lab Partner 1
Lab Partner 2

Lab Name Here

CPE 133-80
Summer 2014

Figure 2: Structural Model

iSim Testing
Table 1 shows the test cases used to test the operation of our Lab 0 circuit. Test
cases 2->5 show the testing of each individual button without changing the input
and test cases 1 and 8 show the result of no button pressed. Test case 6 shows the
result of changing the input while the same button is held. Test case 7 shows
button 2 has precedence over button 3 if both buttons are pushed. Additional test
cases could be used to show correct button precedence for all buttons. These test
cases were not included in the iSim test, but were tested visually on the board.
Figure 3 shows the isim output of all test cases showing the outputs, display_en and
data match those expected outputs in Table 1. Because the iSim output matches
the expected output and because our demo on the board also matched the
expected output, we feel our circuit is working properly.
Table 1: Test Cases for Lab0

Test
Case
1
2
3
4
5
6
7
8

Time

INPUTS
A

Buttons

0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns

0000
1100
1100
1100
1100
1100
1100
1100

0000
0101
0101
0101
0101
1111
1111
1111

0000
0001
0010
0100
1000
1000
1100
0000

EXPECTED OUTPUTS
Data
Display_En
(decimal)
0
0
4
1
13
1
9
1
6
1
12
1
3
1
0
0

Lab Partner 1
Lab Partner 2

Lab Name Here

CPE 133-80
Summer 2014

Figure 3: iSim waveform output

Conclusion
Lab Partner 1
In this weeks lab, I gained an appreciation of using structural modeling. It is super
cool to be able to make use of modules already made (either by me or someone
else) and connect them together, with some added functionality, into a new circuit.
I can appreciate the technique of modular and hierarchical design because I see
how having a toolbox of simple modules makes designing larger and more complex
modules more feasible. I am also now feeling much more comfortable with using
the Xilinx design suite and the VHDL language. Finally, I was able to practice my
understanding of bit operations (and, or, xor, and xnor) and my ability to convert
binary to decimal.
Lab Partner 2
Insert conclusion here.

Answers to Questions

Code
----------------------------------------------------------------------------------- Engineer: Bridget Benson
-- Create Date:
14:26:39 06/13/2014
-- Target Devices: Digilent Nexys 2
-- Description: This module is a dummy module for use int he lab report template.
-- It reads the status of four buttons and 8 switches, the
-- left four switches being called 'A', and the right four switches called 'B'
-If no buttons are pressed, nothing is shown on the SSEG display
-If button 1 is pressed, the result of A and B is shown

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-If button 2 is pressed, the result of A or B is shown

-If button 3 is pressed, the result of A xor B is shown
-If button 4 is pressed, the result of A xnor B is shown
-The order of button precedence is 1, 2, 3, 4
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TopModule is
Port ( Buttons : in STD_LOGIC_VECTOR (3 downto 0);
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
CLK : in STD_LOGIC;
SSEG : out STD_LOGIC_VECTOR (7 downto 0);
EN : out STD_LOGIC_VECTOR (3 downto 0));
end TopModule;
architecture Behavioral of TopModule is
-------------------------------------------------------------------------- Components
------------------------------------------------------------------------component sseg_dec is
Port (
ALU_VAL : in std_logic_vector(7 downto 0)
SIGN : in std_logic;
VALID : in std_logic;
CLK : in std_logic;
DISP_EN : out std_logic_vector(3 downto 0);
SEGMENTS : out std_logic_vector(7 downto 0));
end component;
-------------------------------------------------------------------------- Signal Declarations
------------------------------------------------------------------------signal data
signal display_en
signal disp_en_sseg

: std_logic_vector (7 downto 0);

: std_logic := '0'; --initialize display to be off
: std_logic_vector (3 downto 0);

begin
-------------------------------------------------------------------------- Port Maps
------------------------------------------------------------------------sd1: sseg_dec port map (
ALU_VAL
=> data,
SIGN
=> '0', --no signed numbers
VALID
=> '1', --always valid
CLK
=> CLK,
DISP_EN
=> disp_en_sseg,
SEGMENTS
=> SSEG);
-------------------------------------------------------------------------- Logic
------------------------------------------------------------------------process (A, B, Buttons)
begin
if (Buttons(0) = '1') then
data <= "0000" & (A and B);
display_en <= '1';
elsif (Buttons(1) = '1') then
data <= "0000" & (A or B);
display_en <= '1';
elsif (Buttons(2) = '1') then

Lab Partner 1
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CPE 133-80
Summer 2014

data <= "0000" & (A xor B);

display_en <= '1';
elsif (Buttons(3) = '1') then
data <= "0000" & (A xnor B);
display_en <= '1';
else
data <= "00000000"; -- doesn't matter, as the display will be off
display_en <= '0';
end if;
end process;
EN <= disp_en_sseg when display_en = '1' else
"1111"; -- turn all displays off
end Behavioral;
----------------------------------------------------------------------------------- Engineer: Bridget Benson
-- Create Date:
14:26:39 06/13/2014
-- Target Devices: Digilent Nexys 2
-- Description: This module tests the design used in the Lab Report Template
---------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TopModuleTest IS
END TopModuleTest;
ARCHITECTURE behavior OF TopModuleTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TopModule
PORT(
Buttons : IN std_logic_vector(3 downto 0);
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
CLK : IN std_logic;
SSEG : OUT std_logic_vector(7 downto 0);
EN : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal Buttons : std_logic_vector(3 downto 0) := (others => '0');
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal CLK : std_logic := '0';
--Outputs
signal SSEG : std_logic_vector(7 downto 0);
signal EN : std_logic_vector(3 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)

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Lab Name Here

CPE 133-80
Summer 2014

uut: TopModule PORT MAP (

Buttons => Buttons,
A => A,
B => B,
CLK => CLK,
SSEG => SSEG,
EN => EN
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 20 ns; -- should see display_en as '0'
-- insert stimulus here
A <= "1100";
B <= "0101";
Buttons <= "0001"; --expecting "0100" or 4
wait for 20 ns;
Buttons <= "0010";
wait for 20 ns;

--expecting "1101" or 13

Buttons <= "0100";

wait for 20 ns;

--expecting "1001" or 9

Buttons <= "1000";

wait for 20 ns;

--expecting "0110" or 6

B <= "1111";
wait for 20 ns;

--expecting "1100" or 12

Buttons <="1100";
wait for 20 ns;
Buttons <= "0000";
wait;
end process;
END;

--expecting "0011" or 3
--expecting no display and value zero