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# 1.

The entire past history of inputs is preserved by the network, as internal information that is referred to as
a) Next State
b) Pervious State
c) Excitation State
d) Present state
2. With p bits, the number of states s that can be coded is given by
a) 2p+1 < s 2p

b) 2p-1 < s 2p

c) 2p-1 < s 2p

d) 2p+1 > s 2p

3. _______ and the logic values needed at its input terminals to achieve necessary transitions.
a) Latches

b) Shift Registers

c) Flip Flops

d) Gates

## 4. Concept Combinational circuit

a) Generate O/P based on I/P

b) generate I/P based on O/P c) generate I/P & O/P d) All the above

## 5. Number of rows in a transition table for a P state variable is _______.

a) log P
b) e P
c) 2 P
d) P 2
6. For a given input state if the next state Yi and the present state yi are unhinged then
a) Yi <yi

b) Yi > yi

c) Yi = yi

d) Yi yi

7. As long as the network is uneven and the input state is not changed, then after a time delay the
a) Next state act as present state

## d) pervious state as present state

8. A special flow chart that has been developed specifically to define _________________ is called an ASM
chart of
a) Digital Software Algorithm

## b) Digital Hardware algorithm

d) b) & c)
9. ___________ is a description for the terminal behavior of a clocked synchronous sequential network.
a) State Diagram

b) State Table

c) State Reduction

d)

State Assignment

## 10. The characteristic equation of JK Flip Flop is _______.

a) J Q K Q

b) J Q K Q

c) J Q K Q

d) J Q K Q

11. A sequential circuit with two D flip-flops A and B, and one input X is specified by the following input
equations: and What are the next states of the flip-flops A and B if the present state of the flip-flops A, B and
the input X equals, 001, 110 respectively:
a) 11, 00
b) 10, 00
c) 00, 10
d) 01, 00
12. In state assignment, the following conditions are satisfied in three rules:
Rule I: (B,G)(2X),(C,F),(D,H)(2X),(A,E)
Rule II:(A,B),(B,C)(3X),(D,E),(F,G)(2X),(D,H)
Rule III: (D,F),(E,G) determine the state-assignment map

a) Q1

b) Q1

c) Q1

d) Q1

0
1

00
A
B

0
1

00
A
E

0
1

00
A
E

0
1

00
B
C

Q2Q3
01
11
F
C
G
H
Q2Q3
01
11
B
C
G
F
Q2Q3
01
11
C
B
F
G
Q2Q3
01
11
G
F
H
D

10
E
D
10
H
D
10
H
D
10
A
E

13. Generating output based on present input variables and pervious input variables is referred as
a) Synchronous Circuit

b) Sequential Circuit

c) Combinational circuit

d) Asynchronous Circuit

a) Counters

b) Multiplexers

## c) Un clocked Flip Flop

d) TimeDelay Circuits

15. Minimum number of the inputs that are necessary to generate a particular next state variable is
a) State table
16.

a)

b) Present state

c) Excitation state

d) Transition State

For the clocked synchronous network shown in the figure. Determine the type of circuit also
construct the i) Excitation table ii) Transition table iii) State table iv) State diagram.

(Or)
b)

Illustrate with suitable example and explain the structure and operation of Asynchronous Sequential
Network.

17. a) Describe the modeling of clocked synchronous sequential network and explain the relationship of
ASM

## charts and state diagrams

(Or)

b)

Obtain a minimal state for a clocked synchronous sequential network having a single input line x, in
which the symbol 0 and 1 are applied, and a single output line z. An output of 1 is to be produced

coincident with each third multiple of the input symbol 1. At all other times the network is to produce 0
outputs. An example of input/output sequences that satisfy the conditions of the network specifications is
x=01101011110001110
z=00001000100000100
18. a) Design and analyze the Asynchronous Sequential Network for the given logic diagram
Y1
X
Y2

(Or)
b) Explain the behavior of the clocked synchronous sequential network is described and discuss the state
table reduction method with example.