IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO.

3, MARCH 2014

Asymmetric Aging: Introduction and Solution for

Power-Managed Mixed-Signal SoCs

691

Degradation variations across load/slew space

for a combinational cell
14.00

Palkesh Jain, Frank Cano, Bapana Pudi, and N. V. Arvind

12.00
10.00
8.00
6.00
4.00
400
200
100
50

2.00

252.00

227.00

56.64

28.32

7.08

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14.16

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113.29

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25
Cell Input
Slew (AU)

DelayDegradation

Abstract A detailed introduction to the problem of asymmetric aging

of mixed signal CMOS circuits is given in this paper, with special focus
on clock skew, pulse width, and aspects of burn-in. A comprehensive
look into the origin and aggravation of the problem due to power
management techniques is presented. Additionally, various asymmetric
aging analyses and management techniques, including conventional
timing analysis frameworks, are shared. For the first time, problem
formulation and desensitization schemes in a statistical framework are
presented. Subsequently, design guidelines are shared that can be applied
on production clock designs to significantly alleviate the asymmetric
aging problem. Several of these techniques must be applied to advanced
production designs to enable higher performance and integrity.

Operating Load (AU)

Index Terms Aging, asymmetric aging, clock tree, negative bias

temperature instability (NBTI), skew.

Fig. 1. Representative impact of NBTI aging on a simple circuit when

operating under different load and slew conditions.

I. I NTRODUCTION

the analysis techniques, and then providing results from production

designs and clock strategies.

Bias temperature instability (BTI), or gradual degradation of

CMOS transistors in the ON state, is a dominant product aging
mechanism. Its analysis [specifically for negative BTI (NBTI)] and
containment, in the form of process corrections, guard bands, designs
margins, and techniques, has been an integral part of the chip making
process during the last decade [1][4].
Nonetheless, the prevalent commercial analyses and optimization
techniques for chip making are not aware of a critical paths sensitivity to NBTI and, in turn, may leave hot spots in the design
even after optimization [5], [6]. Furthermore, transistor degradation
as a phenomenon is strongly dependent on the operating voltage,
temperature, and ON time of a transistor. Clearly, with increasing
use of power management techniques, such as clock gating or power
gating, different transistors on a chip do indeed age asymmetrically.
Such asymmetric aging worsens clock skew and causes timing
failures. It should also be noted that, while adaptive design techniques
do compensate for the generic aging across the chip, they are
incompetent in handling the asymmetric aspect of the problem. This
is primarily due to the cost of becoming too granular or incurring
further skew due to correction of a degraded pMOS in a CMOS
circuit [2].
Naturally, it is demanded from the analysis methodology to be
aware of a designs sensitivity to NBTI itself and to rigorously
analyze and correct for asymmetric aging. In this paper, we present
comprehensive schemes for carrying this out. One proposed analysis
solution builds on the existing commercial framework of static timing
analysis (STA) methodology (with degraded and fresh models), while
the other way to handle the problem is through incorporating NBTI
awareness in the statistical STA (SSTA) framework. The proposals
are apt for an increasingly fabless world, where several third-party IPs
may be integrated on a chip that is designed with different constraints.
We now begin with a quick recap of NBTI handling, moving on to
Manuscript received September 3, 2012; revised December 14, 2012;
accepted February 5, 2013. Date of publication March 27, 2013; date of
current version February 20, 2014.
P. Jain, B. Pudi, and N. V. Arvind are with the CMOS Design Backplane Group, Texas Instruments India, Bangalore 560093, India (e-mail:
palkesh@ti.com; b-pudi2@ti.com; aravind@ti.com).
F. Cano is with the Advanced CMOS Ramp Team, Houston, TX 77058
USA (e-mail: f-cano@ti.com).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2013.2251022

II. H ANDLING NBTI AGING IN D IGITAL D ESIGNS : R ECAP

Beginning from application of chip-level timing margins to counter
the effect, today there are commercially available sophisticated tools
to understand the exact impact of aging based on the stress time, pattern, activities, voltage, temperature, and associated recovery [5], [6].
Without loss of generality, the fundamental aspects of NBTI
degradation can be understood through a much simpler method of
applying a degraded SPICE model [also referred to as End-of-Life
(EoL)]. Such a model can be derived from dc or ac considerations [3].
To elucidate, Fig. 1 presents the output rise-delay degradation map
from a standard AND gatea two-stage circuitwith rising input,
falling internal stage, and rising output. It can be noted that increasing
input slews bring in higher contribution of the intermediate pulldown,
causing the net rise-delay degradation to be lower. On the other
hand, increasing operating load requires a higher contribution from
the degraded output pull-up action, thus increasing the net rise-delay
degradation impact. Such an asymmetry is already captured through
the above techniqueseither a simple Vth shift or a more involved
voltage-based method [5], [6].
The strong dependence of the impact of degradation on the operating load and slew conditions also indicates the inherent asymmetric
degradation among the rise and fall edges of the same circuit and
different circuits. Indeed, such a response of cells to degradation
at different operating loads/slew conditions is already exploited by
optimizers and timers today to meet entitlement, when doing the
timing analysis with libraries created with EoL models.
III. A SYMMETRIC AGING : P ROBLEM I NTRODUCTION
From the foregoing discussion, it is evident that the existing
techniques are well equipped to comprehend the dependencies on
operating loads, slews, and realistic activities to some extent. Moreover, with increasing confidence in NBTI recovery, the generic
NBTI degradation is less of a concern.
However, a more serious problem is power-management-induced
asymmetric aging. Techniques such as multivoltage islands naturally
create an asymmetry in the stress due to differences in the stress
voltage and, in fact, can result in significant differences in the delay
degradations of interacting paths. As an example, since NBTI has
a power-law stresstime dependency [1], [2], even a domain that is
ON only for 5% of the total lifetime may incur up to 40% of the
degradation as compared to an always-ON domain. Thus, the exact

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See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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TABLE I
VARIOUS S CENARIOS OF A SYMMETRIC A GING IN P OWER -M ANAGED SoC
Power Managed
Mode

Transistor Stress
Details

Voltage domain

Different stress
voltage

Standby/ power
gate

Power down mode

for power
management

DVFS

Stress and measure

conditions different

Clock gating

Half-cycle paths

Gating clock portions

while others free
running
Using both the edges
of the clock to save
power

Impact to Transistor
After a Sufficiently
Long Time

Fresh

Aged

Fresh

Aged

Fresh

Aged

Clock A

Clock B

Significant difference
in delay degradations
(10% skew)
Additional 2 delay
degradation at lower
OPP

Clock C

Significant skew and

pulse width issues
Extreme sensitivity to
clock-skew and pulse
width

Fig. 2.
Schematics and degradation maps of (Clock A) free running,
(Clock B) gated-high, and (Clock C) a gated-low clock along with fresh/aged
waveforms for each case.

IV. A SYMMETRIC AGING I NDUCED S KEW: I NTRODUCTION

Based on the foregoing discussion, three clock scenarios are of
importance to study: free running, gated high, or gated low configurations. Accordingly, Fig. 2 illustrates different clock configurations
realized from standard buffers when undergoing different stress types.
Naturally, for a simple free-running clock of Fig. 2, i.e., Clock
A, all pMOS transistors undergo ac NBTI degradation for one-half
of the total circuit lifetime. On the contrary, for the gated at logic
high clock, i.e., Clock B, only one-half of the transistors degrade
in a dc fashion for the entire circuit lifetime. If such a gated clock
starts toggling post stress (at the end of life), it is easy to see that
only the rising edge propagation degrades. A contrary argument holds

Normalized Delay Degradation (%)

impact of different power-managed scenarios (shutdown or different

voltage domains) must be carefully computed.
Furthermore, techniques like dynamic voltage frequency scaling,
which relies on changing the operating conditions based on work
load, present challenges based on the headroom and stress dynamics [1]. Indeed, the asymmetric stress incurred at higher voltages
results in a much higher impact when the circuit switches to a lower
voltage point because of headroom effects. As an example, when
a circuit stressed at a higher voltage is forced to operate at 15%
lower voltage, the degradation impact could be about 25% more. The
situation is further complicated by techniques such as power gating
and standby, where the degradation through certain circuit blocks can
be negligible. Such a scenario can potentially create a large skew
among interacting paths.
Furthermore, many modern circuits depend heavily on techniques
such as clock gating, which directly results in an asymmetric stress
on the gated portion of the clock versus the free-running portion.
Finally, among various power-managed scenarios, a very promising
one of combining gated clocks with dual edge operations poses even
larger challenges, as it requires a very tightly controlled clock duty
cycle [2]. Needless to say, such asymmetric aging design scenarios,
as presented in Table I, need very careful and involved analysis
and solution strategies, which, in our opinion, are missing from
the existing literature. To our knowledge, this is the first attempt
to comprehensively address the above aspects.
It should be noted that, although the problem of asymmetric aging
in clocks has been touched upon before, its holistic solution in the
power-managed context has been missing [2], [9]. Also, the existing
STA techniques are simply incapable of addressing the asymmetric
aspect of the problem because of their inability to distinguish between
degrading edges. While the voltage-induced aspects of the problem
are also important, clock integrity is of prime importance in modern
digital circuits. Therefore, in subsequent sections, we will specifically
look at asymmetric aging from the clock perspective.

Rising Edge
Falling Edge
Average

0
100% Gated
Low

~70% Gated
Low

~ Free
Running

~ Free
Running

~70% Gated
High

100% Gated
High

Gating Extent (Gated Low to Free Running to Gated High)

Fig. 3. Impact of clock-gating extent on the rising/falling edge degradation.

true for Clock C. Indeed, such a behavior leads to experimentally

observed skew built up between the interacting clocks as well as
pulse-width (PW)/duty-cycle distortion of the gated clocks. As a
result, duty-cycle-sensitive circuits (e.g., memories) can fail. In real
circuits, the launch and capture clock can potentially be gated at
different logics, which induces significant skew and directly affects
the hold and the maximum operation frequency. Alternatively, even
if the launch and capture clock gets gated at similar logic, but the
circuit happens to be half-cycle based, it brings in a skew. Fig. 3
shows the impact of the nature and extent of gating on the propagation
delay through the circuit (based on RelXpert simulations). The x-axis
highlights the gating extent to go from 100% at logic low (left) to
100% at logic high (toward extreme right). Clearly, it can be seen that
for a fully gated high (or low) case, only one of the edges degrades.
For the free-running case on the contrary, this magnitude is almost
halved.
A. Burn-In Impact With Gated Clocks
Interactions of NBTI with product burn-in (BI) are of significant interest. NBTI, as a phenomenon, is strongly voltage- and
temperature-accelerated, and both the stress parameters are severe
during the product BI. It has been experimentally shown that a
few hours of BI can induce as much as 60%70% of the total
stress, which is specified by the foundry over the entire lifetime.
However, if the clocks are chosen to remain predominantly gated
in BI to control test power, it could be detrimental since a high
stress condition induces a much higher skew. Moreover, on the other
hand, free-running clocks during BI ensure that sufficient amount
of degradation happens through all the transistors, thereby reducing
down the extent of any asymmetry. Consequently, the BI patterns
need to be very judiciously chosen, which otherwise (e.g., vectors
that lead to some clocks to be fully gated) can pronounce the basic

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 3, MARCH 2014

693

weakness of the design against asymmetric aging. However, it must

be noted that, with process maturity, as the product gets out of BI, the
real design weakness is exposed, making it important to safeguard
against asymmetric aging.
It is also critical to incorporate the PBTI perspective, which only
aggravates the situation. As an example, looking at Clock B in Fig. 2,
it can be seen that gating the circuit at logic high also degrades
all the critical nMOS transistors that take part in the critical-edge
propagation.
V. A SYMMETRIC AGING A NALYSIS : S KEW H ANDLING
Moving on from the various aspects of asymmetric aging in clocks,
we now look at the analysis and design techniques.

Fig. 4. Timing block highlighting the clustering concept and degradation

based on clock gating and inversion.

A. Skew and Conventional STA-Based Handling

the cell delays (now separated as rise and fall) to rise and fall NBTI
parameters, as in (2) and (3)

As discussed, for all practical purposes, gated clocks are the ones
that are most affected by asymmetric aging. Notably, for a buffer
based clock tree:
1) a clock gated-low or power-gated domain driving an active
(ungated or gated-high, but enabled) domain can experience
hold failure as the rising edge of the capture clock ages while
the launchs rising edge remains essentially unaged;
2) an active domain driving an inactive domain can experience
setup failure as the rising edge of the launch clock degrades,
whereas the rising edge of the capture clock remains unaged;
3) the falling edge logic has similar relationships, i.e., falling edge
launch risks setup and falling edge capture carries hold risk.
Theoretically, multitudes of aging combinations are possible
between two interacting clocks. In practice, however, a simple guidance can be prepared for limited cases for conventional STA-based
handling.
B. SSTA-Based Problem Formulation and Desensitization
As a next step, we now share exploiting the SSTA infrastructure
for asymmetric aging analysis and, furthermore, desensitization of
the design to extreme NBTI degradation.
1) Basic Formulation: In a simplistic manner, the basic formulations of SSTA can be extended to incorporate transistor degradation
by assigning a unit threshold voltage shift to the pMOS transistors and
computing the sensitivities of the delay to this shift, as in (1). Here, d
is the edge delay (rising/falling), vari is the regular statistical variation
parameter, and ki is the paths sensitivity to that. For example, kn
indicates path-delays sensitivity to threshold voltage shift due to
NBTI
(1)
d = d0 + k1 var 1 + kn Vth,NBTI.
The above method can easily be extended to the case where different
transistors within a circuit get assigned with different threshold
shifts based on the circuit-level activity. Importantly, while doing
the statistical timing at the block level, the tool can readily print out
the cumulative sensitivity of the entire path [7]. The slack sensitivity
of the path to the NBTI parameter can be used to identify and fix
NBTI-sensitive paths. The changes in the operating conditions of the
circuit (due to voltage/temperature) can also be accounted for through
an equivalent-time computation model, which computes a stress time
under reference conditions, such that the degradation induced is the
same as that of the original stress applicable for the original stress
time [2].
2) Asymmetric Aging Analysis: The above formulation, however,
cannot be employed for asymmetric aging, wherein different circuit
elements undergo different degradation. This brings up a need to
differentiate NBTI impact to rise and fall delays of a cell when it
is in different aging states. Therefore, we extend the above method
to assign two variables for individually capturing the sensitivity of

drise = dr0 + kr1 var1 + krn Vth,NBTI,rise

dfall = d f 0 + k f 1 var 1 + kfn Vth,NBTI,fall .

(2)
(3)

It can be noted that krn and kfn are, respectively, equal to the
NBTI sensitivity parameter as obtained through (1). Note that, for
asymmetric aging analysis, NBTI_rise/fall parameters always take
complementary valueshigh or zero. For example, a standard buffer
in the clock tree with gated-high stress should be set with the
NBTI_rise parameter as high, and, conversely, for a buffer in a gatedlow clock tree. The next step is to clusterize the circuit so as to
group the identically degrading instances together. As an example,
unless an inverting logic exists between two clock gates, the entire
clock sub-tree between them degrades alikeonly one of the edges
will degrade. On the other hand, if an inverting logic does exist, the
cluster needs to be distributed into two small clustersfrom first
clock gate to the inverting logic, and from the inverting logic to the
second clock gate.
A sample application of above method is shown through a fairly
complex timing circuit of Fig. 4. The circuit has been distributed
into clusters that degrade in the same manner. An SSTA run with
this definition of clusters and parameter assignment provides slack
results in the parameterized form.
A path-based analysis can then be employed to determine the worst
case assignments of NBTI parameter values that minimizes the slack,
as shown in Table II.
The key advantage of using an SSTA formulation is that it
facilitates the option of a bounded graph-based analysis (apart from
parameter sensitivities being an analysis byproduct), thereby also
ensuring exhaustive coverage of all paths. Furthermore, Table III
compares the results as obtained from a regular aging analysis versus
the approach outlined above.
We note that, for a 1 frequency degradation estimate through
regular aging analysis, up to 3 frequency degradation can happen in
the asymmetric aging case. The linear relationship between insertion
delay and frequency degradation can also be seen. Summing up,
Fig. 5 highlights the overall analysis flow.
3) Results From Production Design: We now present the results
from using the above methods on several advanced power-managed
designs. As can be seen from the Table IV, application of such a
method results in several new violations as compared to the regular
timing. A detailed analysis of the violations and the clock tree was
separately done to realize the nature of violations and the exact aging
of certain portion of the clock trees.
For one such design, a pre- and post-BI shmoo is plotted in Fig. 6,
which shows a post-BI Vmin wall. Indeed, detailed analysis reveals
the impact of asymmetric aging during BI on the failing paths.
While, typically, Vmin walls are associated with hold failures, in
this particular instance peculiarly, asymmetric aging creates a case
of setup failure doing this. A detailed study revealed the case of a

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TABLE II
VARIOUS C OMBINATIONS OF A GE A SSIGNMENTS FOR O BTAINING P RACTICALLY W ORST P OSSIBLE A GING
Cluster 1
R1
F1
0
0
1
1
1
0

1
1
1
1
1
1
1
1

Cluster 2
R2
F2
0
0
1
1
X
X

1
0
0
1
0
1
1
0

Cluster 3
R3
F3
0
0
1
1
X
X

1
0
X
X
0
1
X
X

Cluster 4
R4
F4
0
0
1
1
X
X

0
1
X
X
1
0
X
X

Comment
All clusters at time zero (no aging)
No gating enabled free running clock
Invalid as R1 and F1 are fully correlated

Worst combination for setup between flop 2, 3

Worst combination for setup between flop 1, 2
No impact after nnon-critical hold in flop 2, 3
Worst combination for hold between flop 1, 2

TABLE III
H IGHLIGHTING THE E XTENT OF A SYMMETRIC -AGING -I NDUCED F REQUENCY D EGRADATION

Fig. 5.

Interaction (t0 min

clock per required)

Frequency Degradation Estimates with:

Representative Existing Method

Proposed Method, within SSTA

Flops 1, 2 interact
[t = 0 500 ps]

EOL min. clock period required =

(1100 ps + 550 ps 1100 ps) = 550 ps
assuming 10% degradation Frequency
degradation = 10%

Gate 0 remains at logic 0 EOL min.

clock period required = (1100 ps +
550 ps 1000 ps) = 650 ps
Frequency degradation = 30%!

Flops 2, 3 interact
[t = 0 1000 ps]

EOL: (1100 ps + 1650 ps) (1650 ps)

= 1150 ps
Frequency Degradation = 10%

EOL: (1100 ps + 1650 ps) (650 ps +

500ps + 650 ps) = 1300 ps Frequency
degradation = 30%!

Overall flow diagram, from library to timing analysis level.

Fig. 6. Pre- and post-BI shmoo plots for a production design, highlighting
asymmetric-aging-induced setup failure and inadequacy of existing method.

TABLE IV
R ESULTS FROM P RODUCTION D ESIGNS
Design details
(28 nm)
Design A
Design B
Design C

Timing violations without

asymmetric aging
724
617
788

Violations with
asymmetric aging
938
631
958

failure on a multiclock constrained circuit, in which the secondary

clock is internally generated through self-timed paths. Asymmetric
aging on such self-timed paths during BI prompts an early trigger of
secondary clock, eventually leading to setup failures. The described
analysis method has been used to identify and fix more such paths.

Fig. 7. Stage-wise PW degradation in a long insertion delay path. Inset

shows the timing waveforms resulting in PW degradation.

VI. A SYMMETRIC AGING M ANAGEMENT: P ULSE W IDTH

Traditionally, designers ensure that the PW requirements are met,
both at time-zero and EoL scenarios. For balanced clock network,
rise and fall degradations remain similar with uniform aging, thus
incurring minimal PW degradation at EoL. However, as described
in the foregoing sections, clock gating results in nonuniform aging,
thereby causing differential rise/fall degradations and PW variation.
It is important to note that the PW at EoL is a strong function
of rise/fall degradations, t = 0 PW and the insertion delay. Fig. 7
describes stage-wise PW degradation in a long insertion delay path

on one of the 28-nm design blocks for two aging cases: (a) free
running and (b) asymmetrically aged while being gated at logic 1.
Clearly, in such a case, large PW degradations can be observed for
the gated clock.
In reality, for a production design, convolved effects of PW
requirement as well as degradation can happen. As an instance,
Fig. 8 shows the shmoo data (post-BI) for a device under two
test conditions, while the pre-BI shmoo data for both the patterns
remained standard with linear slope.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 3, MARCH 2014

(a)

(b)

Fig. 8. Post-BI shmoo data for a production design with two test patterns.
(a) With high activity. (b) With low activity.

695

to effect similar degradation on both the edges. Needless to say, halfcycle paths and inverter-based clock trees will need further special
considerations, and various implementations are possible to realize
the above intents.
VIII. C ONCLUSION
In this paper, a detailed introduction to asymmetric NBTI aging
was given with special focus on clock skew and pulse width,
along with aspects of BI. We noted that various power management
techniques could be detrimental from the NBTI perspective. Analysis
and management techniques for the problem were shared, including
conventional STA procedures, and a detailed problem formulation
and desensitization scheme in SSTA framework was presented.
Additionally, data from production designs was shared to highlight
the inadequacy of existing analysis techniques, resulting in failures.
ACKNOWLEDGMENT
The authors would like to thank R. Venkatraman and P. Rana
(and the respective design teams) for helping with shmoo data from
different products.
R EFERENCES

Fig. 9. Minimum PW (MPW) requirements for robust flop operation under

different operating voltages and stress types (free running and asymmetric).

In this particular case, we see the effects of multiple mechanisms

contributing to failure. First, the clock PW goes bad because of
asymmetric aging (post-BI). Second, the capture flops have their
own PW requirement, which obviously degrades with: 1) reducing
voltage and 2) with the asymmetric aging of the flops themselves.
Indeed, Fig. 9 shows the PW requirement trajectories for the flop
when aged in a regular manner versus asymmetric aging. Clearly,
under asymmetric aging stress mode, the PW requirement becomes
very high.
Finally, the operating voltage at the flops becomes critical, as
this PW requirement depends steeply on the voltage. Indeed, for
the shmoo plot Fig. 8(a), the high-activity test patterns create
much higher IR drop, reducing the effective voltage at the flops
and degrading the PW requirement aggressively. Note that reduced
operating voltage directly means a reduced headroom [1], [2]. Indeed,
such an aging scenario was not caught with the traditional analysis,
being incompetent in predicting clocks PW degradation or flops PW
requirement. The proposed method was used to control the clock PW
as well as to contain the flops PW demand.
VII. A SYMMETRIC AGING : C LOCK S TRATEGIES
The foregoing discussions clearly established the qualities of the
clock to ensure low or negligible asymmetric aging. Consequently,
the absolute lifetime for which a clock remains gated and the
nature of clock gating are the primary factors in aging-induced
skew, and careful consideration should be given while defining clock
architectures.
Similarly, insertion delay and tree depth are critical in determining
the PW degradation and, therefore, the exact placement of clock gates
needs careful handling. Circuitry to monitor the resultant clocks
duty cycle and other feedback or auto-corrective mechanisms coupled
with latency can be applied to maintain the quality of the clock.
Additionally, techniques like periodic data refresh in a memory bitcell can be applied analogously to the clocks during the gated period

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