SERVICE MANUAL

Model:

PDP4216M Monitor

Safety Precaution
Technical Specifications
Block Diagram
Circuit Diagram
Basic Operations & Circuit Description
Main IC Specifications
Trouble Shooting Manual of PDP Module
Spare Part list
Exploded View
If You Forget Your V-CHIP Password
Software Upgrade

This manual is the latest at the time of printing, and does not
include the modification which may be made after the printing,
by the constant improvement of product.

Safety Precaution

RISK OF ELECTRIC SHOCK

DO NOT OPEN

The lightning flash with arrowhead symbol,

within an equilateral triangle, is intended to
alert the user to the presence of uninsulated
dangerous voltage within the products enclo
sure that may be of sufficient magnitude to
constitute a risk of electric shock to persons.

CAUTION: TO REDUCE THE RISK OF

ELECTRIC SHOCK, DO NOT REMOVE COVER
(OR BACK). NO USER-SERVICEABLE PARTS
INSIDE. REFER SERVICING TO QUALIFIED
SERVICE PERSONNEL ONLY.

The exclamation point within an equilateral

triangle is intended to alert the user to the
presence of important operating and
maintenance (servicing) instructions in the
literature accompanying the appliance.

CAUTION

PRECAUTIONS DURING
SERVICING
1. In addition to safety, other parts and
assemblies are specified for conformance with
such regulations as those applying to spurious
radiation. These must also be replaced only
with specified replacements.
Examples: RF converters, tuner units, antenna
selection switches, RF cables, noise-blocking
capacitors, noise-blocking filters, etc.
2. Use specified internal Wiring. Note especially:
1) Wires covered with PVC tubing
2) Double insulated wires
3) High voltage leads
3. Use specified insulating materials for hazardous
live parts. Note especially:
1) Insulating Tape
2) PVC tubing
3) Spacers (insulating barriers)
4) Insulating sheets for transistors
5) Plastic screws for fixing micro switches
4. When replacing AC primary side components
(transformers, power cords, noise blocking
capacitors, etc.), wrap ends of wires securely
about the terminals before soldering.

MAKE YOUR CONTRIBUTION

TO PROTECT THE
ENVIRONMENT
Used batteries with the ISO symbol
for recycling as well as small accumulators
(rechargeable batteries), mini-batteries (cells) and
starter batteries should not be thrown into the
garbage can.
Please leave them at an appropriate depot.

WARNING:

Before servicing this TV receiver, read the

SAFETY INSTRUCTION and PRODUCT
SAFETY NOTICE.

SAFETY INSTRUCTION
The service should not be attempted by anyone
unfamiliar with the necessary instructions on this
apparatus. The following are the necessary
instructions to be observed before servicing.
1. An isolation transformer should be connected in
the power line between the receiver and the
AC line when a service is performed on the
primary of the converter transformer of the set.
2. Comply with all caution and safety related
provided on the back of the cabinet, inside the
cabinet, on the chassis or picture tube.

5. Make sure that wires do not contact heat

generating parts (heat sinks, oxide metal film
resistors, fusible resistors, etc.)
6. Check if replaced wires do not contact sharply
edged or pointed parts.
7. Make sure that foreign objects (screws, solder
droplets, etc.) do not remain inside the set.

3. To avoid a shock hazard, always discharge the

picture tube's anode to the chassis ground
before removing the anode cap.
4. Completely discharge the high potential voltage
of the picture tube before handling. The picture
tube is a vacuum and if broken, the glass will
explode.

5. When replacing a MAIN PCB in the cabinet,

always be certain that all protective are
installed properly such as control knobs,
adjustment covers or shields, barriers, isolation
resistor networks etc.
6. When servicing is required, observe the original
lead dressing. Extra precaution should be given
to assure correct lead dressing in the high
voltage area.

PRODUCT SAFETY NOTICE

Many electrical and mechanical parts in this
apparatus have special safety-related
characteristics.
These characteristics are offer passed
unnoticed by visual spection and the protection
afforded by them cannot necessarily be obtained
by using replacement components rates for a

7. Keep wires away from high voltage or high

tempera ture components.

higher voltage, wattage, etc.

The replacement parts which have these

8. Before returning the set to the customer,

always perform an AC leakage current check

special safety characteristics are identified by

marks on the schematic diagram and on the parts

on the exposed metallic parts of the cabinet,

such as antennas, terminals, screwheads,metal

list.

overlay, control shafts, etc., to be sure the set

is safe to operate without danger of electrical

read the parts list in this manual carefully. The

use of substitute replacement parts which do not

shock. Plug the AC line cord directly to the

AC outlet (do not use a line isolation

have the same safety characteristics as specified

in the parts list may create shock, fire, or other

transformer during this check). Use an AC

voltmeter having 5K ohms volt sensitivity or

hazards.
9. Must be sure that the ground wire of the AC

more in the following manner.

Connect a 1.5K ohm 10 watt resistor paralleled

inlet is connected with the ground of the

apparatus properly.

by a 0.15F AC type capacitor, between a

good earth ground (water pipe, conductor etc.,)
and the exposed metallic parts, one at a time.
Measure the AC voltage across the combination
of the 1.5K ohm resistor and 0.15 uF
capacitor. Reverse the AC plug at the AC
outlet and repeat the AC voltage measurements
for each exposed metallic part.
The measured voltage must not exceed 0.3V
RMS.
This corresponds to 0.5mA AC. Any value
exceeding this limit constitutes a potential
shock hazard and must be corrected
immediately.
The resistance measurement should be done
between accessible exposed metal parts and
power cord plug prongs with the power switch
"ON". The resistance should be more than
6M ohms.
AC VOLTMETER

Good earth ground

such as the water
pipe, conductor,
etc.

Place this probe

on each exposed
metallic part

AC Leakage Current Check

Before replacing any of these components,

Technical

Specifications

DATE FIRST ISSUED

ISSUE

MODEL :

PDP4216M Monitor
42 Plasma Display

RAISED BY

CHECKED BY

NUMBER OF PAGE

10

RAISED BY :

DATE

R & D DEPARTMENT

......................................................................................
......

...........................
...

......................................................................................
......

...........................
...

Q/A DEPARTMENT

......................................................................................
.......

...........................
...

CUSTOMER

......................................................................................
.......

...........................
...

......................................................................................
.......

...........................
...

COMMERCIAL DEPARTMENT

PRODUCTION DEPARTMENT

SIGNATURE :

NOTE :

DATE :

Only documents stamped Controlled Document to be used for manufacture of production parts.

Technical
1.

CONTINUATION PAGE

Specifications

PDP4216M

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PAGES

Standard Test Conditions

All tests shall be performed under the following conditions, unless otherwise specified.
1.1

Ambient light

150ux (When measuring IB, the ambient luminance

0.1Cd/m2)

1.2

Viewing distance

50cm in front of PDP

1.3

Warm up time

30 minutes

1.4

PDP Panel facing

no restricted

1.5

Measuring Equipment :

PC, Chroma 2225 signal generator (with Chroma digital

additional card) or equivalent, Minolta CA100 photometer

1.6

Magnetic field

no restricted

1.7

Control settings

Brightness, Contrast, Tint, Color set at Center(50)

1.8

Power input

100~120Vac

1.9

Ambient temperature :

1.10 Display mode

1.11 Other conditions

60Hz

20C 5C (68F 9F)

Resolution 1024 x 768

1.11.1

With image sticking protection of PDP module, the luminance will descend
by time on a same still screen and rapidly go down in 5 minutes. When
measuring the color tracking and luminance of a same still screen, be sure t
o accomplish the measurement in one minute to ensure its accuracy.

1.11.2

Due to the structure of PDP, the extra-high-bright same screen should not
hold over 5 minutes for fear of branding on the panel.

Technical

CONTINUATION PAGE

Specifications

PDP4216M

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PAGES

ELECTRICAL CHARACTERISTICS
2.

3.

Power Input
Voltage

100 ~120VAC

2.2

Input Current

5.0 /2.5A

2.3

Maximum Inrush Current

Test condition

:
:

<30 A (FOR AC110V ONLY)

Measured when switched off for at least 20 mins

2.4

Frequency

50Hz to 60Hz(3Hz)

2.5

Power Consumption
Test condition

:
:

330W Typical
full white display with maximum brightness and
contrast

2.6

Power Factor

Meets IEC1000-3-2

2.7

Withstanding voltage

1.5kVac or 2.2kVdc for 1 sec

:
:
:
:
:
:
:

42 Plasma display
16:9
1024x768
1000 cd/m (Typical, Panel only)
5000:1 (Ratio, Typical, in a dark room, Panel only)
Over 160
English,Spanish,French

Display
3.1
3.2
3.3
3.4
3.5
3.6
3.7

4.

60Hz

2.1

Screen Size
Aspect Ratio
Pixel Resolution
Peak Brightness
Contrast Ratio (Dark room)
Viewing Angle
OSD language

Signal
4.1

AV & Graphic input

4.1.1 Composite signal
4.1.2 Y,C Signal
4.1.3 Component signal
4.1.4 Graphic I/P

:
:
:
:

4.1.5EDID compatibility
4.1.6 I/P frequency

:
:

CVBS
S-Video
YPbPr x 2, HDMI,VGA compatible
Analog: D-sub 15pin detachable cable
Digital:HDMI
DDC 1.3
fH: 31.5kHz to 60kHz/fV: 56.25Hz to 75Hz(1024x768
recommended)

Technical

4.2 Audio input

4.3 Audio output

5.

PDP4216M

VGA(D-Sub 15 Pin Type)1

D-Sub 9 Pin (RS-232 Input) 1
HDMI (Ver. 1.1) connector 1
S-Video (Mini Din 4 Pin) 1
C V B I n p u t (RCA Type) 1
YPbPr 2
Stereo/Audio 6
Audio&Video Output (RCA Type) 1

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PAGES

SPDIF (Optical) 1

PIP/POP/PBP, Picture size, Picture Still, Sound mode,Last

memory, Timer, MTS

Environment
5.1 Operating environment

5.2

6.

CONTINUATION PAGE

Specifications

5.1.1 Temperature
:
5.1.2 Relative humidity:

5 to 33C
20% to 85%(non-condensing)

Storage and Transport

5.2.1 Temperature
:
5.2.2 Relative humidity:

-20C to 60C(-4 to 140F)

5% to 95%

Panel Characteristics
6.1
6.2

Type
Size

:
:

6.3
6.4
6.5
6.6
6.7
6.8

Aspect ratio
:
Viewing angle :
Resolution
:
Weight
:
Color
:
Contrast
:

6.9

Peak brightness :

LGX2A
42,1106.5mm(W)X622.1mm(H)
(W/Ostand)
16:9
Over 160
1024X768
22.0kg 0.5 kg (Net)
16.7 millions of colors (R/G/B each 256 scales)
Average 60:1 (In a bright room with 150Lux at center)
Typical 5000:1 (In a dark room 1/100 White Window
pattern at center).
Typical 1000cd/ (1/25 White Window)

6.10 Color Coordinate Uniformity :

Test Pattern

Contrast; Brightness and Color control at normal

setting
Full white pattern
Average of point A,B,C,D and E +/- 0.01

Technical

CONTINUATION PAGE

Specifications

6.11 Color temperature

PDP4216M

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Contrast at center (50); Brightness center (50);

Color temperature set at Natural
x=0.2850.02
y=0.2900.02

6.12 Cell Defect Specifications

Subject to Panel supplier specification as appends.
7.

Front Panel Control Button

7.1

SEL. Up / Down Button

VOL. Left/Right Button

MENU Button

Source Select Button

Push the key to select Item up or down.

When selecting the item on OSD menu.
Push the key to increase the volume left or right.
When selecting the adjusting item on OSD menu
increase or decrease the data-bar.
Display or Exit the OSD menu.
Press this button and use up/down button to sellect
the signal sources. AV, S-Video, YPbPr1,YPbPr2
VGA or HDMI.

7.2

STANDBY Button

Switch on main power, or switch off to enter power

Saving modes.

7.3

Main Power Switch

Turn on or off the unit.

8.

OSD Function

8.1 Picture : Brightness; Contrast; Saturation; Phase; Frequency;

Picture Mode (Normal, Bright, Cinema, User);
Color Temp (Warm, Normal, Cool); etc.
8.2 Window : Image Size (Fill All, Force 4:3, Letter Box, Wide, Anamorphic, etc);
H Position; V Position; Freeze Window (Off, On)
8.3 Audio : Balance; Audio Mode (SRS TSXT, Cinema, Music, News, User)
Speaker (Internal, External); AVC (Off, On)
Equalizer (120Hz, 200Hz, 500Hz, 1.2kHz, 3kHz, 7.5kHz, 12kHz)
8.4 Options : Osd Timeout (5 Sec, 15 Sec, 60 Sec); Menu Background (Opaque,
Translucent); Language (English, French, Spanish); Default Setting;
Close Caption Mode (CC1, CC2, T1, T2, Xds); Close Caption (Off, On,
On Mute); Content Blocking; Timer
8.5 Layout : Full Screen; PIP; Split Screen

Technical
9.

Specifications

CONTINUATION PAGE

PDP4216M

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Agency Approvals
Safety

UL/FCC/cUL

Emissions

FCC class B

10. Reliability
11.1 MTBF
11. Accessories

20,000 hours(Use moving picture signal at 25C ambient)

User manual x1, Remote control x1,

Stand x 1, Battery x 2, AC Cable x 1

PAGES

Technical

CONTINUATION PAGE

Specifications

PDP4216M

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12. Support the Signal Mode

A. HDMI Mode / D-Sub Mode (VGA or DVI) / HDTV Mode (YpbPr1 or YpbPr2)
No

Mode

Resolution

Horizontal
Frequency
(KHz)

Vertical
Frequency
(KHz)

Dot Clock
Frequency
(MHz)

640x400

31.47

70.08

25.17

640x480

31.50

60.00

25.18

640x480

35.00

67.00

30.24

640x480

37.50

75.00

31.50

640x480

37.86

72.81

31.50

720x400

31.47

70.08

28.32

800x600

31.56

56.25

36.00

800x600

37.90

60.32

40.00

800x600

46.90

75.00

49.50

800x600

48.08

72.19

50.00

832x624

49.00

74.00

57.27

1024x768

48.84

60.00

65.00

1024x768

56.50

70.00

75.00

1024x768

60.00

75.00

78.75

1152x864

54.53

61.13

80.37

16

1152x864

63.86

70.02

94.51

17

1152x864

67.52

75.02

108.03

18

1280x960

60.02

60.02

108.04

19

1280x1024

64.00

60.01

108.00

20

1080i (1920x1080)

33.75

60.00

74.25

21

1080i (1920x1080)

28.125

50.00

74.25

720P (1280x720)

45.00

60.00

74.25

720P (1280x720)

37.50

50.00

74.25

576p (720x576)

31.25

50.00

27.00

480p (720x480)

31.468

59.94

27.00

26

576i

15.625

50.00

13.50

27

480i

15.734

59.94

13.50

D-Sub
Mode
(VGA or
DVI)

8
9
10
11
12
13
14
15

22
23
24
25

HDMI
Mode

HDTV
Mode
(YpbPr1/
YpbPr2)

PAGES

Technical

Specifications

4.4 Remote Control

1 POWER( ): Press this button to turn off to
standby and turn on from standby.
2 MUTE( ): Press this button to quiet the sound
system. Press again to reactivate the
sound system.
3 P.STILL: Press this button to hold on the
screen. Press again to normal.
4 P.SIZE: When the input source is YPbPr 1,
YPbPr 2, VGA or HDMI, press this button,
the picture will change according to Fill All,
Force 4:3, Letter Box, Wide or Anamorphic.
When the input source is AV or S-Video, press
this button, the picture will change according to
Fill All, 4:3, Letter Box, Wide or Anamorphic.
5 S.SELE: Press this button to select the sound
output from Main Window or Sub Window.
6 P.MODE : Press the button to select different
picture effect.
7 TIME: Press this button to pop up the Clock
Set menu.
8 SLEEP: Press this button to select the sleep
time.
9 INFO: Press the button to display the
source information.
10 AUTO: The Display automatically adjusts the
phase, vertical / horizontal position when
pressing this button in VGA mode.
11 LAYOUT: Press this button to pop up Layout
menu.
12 C/C: Press this button to enter the Closed
Caption Function. (Only for AV or S-Video)
13 V-CHIP: Press this button to enter the V-Chip
Function. (Only for AV or S-Video)
14 Number buttons: Use these buttons to enter
the password.
(Continued on next page)

CONTINUATION PAGE

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PAGES

Technical

Specifications

15 SWAP: Press this button to switch the Main

window or Sub window pictures in PIP and
Split Screen.
16 F.WHITE: Press this button to show a full
white picture.
17 PIP POS. : Press the button to select different
Image Position in PIP Mode.
18 PIP SIZE : Press the button to select different
Image Size in PIP Mode.
19 SPEAKER: Press this button to pop up the
Speaker menu, use the / button to select
Internal or External.
20 SOUND: Press the button to select different
sound effect.
21 W.SELE: Press this button to select the Main
Window or Sub Window.
22 SOURCE: Press this button and use /
button to select the signal sources. AV, S-Video,
YPbPr 1, YPbPr 2, VGA or HDMI.
23 PIP: Press this button to change different
Picture Mode.
24 MENU: Press this button to pop up the OSD
Menu and press it again to exit the OSD Menu.
25 OK : Press to enter or conrm.
26 / : They are used as / buttons in the
OSD Menu screen and they can be used for
the adjustment of volume when the OSD Menu
is not shown on the screen.
/ : They are used as / buttons in the
OSD Menu screen.
They also can be used for the selection of the
program when the OSD Menu is not shown on
the screen, but only for the Model with Tuner.

CONTINUATION PAGE

PDP4216M

NUMBER

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PAGES

Technical

CONTINUATION PAGE

Specifications

PDP4216M

NUMBER

10

OF

10

PAGES

PHYSICAL CHARACTERISTICS
14. Power Cord
Length

1.8m nominal

Type

optional

15. Cabinet
15.1 Color

black colour as defined by colour plaque reference number

15.2 Weight(W/Ostand)
Net weight
Gross weight

:
:

(W/O stand&speak)

15.3 Dimensions
Width
Height
Depth

34kg

:
:
:

1024mm
692mm
286mm

Block Diagram

Product Specification of PDP Module

LVDS Input

Control Signal
(Serial Interface)

Input
Interface
Controller

Vs(180V~190V)

Memory
Controller

Va(55V~65V)
Vcc(+5V)

Driver
Timing
Controller

APL Data

Color Plasma Display Panel

1366 X 768 pixels

Common sustain driver

Scan Driver

Display data, Driver timing

Address Driver

Applied Voltage level is specified at the time when Full-White pattern is displayed on the panel.

Block Diagram

MAIN / AUDIO BOARD

HDMI Input

Stereo
Audio
Input

MSP44XXG
Audio
decoder

HD1 Input
HD2 Input

Speaker

Video
Input

AD9880
ADC & HDMI
Receive

D-Sub15

TDA 2616
Audio Amp

Max232
RS232C

PI5V330
Switch

D-SUB9

1R
VPC3230D
Video decoder

S-Video
Input

PW1231
De-Interlace

PW181
Image
Processor

VPC3230D
Video decoder

286229
V-Chip /
CCD

SAA5316
TV TEXTPRO

LP262S20480T
SRAM

THc63LVD
M83
LVDS
Transmitter

AT24C32
EEPROM

HT48R06A
mcu

Keypad

LVDS
Header

Circuit Diagram
- Power supply board of Audio Amplifier, MPT012A
- Main (Video) board
- Audio/Tuner board
- Keypad board
- Remote control receiver board
- Remote control board

5
JP902

U902
5V

OVDD3.3V#
GND

INPUT OUTPUT

C910

TAB

PLL1.8V

L900

C916

4
C901

C917

OVDD3.3V#

TVDD3.3V

C918

5V
L914

AVDD3.3V

C924 C925 C956

L915
C954

C949 C950 C951 C952

C907

C904

C911

AVDD3.3V#

L903

1
5V

TAB

CVDD1.8V

L901

L904

OVDD3.3V

C913

C920

C921

C926 C927 C928

DDC5V

82
83

DDC5V

R903

R906

DDC5V

46
R947

R908
HD1_R/Pr

62
VCC
NC1
NC2
NC3

HD1_G/Y

JP901

GYCbCr_Y

C943
C944

HDMI_D0+
HDMI_D0-

GYCbCr_Cb

GYCbCr_Cb

C946

R909

HDMI_CK+
HDMI_CK-

56
59

67
72
76
80

30

32
48

54

AVDD1
AVDD2
AVDD3
AVDD4
B7
B6
B5
B4
B3
B2
B1
B0

U901

RAIN1
GAIN1
SOG1
BAIN1
VS1
HS1

DE
HSOUT
SOGOUT
VSOUT/A0
FIELD
DCLK

R910

GYCbCr_Cr

R945

GYCbCr_Y

R946

GYCbCr_Cb

RP909

DDC_SCL3
DDC_SDA3
HDCP_SCL
HDCP_SDA

HDMI_D0-

D905

HDMI_D1+

D906

HDMI_D1-

D907

HDMI_D2+

D908

HDMI_D2-

D909

HDMI_CK+

D910

HDMI_CK-

SDA#SO
SCL#SO

R912

TVDD3.3V

Vd

270mA 891mW

DDC_SDA3

92
93
94
95
96
97
98
99

ADCR7
ADCR6
ADCR5
ADCR4
ADCR3
ADCR2
ADCR1
ADCR0

RP905

2
3
4
5
6
7
8
9

ADCG7
ADCG6
ADCG5
ADCG4
ADCG3
ADCG2
ADCG1
ADCG0

RP903

12
13
14
15
16
17
18
19

ADCB7
ADCB6
ADCB5
ADCB4
ADCB3
ADCB2
ADCB1
ADCB0

RP901

88
87
86
85
84
89

ADC_DE
ADC_HS
ADC_SOG
ADC_VS
ADC_FIELD
ADC_DCLK

28

S/PDIF

GRE[7..0]

GRE7
GRE6
GRE5
GRE4
GRE3
GRE2
GRE1
GRE0

RP906

C
GGE[7..0]

GGE7
GGE6
GGE5
GGE4
GGE3
GGE2
GGE1
GGE0

RP904

GBE[7..0]

GBE7
GBE6
GBE5
GBE4
GBE3
GBE2
GBE1
GBE0

RP902

RP907
GPEN
GFBK
GHS
GVS
FIELD
GCLK
GSOG

R918
R917
R916

GPEN
GFBK
GHS
GVS
FIELD
GCLK
GSOG

JP903

MCLKIN
MCLKOUT
SCLK
LRCLK
I2S0
I2S1
I2S2
I2S3

DDC_SCL
DDC_SDA
MCL
MDA

PWRDN

20
21
22
23
27
26
25
24

DDC_SCL5
DDC_SDA5

RP908
I2S_SCLK
I2S_LRCLK
I2S_DATA

R928
R927
R926

C2
V2
Y2

OVDD3.3V
C955
AVDD3.3V

81

R930

R933
1

R914

2
U907A

R931

3
R932

4
U907B

SPDIFOUT
R934

R913

C953

7
6
5
4

VCLK
SCL
SDA
GND

VCC
NC1
NC2
NC3

8
1
2
3

A
Title

C934

U906

SGND

Size

9-HDMI-R
Number

Revision

B
Date:
File:
1

3
2
1

D904

49
50
51
52

20mA 36mW

55
58
65
69
75
78

D903

HDMI_D0+

SGND
HPD_DET

S/PDIF

53

HPD_DET

60mA 108mW

PVd

R929
RX0RX0+
RX1RX1+
RX2RX2+
RXC+
RXC-

PGND1
PGND2
AGND1
AGND2
AGND3
AGND4

R915

HD1_B/Pb

R944

34
35
37
38
40
41
43
44

ALGND

R943
3

HDMI_D0HDMI_D0+
HDMI_D1HDMI_D1+
HDMI_D2HDMI_D2+
HDMI_CK+
HDMI_CK-

TGND1
TGND2
TGND3

HD1_G/Y

36
39
42

HD1_R/Pr

R942

CGND1
CGND2

HDMI_5V

R941

DGND1

DDC5V
2
D911

31
47

5V
DDC_SCL5
DDC_SDA5

29

20
21
22
23

77
71
70
66
60
63

HD2_Cb

C930

HD2_Cr
HD2_Y

C945

RAIN0
GAIN0
SOG0
BAIN0
VS0
HS0

OGND1
OGND2
OGND3

T1
T2
T3
T4

GYCbCr_Y

HDMI_D1+
HDMI_D1-

79
74
73
68
61
64

HD1_B/Pb C942

VGA_VS
VGA_HS
GYCbCr_Cr
GYCbCr_Cr

HDMI_D2+
HDMI_D2-

L913

COAST/EXTCK

C941

C929
HD1_B/Pb

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

HD1_G/Y C940

1
11
91

C948

VCLK
SCL
SDA
GND

8
1
2
3

G7
G6
G5
G4
G3
G2
G1
G0

HD1_R/Pr C939

U905
7
DDC_SCL5 6
DDC_SDA5 5
4
C947

RTERM

R907

GCOAST
D902

SCL
SDA

C937

C938

DVdd

R922

Using analog interface:

R924

R7
R6
R5
R4
R3
R2
R1
R0

R905
SCL_H5V
SDA_H5V

FILT

PVDD1
PVDD2

57

ALVDD

C936

C906

DVDD

R904

TVDD3.3V

10-120mA, 30mA typical

14

C915

C923

CVDD1
CVDD2

C922

4
C903

DDC5V

Vdd (3.3V) (Ovdd)

99mW

R921

R925

DDC_SDA5
C935

TVDD1
TVDD2

DVDD1.8V

L902

OVDD1
OVDD2
OVDD3

GND

TAB

DDC_SCL3

Q902
33
45

10
90
100

PLL1.8V
HDMI-1.8V

INPUT OUTPUT

DATA2+
DATA2S
DATA2DATA1+
DATA1S
DATA1DATA0+
DATA0S
DATA0CLK+
CLKS
CLKCEC
NC
SCL
SDA
CEC/GND
+5V
HPDET

Q901

C908

C905

U904

D901

R919

R920

D3V3B

CVDD1.8V DVDD1.8V PLL1.8V

C919

4
C902

C914

GND

INPUT OUTPUT

Vd (3.3V) (Avdd+TVdd) 80mA 264mW

D

DDC_SCL5
AVDD3.3V#

DVdd (1.8V) (DVdd+CVdd) 130mA 234mW

GND

PVd (1.8V) (PVd+ALVdd) 30mA 54mW

SGND

U903

C912

Using digital interface:

VCC

R923

D
3

VIN

C909

SPDIFOUT

14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
6

D3V3D
D

D0_SRAM

D1_SRAM

D2_SRAM

D3_SRAM

D4_SRAM

D5_SRAM

D6_SRAM

D7_SRAM

D5_SRAM
D4_SRAM
SDA_S3V

R1515

D3_SRAM
D2_SRAM

SCL_S3V

SCL_S3V

D1_SRAM

C1513

R1506

/WR_SRAM

5
30

R1513
3450_rest

81
80
79
78
77
76

83
82

D3V3D

SDA_S3V

D0_SRAM

C1512

SC2_SW1

SC1_SW0
SC1_SW1
SC2_SW0

RP1502

100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84

R1527

RP1501

D6_SRAM

R1514

D3V3D
6

A15_SRAM
A14_SRAM
/RD_SRAM
/WR_SRAM

A7_SRAM
SCL_NVRAM
SDA_NVRAM

A6_SRAM

C1511

U1501

/CE1
CE2
/OE

R1505
X1501

9
10
7
11
4
12
1
31
2
3
13
14
15
16
17
18
19
20

A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

A17_SRAM
A16_SRAM

RP1503

A15_SRAM
A14_SRAM
A13_SRAM
A12_SRAM

RP1504

A11_SRAM
A10_SRAM
A9_SRAM
A8_SRAM

RP1505

A7_SRAM
A6_SRAM
A5_SRAM
A4_SRAM

RP1506

A3_SRAM
A2_SRAM

R1508
R1509

A1_SRAM
A0_SRAM

C
XTALOUT

C1504

XTALIN

C1505

A8_SRAM
A9_SRAM
A10_SRAM
A11_SRAM

D3V3D

U1503
SDA_NVRAM

SCL_NVRAM

TT_VVVS

7
D3V3D

TT_VVHS
TT_FSO

SDA

GND

SCL

NC2

WP

NC1

VCC

NC0

D3V3D

R1516

SC1_SW1
3
2

D1501

R1517

A16_SRAM

A17_SRAM

A0_SRAM

R_OUT

G_OUT

B_OUT

A1_SRAM

A2_SRAM

A3_SRAM

R1501

A12_SRAM

C1501

A13_SRAM

CVBS1

CVBS0

A4_SRAM

A5_SRAM

SC1_SW

D3V3D

R1522

SC2_SW1

R1525

SC2_SW0

Q1503

D3V3D

Q1504
D1503

R1523

R1526

D1504

TT_R

R1511

TT_G

R1512

TT_B

SGND

R1504

C1518

C1517

R1503

R1502

R1521

C1515

C1514

C1516

C1502

TV_CVBS_S#

D1502

SGND

R1510
C1503

TV_CVBS_M#

R1520
SC2_SW

R1529

C1519

D3V3_TT_A

SGND

D3V3D

Q1502

C1510
SGND

R1519

SC1_SW0

Q1501

R1528

B
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

32

/WE

GND

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

VDDP
NC
RESET
/RESET
XTALOUT
XTALIN
OSCGND
NC
A8
A9
A10
A11
VDDC
VSSC
NC
VSSP
P3.6
NC
NC
NC
VSYNC
P3.5
HSYNC
VDS
RAMBANK0

R1507

I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1

24

P1.4
SDA

/RD_SRAM

SCL
P1.3
P1.2
P1.1
A16_LN
P1.0

P2.7
P3.0
A17_LN
P3.1
P3.2
P3.3
A15_LN
A14
/RD
/WR
VSSC
VSSP
P0.5
NC
A7
SCL_NVRAM
SDA_NVRAM
P0.2
NC
NC
VPE
P0.3
A6
P0.4
P3.7

A5
A4
P0.6
P0.7
VSSA
CVBS0
CVBS1
A15_BK
SYNC_FILTER
IREF
A13
A12
A3
A2
A1
FRAME
VPE
/COR
P3.4
VDDA
B
G
R
A0
RAMBK1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

P2.0
VSSC
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
P1.5

D3V3D

VCC

29
28
27
26
25
23
22
21

D7_SRAM

GPIO_P33
GPIO_P32
GPIO_P31
GPIO_P30
TT_SEL

U1502

D3V3D

SGND
Title

C1506 C1507 C1508

Size

15_TELETEXT_DECODER
Number

Revision

B
Date:
File:
1

14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
6

5
A5V

U1101
5V

L1112

VV33
4

R1121
C1114

C1113

C1109

C1112

TV_CVBS_M#

C1105

C1108

C1111

TAB

R1112

C1110

INPUT OUTPUT
GND

R1114

CVBS_O

D
C1164
Q1101
R1113

C1171

R1103

R1104

3230_VO

R1106

C1163

5VVV

MREST

3230_VO

SGND
RP1105

R1101
C1141

C1124

SDA_S3V
SCL_S3V

C1142 C1143

C1146

C1145

R1102
SGND

5VVV

SGND

RP1106

C1148

74

V_TVCVBS

C1117

73

C1150

R1116

C1151

C1115

75

C1118

71

C1119

72

C1120

C1121

SGND
L1102

C1128

R1117

V_SVideo_C
C1149

VIN3

VIN4
CIN

U1102

Y2/G2
U2/B2

SGND

C1156

R1118
V_TT_B

SGND

V_TT_R
V_TT_FSO

C1167
C1168

62
63

XTALI
XTALO

R1127

R1119

RP1101
RP1102
RP1103
RP1104

LLC2
LLC
HS
INTLC
AVO
HCLP
VS
VREF
VRT

SGND
31
32
33
34
37
38
39
40

RP1107

41
42
43
44
47
48
49
50

VUV7
VUV6
VUV5
VUV4
VUV3
VUV2
VUV1
VUV0
C1139

27
28
56
53
54 #VPEN
R1107
55
R1105
57
R1108

RP1108
VB3
VB2
VB1
VB0

VUV3
VUV2
VUV1
VUV0

VY[7..0]

VB[7..0]
RP1109
#VPEN
VVVS
VVHS
VVCLK

VPEN
VVS
VHS
VCLK

VUV[7..0]

R1109
VVCLK
VVHS
R1123

R1110

VVCLK
VVHS

Install RP1105~RP1109 if cancel deinterlace IC

X1101
L1105

VVVS

78 REF_V
66

A5V
C1137 C1135

5V

C1138 C1136

C1103

C1123

L1103
5VVV
L1101

SGND

C1106

C1104
C1107

SGND

C1140

VYCbCr_Cb

C1134
C1130

C1131

SGND
SGND
A

L1106
VYCbCr_Cr

Title

SGND

Size

Number

Revision

B
Date:
File:

SGND
2

11-DECODERV

R1125 R1126

C1127

C1126

C1125

C1174

C1173

R1124
C1172

TT_VVHS
VVVS
TT_VVVS

C1133

VYCbCr_Y

C1132

L1104

VG[7..0]
VB7
VB6
VB5
VB4

VUV7
VUV6
VUV5
VUV4

VY7
VY6
VY5
VY4
VY3
VY2
VY1
VY0

GND
ASGND
ASGND
PLGND
YGND
CGND
SPGND
AFGND
ISGND
ISGND
ISGND
I2CSEL
VGAV
TEST
OE#

C1154

Y1/G1
U1/B1
V1/R1
FBIN1

UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0

11
7
64
30
35
46
51
65
68
77
80
67
17
16
18

2
1
3
79

APGND
CLK5
FPDAT
CLK20
APVDD

C1166

25
60
58
24
26

V_TT_G

V_SVideo_Y

ADR:0x88

V2/R2

GNDCAP

12

C1122
L1111

VDDCAP

Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0

VIN2

VIN1

C1147

10
29
36
45
52
19
20
21
22
23
69
76
59
VDD
PLVDD
YVDD
CVDD
SPVDD
FFIE
FFWE
FFRST
FFRE
FFOE
AFVDD
ISVDD
VSTBY

C1116
SGND
L1108

70

R1115

C1159

VOUT

C1160

SCL
SDA
RST#

13
14
15

VV33

VG3
VG2
VG1
VG0

VY3
VY2
VY1
VY0

L1107
V_AVCVBS

VG7
VG6
VG5
VG4

VY7
VY6
VY5
VY4

C1144

14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
6

U1401

A5V

5V

GV33
4

C1409

C1414

R1412
C1405

C1413

TAB

L1412
C1412

C1411

GND

INPUT OUTPUT

C1410

R1414

CVBS_S_O

C1463
C1464
5VVG

Q1401
SGND

C1441

R1403

C1442 C1443

C1446

C1445

C1444

C1471

R1413

R1404

R1421
TV_CVBS_S#

MREST
C1424
SGND
G_AVCVBS

L1407

G_AVCVBS

5VVG

SGND

R1406
TV_CVBS_S

R1401
SDA_S3V

C1448

GV33
R1402

SGND

10
29
36
45
52
19
20
21
22
23
69
76
59

R1415

C1459

70

C1460

13
14
15

SCL_S3V

SGND

VDD
PLVDD
YVDD
CVDD
SPVDD
FFIE
FFWE
FFRST
FFRE
FFOE
AFVDD
ISVDD
VSTBY

L1408

VIN3

VOUT

74

SCL
SDA
RST#

C1416

G_TVCVBS
C1450

C1451

L1402

C1417

73

C1415

75

C1418

71

C1419

72

C1420

C1421

C1422

C1466
C1467

2
1
3
79

C1468

62
63

Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0

VIN2

R1416

SGND

G_SVideo_C

VIN4

C1449

SGND

U1402

VIN1

SGND
31
32
33
34
37
38
39
40
41
42
43
44
47
48
49
50

UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0

CIN

R1417
C1428

Y2/G2

RP1401

RP1402

RP1403

GBE7
GBE6
GBE5
GBE4
GBE3
GBE2
GBE1
GBE0

RP1404

L1405

GYCbCr_Cb

G_TT_R
G_TT_FSO

R1427

R1425 R1426

C1432

R1419

C1427

C1426

C1425

C1474

C1473

R1424

X1401

11
7
64
30
35
46
51
65
68
77
80
67
17
16
18

25
60
58
24
26

R1409
R1410
R1408
R1407
R1422
R1405
GHS R1423

78
66

VREF
VRT

L1406

GYCbCr_Cr

C1472

XTALI
XTALO

GYCbCr_Cr

GBE[7..0]

GCLK
GHS
FIELD
GPEN
TT-GHS
GVS

GHS
TT-GHS

REF_G

C1437 C1435

C1438 C1436

C1433

5V

C1423
C1440

GND
ASGND
ASGND
PLGND
YGND
CGND
SPGND
AFGND
ISGND
ISGND
ISGND
I2CSEL
VGAV
TEST
OE#

G_TT_B

12

GYCbCr_Cb

L1404

Y1/G1
U1/B1
V1/R1
FBIN1
APGND
CLK5
FPDAT
CLK20
APVDD

G_TT_G

27
28
56
53
54
55
57

LLC2
LLC
HS
INTLC
AVO
HCLP
VS

ADR:0x8E

V2/R2

GNDCAP

R1418

U2/B2

VDDCAP

C1456

SGND
GYCbCr_Y

GGE[7..0]

C1439

GYCbCr_Y

GGE7
GGE6
GGE5
GGE4
GGE3
GGE2
GGE1
GGE0

L1411
G_SVideo_Y
C1454

TV_CVBS_S

C1447

R1420

SGND

5VVG

SGND

5VVG
L1401

SGND
C1403

C1406

C1404
C1407

C1434
SGND

SGND

C1430

C1431
SGND

A
Title
Size

14-DECODER_G
Number

Revision

B
Date:
File:
1

14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
6

C860

C861
U803

6
SGND 5

TT_VVHS
3230_VO

C855

R857

7
8
9

SCK

SEN

I2C/SEL

SMS

SDO

HIN

BOX

VIDEO

VDD

CSYNC
LPF

V_TT_R

R861

V_TT_G

R862

V_TT_B

V_TT_R
D

V_TT_G
V_TT_B

1
16 SGND
17

R815

R863

12

V_TT_FSO

V_TT_FSO

5V_V_CCD
SCL_S5V

SCL_S5V

10

RREF

11

VSS(A)

R854

Q801

SCL_S3V
V33SW

5V

5V_V_CCD 4

R860

C865

15

SDA

18

C864

R856

R867

SCL_S5V

Vin/INTRO

C863

14

R866

R855

C862

SDA_S5V

R865

TT_VVVS

R864

13

R852

SGND

A5V

R853

L801
C

C856

C857

C858

C859

R858
Q802
C

R859
C804

C806

C803

C807

SDA_S5V

SDA_S5V

SDA_S3V

R814
SGND
C814

SGND

C815
U802

4
6

SGND 5

TT-GHS
TV_CVBS_S

C809

R803

7
8
9

SEN

I2C/SEL

SMS

SDO

HIN

BOX

VIDEO

VDD

CSYNC
LPF

G_TT_R

R807

G_TT_G

R808

G_TT_B

G_TT_R
G_TT_G
G_TT_B

1
16

B
R809

17

G_TT_FSO

G_TT_FSO

12
10

RREF

11

VSS(A)

C820

5V_G_CCD

SCK

R806

C819

15

18

R813

R802

C818

SCL_S5V

SDA

R812

14

R811

R801

C817

SDA_S5V

Vin/INTRO

R810

13

GVS

R804
SGND

A5V

5V_G_CCD
C810

C811

C812

C813

L802

R805
C802
C808

SGND

C805

C801

SGND

Title
Size

8-CCD_DECODER

Number

Revision

A4
Date:
File:
1

14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
4

4
D3V3B

5
D3V3B

R1305

U1301D

R1322

R1308

GRO[7..0]

GGO[7..0]

GBO[7..0]

GGE0
GGE1
GGE2
GGE3
GGE4
GGE5
GGE6
GGE7

C11
B12
B11
A8
B8
C8
A7
B7

GBE0
GBE1
GBE2
GBE3
GBE4
GBE5
GBE6
GBE7

B18
A20
B17
A19
B16
A17
A16
A15

GRO0
GRO1
GRO2
GRO3
GRO4
GRO5
GRO6
GRO7

A6
C7
B6
A5
D7
B5
C6
A4

GGO0
GGO1
GGO2
GGO3
GGO4
GGO5
GGO6
GGO7

C13
B15
A14
B14
A13
C12
B13
A12

GBO0
GBO1
GBO2
GBO3
GBO4
GBO5
GBO6
GBO7

C18
E17
C17
B19
E16
C16
C15
D14

GRE0
GRE1
GRE2
GRE3
GRE4
GRE5
GRE6
GRE7

X1301

R1303

U1301B
E1
E3
F3
D1
N2

VCLK
VVS
VHS
FIELD
VPEN
VR[7..0]

VG[7..0]

PW181 Graphics Port

VB[7..0]

GGO0
GGO1
GGO2
GGO3
GGO4
GGO5
GGO6
GGO7

V11
W11

IR_181
NMI

C1302

GBE0
GBE1
GBE2
GBE3
GBE4
GBE5
GBE6
GBE7

Y12
V12

RXD
TXD
C1301

GGE0
GGE1
GGE2
GGE3
GGE4
GGE5
GGE6
GGE7

GRO0
GRO1
GRO2
GRO3
GRO4
GRO5
GRO6
GRO7

R1301

VR0
VR1
VR2
VR3
VR4
VR5
VR6
VR7

E2
F1
F2
G3
G2
H3
H2
G1

VG0
VG1
VG2
VG3
VG4
VG5
VG6
VG7

J4
H1
J3
J2
J1
K3
K2
K1

VB0
VB1
VB2
VB3
VB4
VB5
VB6
VB7

L2
L1
L3
L4
M3
M1
N1
M2

VCLK
VVS
VHS
FIELD
VPEN

SDA_H3V
SCL_H3V

SDA_H3V
SCL_H3V
SDA_S3V
SCL_S3V

R1304

GAFEOE
MUTE
SEL1
SEL0

REMARK:
HARDWARE I2C: SDA1 SCL1
SOFTWARE I2C: VSDA VSCL

VR0
VR1
VR2
VR3
VR4
VR5
VR6
VR7

D3V3B

R1309

D1302

R17
W18
V18
Y18
U18
Y19
W19
T18

D3V3B

Q1303

T17
V16
W16
Y16
V17
U17
W17
Y17

R1310

3450_rest

P1
Y2
M4
N3

R1332
R1331

VB0
VB1
VB2
VB3
VB4
VB5
VB6
VB7

D3V3B

D3V3B

R1326

SCL_H5V

SCL_H5V

U16
N4
T5
P2

R1313

U15

R1315

PORTC0
PORTC1
PORTC2
PORTC3
PORTC4
PORTC5
PORTC6
PORTC7
CPUTMS
CPUTCK
CPUDI
CPUDO
MODE0
MODE1
MODE2
MODE3
ADR24B

INPUT OUTPUT

C1303

TAB

C1324
S

RD
WR
BHEN
ROMOE
ROMWE
RAMOE
RAMWE
CS1
CS0
EXTINT
NMI
DNC1
DNC2
DNC3

V10
Y10
Y9
W9
V9
Y8
W8
V8
W7
U8
V7
W6
Y6
V6
U7
U6

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

W3
Y3
W12
V5
W4
W5
Y5
Y4
V4
U10
W10

DRE1
DRE5
DRE6
DRE0

DCLK
DVS
DHS
DEN

DRE7
DRE3
DRE2
DRE4
DGE1
DGE0
DGE3
DGE2
DGE7
DGE6
DGE5
DGE4
D[15..0]

DBE0
DBE3
DBE1
DBE2
DBE4
DBE7
DBE6
DBE5

Y20
W20
V20
V19

DR1 RP1302
DR5
DR6
DR0

DRE1
DRE5
DRE6
DRE0

U20
U19
R16
R18

DR7 RP1303
DR3
DR2
DR4

DRE7
DRE3
DRE2
DRE4

T20
T19
R20
R19

DG1 RP1304
DG0
DG3
DG2

DGE1
DGE0
DGE3
DGE2

P20
P19
P18
M18

DG7 RP1305
DG6
DG5
DG4

DGE7
DGE6
DGE5
DGE4

M17
L17
N20
M20

DB0 RP1306
DB3
DB1
DB2

DBE0
DBE3
DBE1
DBE2

M19
L20
L19
K17

DB4 RP1307
DB7
DB6
DB5

DBE4
DBE7
DBE6
DBE5

K19
DRO0
K20
DRO1
K18
DRO2
PW181 Display Port
J20
DRO3
J18
DRO4
J19
DRO5
H20
DRO6
H19
DRO7
DGO0
DGO1
DGO2
DGO3
DGO4
DGO5
DGO6
DGO7

ROMOEn
ROMWEn

DBO0
DBO1
DBO2
DBO3
DBO4
DBO5
DBO6
DBO7

B20
C19
V14

H18
H17
G20
G19
G18
F20
F19
F18
E20
E19
E18
F17
D20
D19
D16
D17

C1304

4
C1355

DR1
DR5
DR6
DR0
DR7
DR3
DR2
DR4
DG1
DG0
DG3
DG2
DG7
DG6
DG5
DG4
DB0
DB3
DB1
DB2
DB4
DB7
DB6
DB5

V25

L1302

RP1308

DGE[7..0]

RP1309

RP1310

RP1311

RP1312

RP1313

DRE[7..0]

DRE3
DRE7
DRE0
DRE2
DRE1
DRE5
DRE4
DRE6
DGE3
DGE2
DGE5
DGE4

DGE[7..0]

DGE1
DGE0
DGE7
DGE6
DBE[7..0]
DBE2
DBE5
DBE3
DBE4
DBE6
DBE1
DBE0
DBE7

C1305 C1306 C1307 C1308 C1309

C1325
C1326

SDA_H3V

DBE[7..0]

For Samsung/Formosa panel

2005.05.22

D0
D1
D2
D3
D4
D5
PW181 MISC
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

A[19..1]

U1302
5V

Q1302
SDA_H5V

PORTB0
PORTB1
PORTB2
PORTB3
PORTB4
PORTB5
PORTB6
PORTB7

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

RNMI2
D3V3C

R1317
R1318
R1319
R1320

DRE[7..0]

U4
T4
V3
U3
Y1
W2
T3
V2
U2
W1
R4
V1
P4
R3
T2
U1
T1
R2
R1
P3

SCL_H3V

R1316

SDA_H5V

PORTA0
PORTA1
PORTA2
PORTA3
PORTA4
PORTA5
PORTA6
PORTA7

Q1301

R1314
5Vstby

IRRCVR0
IRRCVR1

R1324

R1311
R1312

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

RXD
TXD

R1325

R1334

GBO0
GBO1
GBO2
GBO3
GBO4
GBO5
GBO6
GBO7

RESET
MCKEXT
DCKEXT
XI
XO

R1333

COMMUNIC
P_SCLK
P_SDATA
P_SLE
DTXON
HPD_DET

MREST
VG0
VG1
VG2
VG3
PW181 Video Port
VG4
VG5
VG6
VG7

V13
W13
Y13
Y14
W14
Y15
W15
V15

KEY0
KEY1
KEY2
KEY3
KEY4
KEY5
KEY6
SP_RELAY

GND

GBE[7..0]

E4
C3
B1
F4
C2
C1
D3
D2

Y11
E5
D6
A3
C5

VGASEL

A11
D10
C14
A18
C9

GFBK
GREF
GBLKSPL
GCOAST
GHSFOUT

GGE[7..0]

GRE0
GRE1
GRE2
GRE3
GRE4
GRE5
GRE6
GRE7

GCLK
GPEN
GVS
GHS
GSOG

A10
B9
A9
C10
B10

J17
C20
D18
N19

R1323

U1301A
GCLK
GPEN
GVS
GHS
GSOG
GRE[7..0]

C1354
DCLK
DVS
DHS
DEN

R1321

R1307

7
U1301C

RESET

R1306
GCOAST
GBLKSPL
GFBK

R1329

181 LVDS
R6
R0
R7
R1
R2
R0
R3
R1
R4
R2
R5
R3
R6
R4
R7
R5

D3V3B

R1335
U1303
D3V3B

V25

V15p

V15

D3V3B
3

TAB

V15

L1304

C1313

C1314 C1315

C1322 C1321 C1320 C1319 C1318 C1317 C1316

C1331 C1330 C1329 C1328

4
C1357
C1312

C1344

T15
T14
T13
T12
T11
T10
T9
T7
T6
R15
R14
R13
P16
P15
P6
P5
N16
N15
N6
N5
L5
K16
K5
J5
H16
H5
F16
E15
E14
E13
E12
E11
E10
E9
E7

C4
B4
VPP2
VPP1

VDD35
VDD34
VDD33
VDD32
VDD31
VDD30
VDD29
VDD28
VDD27
VDD26
VDD25
VDD24
VDD23
VDD22
VDD21
VDD20
VDD19
VDD18
VDD17
VDD16
VDD15
VDD14
VDD13
VDD12
VDD11
VDD10
VDD9
VDD8
VDD7
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1

U13
U11
U9
U5
T16
A2
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1

VIO19
VIO18
VIO17
VIO16
VIO15
VIO14
VIO13
VIO12
VIO11
VIO10
VIO9
VIO8
VIO7
VIO6
VIO5
VIO4
VIO3
VIO2
VIO1

T8
R8
R7
R6
M16
M5
L16
J16
G16
G15
G6
G5
F15
F14
F7
F6
F5
E8
E6

GND

INPUT OUTPUT

U1301E

V15
C1333 C1334 C1335 C1336 C1337 C1338 C1339 C1340 C1341 C1342 C1343

PW818 POWER AND GROUND

A
V15

V15p

L1301

GND59
GND58
GND57
GND56
GND55
GND54
GND53
GND52
GND51
GND50
GND49
GND48
GND47
GND46
GND45
GND44
GND43
GND42
GND41
GND40
GND39
GND38
GND37
GND36
GND35
GND34
GND33
GND32
GND31
GND30
GND29
GND28
GND27
GND26
GND25
GND24
GND23
GND22
GND21
GND20
GND19
GND18
GND17
GND16
GND15
GND14
GND13
GND12
GND11
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1

C1349 C1350

C1332

C1351 C1352 C1353

Y7
U14
U12
R5
P17
N18
N17
N13
N12
N11
N10
N9
N8
M13
M12
M11
M10
M9
M8
L18
L13
L12
L11
L10
L9
L8
K13
K12
K11
K10
K9
K8
K4
J13
J12
J11
J10
J9
J8
H13
H12
H11
H10
H9
H8
H4
G17
G4
D15
D13
D12
D11
D9
D8
D5
D4
B3
B2
A1

C1346

Title
Size

Date:
File:
1

13-SCALER
Number

Revision

A3

14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
7

31RAMA0 40
31RAMA1 38
31RAMA2 36
31RAMA3 34
31RAMA4 33
31RAMA5 35
31RAMA6 37
31RAMA7 39
31RAMA8 41
31RAMA9 43
31RAMA10 42
31RAMA11 45
31RAMA12 46
31RAMA13 44

U1201A

VUV[7..0]

95
96
97
98
99
100
101
102

VUV0
VUV1
VUV2
VUV3
VUV4
VUV5
VUV6
VUV7

109
110
111
112
113
114
115
116
105
106
107
108

VVCLK
VVVS
VVHS

DG0
DG1
DG2
DG3
DG4
DG5
DG6
DG7

VG0
VG1
VG2
VG3
VG4
VG5
VG6
VG7
VR0
VR1
VR2
VR3
VR4
VR5
VR6
VR7

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

VR0
VR1
VR2
VR3
VR4
VR5
VR6
VR7

RP1201

RP1202

149
150
151
152
153
154
155
156

RP1203

139
140
141
142
143
144
145
148

RP1205

RP1204

125
126

ADSVM
ADR
ADG
ADB
VREFIN
VREFOUT
RSET
COMP

117
118

VB[7..0]
R1203

132

MREST
R1215

C1244

73
72
135

X1201
74

136 R1212
PW1231 VIDEO BLOCK
DCLK
137 R1211
DVS
138 R1213
DHS

PVCLK
CREF
PVVS
PVHS

U1201B
127
128
129
130
131

R1204
R1205
R1206
R1207
R1208

119
120

VB0
VB1
VB2
VB3
VB4
VB5
VB6
VB7

RP1206

V33SW

C1201 C1202

VG[7..0]

VG0
VG1
VG2
VG3
VG4
VG5
VG6
VG7

V33SW
R1201 R1202

C1241

VCLK
VVS
VHS

12
21
18
15

C1218
81

TDO
TCK
TDI
TMS
TRST
I2CA1
I2CA2

51

MCLK

R1209 R1210

PW1231 HOST IF BLOCK

XTALI
XTALO

C1204

TESTCLK
TEST
CGMS
MACRO

38
V25SW
3

C1203

INPUT OUTPUT

R1214

25

TAB

31RAMA0 23
31RAMA1 24
31RAMA2 25
31RAMA3 26
31RAMA4 29
31RAMA5 30
31RAMA6 31
31RAMA7 32
31RAMA8 33
31RAMA9 34
31RAMA10 22
31RAMA11 35

2
C1242

C1205 C1206 C1207 C1208 C1209

AV331
U1204

C1211

5V

V33SW
INPUT OUTPUT
GND

C1243

TAB

2
4

C1245

31RAMA12 20
31RAMA13 21

C1222

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1

U1203

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

CKE

8
71
104
134
1
9
53
79
91
122
147
78
76
123
11
29
32

17
20
23
14

VSS0
VSS1
VSS2
VSS3

U1201D

PVSS0
PVSS1
PVSS2
PVSS3
PVSS4
PVSS5
PVSS6
DPAVSS
DPDVSS
MPAVSS
ADDVSS
ADAVSS
ADGVSS
AVS33B
AVS33G
AVS33R

VDD0
VDD1
VDD2
VDD3
PVDD0
PVDD1
PVDD2
PVDD3
PVDD4
PVDD5
PVDD6

DPAVDD
DPDVDD
MPAVDD

7
70
103
133
30
52
80
90
121
146
160

AVS33SVM AVD33SVM

31RAMD0
31RAMD1
31RAMD2
31RAMD3
31RAMD4
31RAMD5
31RAMD6
31RAMD7
31RAMD8
31RAMD9
31RAMD10
31RAMD11
31RAMD12
31RAMD13
31RAMD14
31RAMD15

37
B
C1226

V25SW

V33SW1
V33SW

V25SW

AV25A V33SW

L1201

AV331

L1205

C1219 C1220 C1221 C1223

C1210 C1212 C1213 C1214 C1215 C1216 C1217

AV25p1

C1237 C1238 C1239 C1240

C1249

77
75

C1250

AV25p2
124

PW1231 POWER AND

10 GROUND
ADDVDD
28
AV25a
ADAVDD
31
ADGVDD
AVD33B
AVD33G
AVD33R

2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53

V33SW

L1203

16
19
22

V33SW1

V25SW

AV25P1

L1204

AV331

C1247

V25SW

AV25P2

L1202

C1234 C1235 C1236

C1227 C1228 C1229 C1230 C1231 C1232 C1233

C1248

C1224 C1225

C1246

Title

13
Size

12-DEINTERLACE
Number

Revision

B
Date:
File:
1

6
12
28
41
46
52
54
19
15
39
36
40

16 31WEn
17 31CASn
18 31RASn

V33SW

VssQ
VssQ
Vss
Vss
VssQ
VssQ
Vss
/CS
DQML
DQMH
NC
NC

WE
CAS
RAS

CLK

U1202

24

R1216
R1217
R1218

V33SW

DEN

C1251

26
27

48
49
50

MRAS
MCAS
MWE

U1201C

RESET

5V

ADR:0x64

47

V33SW

SCL
SDA

31RAMD15
31RAMD14
31RAMD13
31RAMD12
31RAMD11
31RAMD10
31RAMD9
31RAMD8
31RAMD7
31RAMD6
31RAMD5
31RAMD4
31RAMD3
31RAMD2
31RAMD1
31RAMD0

1
3
9
14
27
43
49

VY[7..0]

VY0
VY1
VY2
VY3
VY4
VY5
VY6
VY7

SVHS
SVVS
SVCLK

157
158
159
2
3
4
5
6

68
MD15
66
MD14
64
MD13
62
MD12
60
MD11
58
MD10
56
MD9
54
MD8
55
MD7
57
MD6
59
MD5
61
MD4
63
MD3
PW1231 MEMORY
65 BLOCK
MD2
67
MD1
69
MCLKFB
MD0
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13

Vdd
VddQ
VddQ
Vdd
Vdd
VddQ
VddQ

92
93
94

DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7

GND

VB0
VB1
VB2
VB3
VB4
VB5
VB6
VB7

SCL_S3V
SDA_S3V

82
83
84
85
86
87
88
89

VR[7..0]

14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
6

SC102

A5V

SC101

SC103

SC104

C1026
16

L1004

D
YPbPr_Pr
VGA R

YPbPr_Y

YPbPr_Y
VGA G

SGND

S1A
S2A
S1B
S2B

11
10
14
13
1
15

VGASEL

VGASEL

U1004

DB

S1C
S2C

DC

S1D
S2D

DD

IN
EN

HD1_G/Y

HD1_B/Pb

HD1_G/Y
HD1_B/Pb

12

14

R1007
1

R1009

U1007A
R1015

HD1_R/Pr

SGND

R1005
VGAHS

HD1_R/Pr

TVDD3.3V

DA

AGND

5
6

YPbPr_Pb
VGA B

YPbPr_Pb

2
3

GND

YPbPr_Pr

VCC

VGA_HS

VGA_HS

U1007B
5V

VGA5V

D1006 R1019
R1008

VGAVS

11

10

13

U1007C
R1016
5V

12

VGA_VS

VGA_VS

5V
D1003

15

DDCD

13
12

DDCD
11

D1005

L1001

B
C1003

VGA G

L1003

VGA R
R1011

R1012

R1013

Title
Size

SGND

Date:
File:
2

Number

Revision

A4

SGND

10-PROGRESSIVE_ADC

16

17

8
1
2
3

VCC
NC1
NC2
NC3

VGA B

L1002

VCLK
SCL
SDA
GND

R1022

VGA5V

5
10
4
9
3
8
2
7
1
6

14

DDCC

5V
D1004

7
6
5
4

DDCC

D1002

JP1001

D1015

U1008
5V

VGAHS

R1021

C1042

VGAVS

R1020

U1007D

5V
D1001

D1007

R1010

R1006

C1041

14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
4

ADR:0xA0/MEMORY
ADR:0xD0/COMPANION

U401
26
28
11
12
14
47

ROMOEn
ROMWEn

RESETn
D3V3B
R401

CE
OE
WE
RESET
NC
BYTE

25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16

D3V3B
37

Vdd

29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

R402
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

13

NC

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

C401

C418 C419
SW402

U402

D3V3B
1

R408

R404

NMI

R407

C406

46
27

L401

C417

R410

D15
D14
D5
D4
D3
D2
D9
D8

2
1

U404

3
4

D3V3B

C410

A1
A3
A5
A7
A8
A10

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

R411

R412

R413

TXD

TXD

R417

RXD

R416

11
10

RXD

12
9
C415

C2+
V-

C412

JP403

C2T1_IN

T1_OUT

T2_IN

T2_OUT

R1_OUT

R1_IN

R2_OUT

R2_IN

14

L403

232_IN

7
13

1
6
2
7
3
8
4
9
5

232_OUT

L402

8
C413

C414

B
10

C416

C411
V+

C1-

GND

R418

A13
A15
A16
A18

C1+

15

A17
A19

NC0

5V#

C420

JP402

A12
A14

NC1

VCC

D3V3B

WP

4
3

L405

C409

A9
A11

NC2

D3V3B
2
4

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

GND

SCL

5V

A2
A4
A6

SDA

C402

Vss
Vss

JP401
1
3

L404

5V

R409

SCL_H5V

R405

5Vstby

FLASH_8M

SDA_H5V

9
10
15

A19
NC
RY/BY

11

16

A[19..1]

VCC

D7
D6
D13
D12

JP404

D3V3B
R419

TXD
RXD

D11
D10

R414

C405
7

R420
R421

R415

U403

SW401
D1
D0
2

RSTINn

TLCCT

3
1

C408

C407

SENCE Vdd
RESin
RESET
CT
RESET
CONTROL
GND

5V

SDA#SO
SCL#SO

4
3
2
1

SDA#SO
SCL#SO

R422
6

RESET

RESET

RESETn

4
R406

D[15..0]
A

Title
Size

4-FLASH
Number

Revision

A3
Date:
File:
1

14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
7

For sumsung panel standard LVDS jack

TX0+

TX1-

C523

C525

SCL_S3V

C502

R501

L505

PDPGO
R511

TX2-

10

TX2+ 11

12

P_SDATA#

13

14

P_SCLK#

CK+ 15

16

P_SLE#

TX3- 17

18

P_DISPEN#

TX3+ 19

20

CKC501

R513
R510

TX1+

P_SDATA
D

Formosa panel PDPGO

VS_ON#
P_SCLK

P_SCLK

C528
SDA_S3V
L506

IRQ

P_SLE

P_SLE

C529

L503

PDWN

P_DISPEN

P_DISPEN

RS
C526

R502
For LG panel standard LVDS jack

31

SGND

DCLK

DCLK

DRE[7..0]

DGE[7..0]

DBE[7..0]
DHS
DVS
DEN

DHS
DVS
DEN

DRE2
DRE3
DRE4
DRE5
DRE6
DRE7
DRE0
DRE1
DGE2
DGE3
DGE4
DGE5
DGE6
DGE7
DGE0
DGE1
DBE2
DBE3
DBE4
DBE5
DBE6
DBE7
DBE0
DBE1

51
52
54
55
56
3
50
2
4
6
7
11
12
14
8
10
15
19
20
22
23
24
16
18
27
28
30
25

TxCLK_IN
TxIN0
TxIN1
TxIN2
TxIN3
TxIN4
TxIN6
TxIN27
TxIN5
TxIN7
TxIN8
TxIN9
TxIN12
TxIN13
TxIN14
TxIN10
TxIN11
TxIN15
TxIN18
TxIN19
TxIN20
TxIN21
TxIN22
TxIN16
TxIN17
TxIN24
TxIN25
TxIN26
TxIN23

TxOUT0TxOUT0+
TxOUT1TxOUT1+
TxOUT2TxOUT2+
TxOUT3TxOUT3+
TxCLKOUTTxCLKOUT+

U501

PWR_DWN
R_FB

48
47
46
45
42
41
38
37
40
39

TX0TX0+
TX1TX1+
TX2TX2+
TX3TX3+
CKCK+

32 DTXON
17
LVD33

/ DS90C385AMTD
PLL_GND
PLL_GND
LVDS_GND
LVDS_GND
LVDS_GND

1
2
3
4
5
6
TX27
TX2+
8
CK9
CK+
10
TX311
TX3+
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
p_dispen# 27
p_sdata# 28
29
p_sclk#
30
p_sle#
31
TX0TX0+
TX1TX1+

For LG panel

35
33
R508
49
43
36

DTXON
R509

NC

U502
5V

LVD33
3

INPUT OUTPUT
GND

LVD_VCC
C521

For sumsung panel

DRE0
DRE1
DRE2
DRE3
DRE4
DRE5
DRE6
DRE7
DGE0
DGE1
DGE2
DGE3
DGE4
DGE5
DGE6
DGE7
DBE0
DBE1
DBE2
DBE3
DBE4
DBE5
DBE6
DBE7

TX0-

P_SDATA

C527

TAB

2
4
C507

C505

C510

SGND
Title

5
13
21
29
53

Size

5-LVDS&TMDS
Number

Revision
00

A4
Date:
File:
1

C506
1

NC

L502

C524

22

C522

21

TX3TX3+

C520

L504

CPUGO

R504

44
34

CKCK+

JP501

LVDS_VCC
PLL_VCC

TX2TX2+

R503

LVD_PLL33

1
9
26

TX1TX1+

L501

VCC
VCC
VCC

Formosa panel CPUGO

RELAY_ON#

R512
LVD33

GND
GND
GND
GND
GND

TX0TX0+

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
4

ANDY

3
U604

D3V3B

5V
2

D3V3#

C623

C614

C622

TAB

D3V3#
2

5VSC

C613
1

OUTPUT INPUT
TAB

C601

RELAY_ON#

C603

U603

5Vstby#

D3V3C

1
2
3
4
5
6
7
8
9

D605

C621

5
JP608

D6V

OUTPUT INPUT

GND

L606

R630

L602
5V
D

5VSC

L607

JP607

L608

C624

C618

C626

C625

R628

C617

1
2
3
4
5
6
7
8
9
10
11

For SDI V3 HD Panel

2005.06.14
D3V3D
L628

L605

5Vstby

R629

C630

C651

C654

C655

RELAY_ON#
5Vstby#

RELAY_ON
L623

C612

C602

VS_ON
5VDetect

L624

VS_ON#

L625
C649

D3V3_TT_A

R635
U601
PA3

PA4

PA2

PA5

18

mut#

MUTE
R627

SB_5VCN

17

key_stby

key_stby

17

Q606

Q605
5VDetect

PA1

PA6

16

5VDetect

SDA#

PA1

PA6

16 SDA#

R617

SDA_H5V

D3V3B

5Vstby

R624

5Vstby

L620
L621
L622

C628

OSCO

14

OSCO

13

OSCI

P_ON/SLEEP

PA0

PA7

PB2

OSCO

15 SCL#

R618

SCL_H5V

C629
P_DISPEN

COMMUNIC 6

PB1/_BZ

OSCI

PB0/BZ

VDD

P_DISPEN
COMMUNIC

P_DISPEN

COMMUNIC

R616

PB1/_BZ

OSCI

PB0/BZ

VDD

14

OSCO

13

OSCI

5V_mcu
7

VSS

/RES

C608

RST

VSS

/RES

R622 R623

IR_mcu

R632
R631
R633

R625

5V_mcu

12
11

R621

IR_181

Q607

X601

12
R626

R619

11 RST

C610

R620

C611

5Vstby

B
9

PC0/_INT PC1/TMR

IR_mcu

10

PC0/_INT PC1/TMR

D3V3B

C609

R606

RELAY_ON

R610

C633

Q601

R607

R603

JP604
To Key Board

Q602
A

13
12
11
10
9
8
7
6
5
4
3
2
1

STANDBY
P+
PVV+
MENU
INPUT

L611
L612
L613
L614
L615
L616
L617
C635

R602

P_ON/SLEEP

D602
D603
D604

KEY0
KEY1
KEY2
KEY3
KEY4
KEY5
KEY6

R605

C634

5Vstby
R601

R609

R615
D3V3B

D3V3B

10

R608

IR_mcu

LED_G
IR_5V

C640

PA7

PB2

SCL#

R611

PA0

15

C636

P_ON/SLEEP 4

5V

C641

R614

PA5

VS_ON

mut#

R613

PA2

18

C639

PA4

LED_R

R612

PA3

D601

C644

Q603

U602

C632

R643

R642

R641

R640

R639

5Vstby

C637

VS_ON

SGND
1

VS_ON#
RELAY_ON#

C642

C648

D610

L629

C643

C650

C638

C631

L601

5V_mcu

R604
Title
Size

6-POWER MANAGE
Number

Revision

B
Date:
File:
1

From pannel

GND

14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
6

5V_E

R765

V_TVCVBS

R705
Y

Cr
Q733

Q734

C760

GYCbCr_Cr
C762

R749

C701

C763

GYCbCr_Y
C765

R763

C766

R767

L748

A5V

SGND

A5V

SGND

5V_E

R787

L738

JP701

VCC

C711

C702

C710

R721

R719

SGND
GYCbCr_Cb

4 Pb_in

Q701
A5V

VYCbCr_Cb
R736

R720

C753

R722

C737

SGND

Cb_in#

R723

SGND
C738

Cr_in#

GYCbCr_Cr

VYCbCr_Cr

R751
R737 R724

L752

TT_R

TT_R
SC1_R

2
3

TT_G

TT_G
SC1_G

5
6

TT_B
SC1_B

11
10

TT_FSO
SC1_BOX

14
13

TT_SEL

1
15

Q702
D702

YUV_Y_in

R709

S1A
S2A

R726

SGND

SGND

TT_B
P15V330 Truth Table
IN EN
ON Switch
0
0 S1A S1B S1C S1D
1
0 S2A S2B S2C S2D
x
1 Disabled

C739

C754

TT_FSO
TT_SEL

5V_E

C709

U704

DB

S1C
S2C

DC

S1D
S2D

V_TT_G

V_TT_B

V_TT_R

V_TT_B

DVI_L_IN#

R776

DVI_L_IN 3

V_TT_FSO

DVI_R_IN#

R780

DVI_R_IN 2

AGND

SGND

JP707
5V

VGA_L4#
SC2_BOX

R784

V2

R791
VYCbCr_Y

R738

D704

R753

R728

C714

C752

C755

C713

C715

C716

C718

R788

R773

SC2_R

R785

C2

R774

SC2_G

R786

Y2

R775

SC2_B

VGA_R4#

R713

Q703

YPbPr_Pb
5V
C746

R772

C729

L753

SGND

R777

VGA_L4

R781

VGA_R4

3
4
2
1

C733

A5V R794
R732

R714

Pb_in

C2
V2
Y2

JP705

GYCbCr_Y

C751

V2
C2
Y2

AGND SGND

SGND

R729

R727

D703

R752

A5V

V_TT_G

5V
C744

50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

JP703

12 V_TT_FSO

DD

IN
EN

YUV_Y_in#

SGND
4 V_TT_R

DA

S1B
S2B

V_AVCVBS
V_SVideo_C
V_SVideo_Y

A5V

L739

R731

Cr

5V
C742

R707

Cutoff frequency : 6.4MHz

16

R725

49
47
45
43
41
39
37
35
33
31
29
27
SDA_S5V 25
3450_rest 23
MUTE
21
SP_RELAY 19
3230_VO 17
15
TV_M
TV_S
13
V_AVCVBS11
V_SVideo_C 9
V_SVideo_Y 7
AV_LOUT 5
AV_ROUT 3
1
+8V

SDA_S5V
3450_rest
MUTE
SP_RELAY
3230_VO

R711

L751

C708

SGND
D701

GPIO_P32
GPIO_P33
SC2_BOX
SC2_R
SC2_G
SC2_B
SC1_SW
SC1_BOX
SC1_R
SC1_G
SC1_B

R768
R769
R770
R771

A5V

R708

6
5

C706

5V_E

5V
R750

Cr_in

GND

R706

R790

C740

VCC

AGND

L750
Cb_in

VOUT

SC2_SW
GPIO_P31
GPIO_P30

VF

RFC

VCC

SGND

G_TVCVBS

C707

GSEL

ENABLE

L749

R742

SGND

VIN

C736

5 YUV_Y_in
7

R730

Cb

R741

C705

GND

6 HD_Y_in

GPIO_P32
GPIO_P33
G_TT_FSO
G_TT_R
G_TT_G
G_TT_B
SC1_SW

U703
TV_S

SGND

3 Cb_in

G_TVCVBS

R710

1 Cr_in

SCL_S5V

SCL_S5V
SC2_SW
GPIO_P31
GPIO_P30

R704

R702

Cutoff requency : 6.4MHz

2 Pr_in

GND

R701

V_AVCVBS

R743

G_AVCVBS

G_AVCVBS

C704

R733

R703

VOUT

V_SVideo_C

R744

G_SVideo_C

G_SVideo_C

VF

RFC

4
SGND

GSEL

ENABLE

R734

C703

V_SVideo_Y

R745

G_SVideo_Y

G_SVideo_Y

VIN

Q735

GYCbCr_Cb
C759

R735

V_TVCVBS

U702
TV_M

R761

Cb

R712

R748

5V_E

C728

5V_E

C732

SGND
SGND

SGND

AGND
JP704

SGND
8V_4052

YPbPr_Y
DVI_L_IN#

C719

VGA_L4#

C720

YPbPr_L_IN#

C721

5V
C750

R755

D706

AV_L1
AV_L2
AV_L3
AV_L4

1
5
2
4

Y0A
Y1A
Y2A
Y3A
Y0B
Y1B
Y2B
Y3B

ZA
ZB
A1
A0
E

13 R_O C756

AV_ROUT

L_O C757

AV_LOUT

YUV_L_IN#

R740

R739

AV_L2

R77

AV_L3

R78

AV_L4

R79

R71

9
10
AGND

6
SEL1

SEL1
C743

R792

R793
Q704

Q705

SEL0

Date:
File:
4

7-VIDEO&AUDIO IN
Number

Revision

A3

C725

AGND

Size

C741

SGND
2

YPbPr_R_IN 2

Title

SEL0

AGND
1

YPbPr_L_IN 4

R782

AV_L1

YUV_R_IN 1

R778

YPbPr_R_IN#

R718

12
14
15
11

R76

R783

YPbPr_L_IN#

C731

AV_R1
AV_R2
AV_R3
AV_R4

R75

YUV_R_IN#

R717

C726

AV_R4

R70

C735

C724

YUV_R_IN#

VDD

YPbPr_R_IN#

VSS
VEE

HD_Y_in

SGND

8
7

L755

8V_4052

AV_R3

R74

R716

AGND

AGND U701

R73

C730

C723

R72

AV_R2

R715

R759

AV_R1

YUV_L_IN 3

C734

VGA_R4#

C787

C780

L_O

D705

C790

R758

R779

C781

C722

YUV_L_IN#

L756

C789

AGND
DVI_R_IN#

R754

8V_4052

R757

YPbPr_Pr
5V
C748

+8V

R756

16

L754

Pr_in

R_O

SGND

14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
7

Audio.Board.BH(M-CH).05.06.14.sch-1 - Tue Aug 16 22:15:14 2005

DUBHE OSD Ver1.1_NAKS.sch-1 - Mon Oct 18 11:47:11 2004

0025.sch-1 - Mon May 16 09:25:50 2005

Basic Operations & Circuit Description

MODULE
There are 1 pc. panel and 12 pc.s PCB including 2 pc.s Y/Z Sustainer board, 2 pc.s Y Drive
board, 6 pc.s X Extension boards, 1 pc. Control (Signal Input) and 1 pc. Power
board in the Module.

SET
There are 6 pc.s PCBs including 1 pc. AUX. PSU Board, 1 pc. Keypad board, 1 pc.
Remote Control Receiver board, 1 pc. L/R Speakers and 1 pc. Main (Video) board in the SET.

E-extension Top
L/C/R

Control Board Assay

Power supple

Internal Speaker
terminal

AUX PUS Board

Y-driver TOP

Y-sustainer

Z-sustainer

EMI Filter & AC

Intel

Y-driver Bottom

Local Key

Stand

Main ( Video)

Turner / Audio

X-extension
Bottom L/C/R

PCB function

1. Power:
(1). Input voltage: AC 100V~120V, 45Hz~60Hz.
Input range: AC 90V(Min)~265V(Max) auto regulation.
(2). To provide power for PCBs.
2. Main (Video InterFace) board: To converter TV signals, S signals, AV signals, Y Pb/
Cb Pr/Cr signals, DVI signals and D-SUB signals to digital ones and to transmit to
Control board.
3. Control board: Dealing with the digital signal for output to panel.
4. Y-Sustainer / Z-Sustainer board:
(1). Receiving the signals from Control and high voltage supply.
(2). Output scanning waveform for Module.
5. Y-Drive board: Receive signal from Y sustainer, output horizontal scanning waveform to the panel.
6. X extension board (6pcs): Output addressing signals.
: Process and Amplifying the audio signal to speakers and
7. Tuner/Audio Board:
convert TV RF signal to video/audio signal and send to Main board.

PCB failure analysis

1. CONTROL
:
2. MAIN (video) :

a. Abnormal noise on screen. b. No picture.

a. Lacking color, Bad color scale.
b. No voice.
c. No picture but with signals output, OSD and back light.
d. Abnormal noise on screen.
3. POWER
: No picture, no power output.
4. Z - Sustainer : a. No picture.
b. Color not enough.
c. Flash on screen.
5. Y - Sustainer : Darker picture with signals.

6. X - Extension : Abormal vertical noise on screen.

7. Audio Board or AUX PSU: a. No voice. (Make sure Mute/OFF) .
b. Noise.

Basic operation of Plasma Display

1. After turning on power switch, power board sends 5Vst-by Volt to Micro Processor

2. The micro Processor memorize the last state of Power, When the last state of
power is on or receive power on signal from local Key or Remote control, Micro
Processor will send on control signal to power. Then Power sends (5Vsc, 9Vsc,
24V and RLYON, Vs ON) to PCBs working. This time VIF will send signals to
display Image, OSD on the panel and start to search available signal sources.
If the audio signals input, them will be amplified by Audio AMP and transmitted to
Speakers.
3. If some abnormal signals are detected (for example: over volts, over current, over
temperature and under volts), the system will be shut down by Power off.

Main IC Specifications

- PW181 Image Processor, Scaler

- PW1231 Digital Video Signal Processor
- VPC 323XD Comb-filter Video Processor
- Z86229 NTSC Line 21 CCD decorder
- MSP34x0G Multistandard Sound Processor
-AD9880 Analog/HDMI Dual Display Interface
-PI5V330 Wideband/Video Quad 2-Channel MUX/DEMUX
-SM5304AV Video Buffer with Built-in Analog LPF
-TDA2616 2 X 12 W hi-fi audio power amplifier with mute
-SAA5360 Multi page intelligent teletext decoder
-AT24C32 Z-Wire Serial EEPROM
-HT48R06A-1 8-Bit Cost-Effective I/O Type MCU

PW181
Product Specification
General Description
The PW181 ImageProcessor is a highly integrated
system-on-a-chip that interfaces computer graphics and
video inputs in virtually any format to a fixed-frequency flat
panel display.
Computer and video images from NTSC/PAL to WUXGA
at virtually any refresh rate can be resized to fit on a fixedfrequency target display device with any resolution up to
WUXGA. Video data from 4:3 aspect ratio NTSC or PAL
and 16:9 aspect ratio HDTV or SDTV is supported. Multiregion, nonlinear scaling allows these inputs to be resized
optimally for the native resolution of the display.
Advanced scaling techniques are supported, such as
format conversion using multiple programmable regions.
Three independent image scalers coupled with frame
locking circuitry and dual programmable color lookup
tables create sharp images in multiple windows, without
user intervention.
Embedded SDRAM frame buffers and memory controllers
perform frame rate conversion and enhanced video
processing completely on-chip. A separate memory is
dedicated to storage of on-screen display images and
CPU general purpose use.
Advanced video processing techniques are supported
using the internal frame buffer, including motion adaptive,
temporal deinterlacing with film mode detection. When
used in combination with the new third-generation scaler,
this advanced video processing technology delivers the
highest quality video for advanced displays.
Both input ports support integrated DVI 1.0 content
protection using standard DVI receivers.
A new advanced OSD Generator with more colors and
larger sizes supports more demanding OSD applications,
such as on-screen programming guides. When coupled
with the new, faster, integrated microprocessor, this OSD
Generator supports advanced OSD animation techniques.

Video
Input
TV
Signal

Video
Decoder

Crystal

TV Tuner

Com puter

ADC/
TMDS

PW181
Com puter
TV
Signal

Display

ADC/
TMDS

TV Tuner
Video
Decoder

Video
Input

ROM

PW181 System Block Diagram

Features

Third-generation, two-dimensional filtering techniques

Third-generation, advanced scaling techniques
Second-generation Automatic Image Optimization
Frame rate conversion
Video processing
On-Screen Display (OSD)
On-chip microprocessor
JTAG debugger and boundary scan
Picture-in-picture (PIP)
Multi-region, non-linear scaling
Hardware 2-wire serial bus support

Applications
Multimedia Displays
Plasma Displays
Digital Television
Device

Application

PW181-10V

Up to XGA Displays

PW181-20V

Up to UXGA Displays

Package
352 PBGA

Programmable features include the user interface, custom

start-up screen, all automatic imaging features, and
special screen effects.

PRELIMINARY / CONFIDENTIAL

110 MSPS/140 MSPS Analog Interface

for Flat Panel Displays
AD9883A

FEATURES
140 MSPS Maximum Conversion Rate
300 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 110 MSPS
3.3 V Power Supply
Full Sync Processing
Sync Detect for Hot Plugging
Midscale Clamping
Power-Down Mode
Low Power: 500 mW Typical
4:2:2 Output Format Mode

FUNCTIONAL BLOCK DIAGRAM

RAIN

CLAMP

A/D

GAIN

CLAMP

A/D

BAIN

CLAMP

A/D

GENERAL DESCRIPTION

The AD9883A is a complete 8-bit, 140 MSPS monolithic analog

interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280 1024 at 75 Hz).
The AD9883A includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and Hsync and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9883As on-chip PLL generates a pixel clock from the
Hsync input. Pixel clock output frequencies range from 12 MHz to

ROUTA

GOUTA

BOUTA
MIDSCV

HSYNC

APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Microdisplays
Digital TV

COAST
CLAMP

DTACK

SYNC
PROCESSING
AND CLOCK
GENERATION

HSOUT
VSOUT
SOGOUT

FILT
REF
SCL
SDA
A0

SERIAL REGISTER
AND
POWER MANAGEMENT

REF
BYPASS

AD9883A

140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9883A also offers full sync
processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883A is
provided in a space-saving 80-lead LQFP surface-mount plastic
package and is specified over the 0C to 70C temperature range.

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:
Fax:

PW1231A
Product Specification
General

Crystal

The PW1231A is a high-quality, digital video signal

processor that incorporates Pixelworks patented
deinterlacing, scaling, and video enhancement
algorithms. The PW1231A accepts industry-standard
video formats and resolutions, and converts the input into
many desired output formats.The highly efficient video
algorithms result in excellent quality video.
The PW1231A combines many functions into a single
device, including a memory controller, auto-configuration,
and others. This high level of integration enables simple,
flexible, cost-effective solutions that require fewer
components.

Video

Video
Decoder

PW1231A
System Block Diagram

PW1231A
PW1231AL

Digital
Output

SDRAM

Features

Built-In Memory Controller

Motion-Adaptive Deinterlace Processor
Intelligent Edge Deinterlacing
Digital Color/Luminance Transient Improvement (DCTI/DLTI)
Interlaced Video Input Options, including NTSC and PAL
Independent horizontal and vertical scaling
Copy Protection
Two-Wire Serial Interface

Applications:
For use with Digital Displays

Flat-Panel (LCD, DLP) TVs

Rear Projection TVs
Plasma Displays
LCD Multimedia Monitors
Multimedia Projectors

Device

Application

Package

PW1231A
PW1231AL

Up to XGA

160-pin PQF

NOTE: L denotes lead (Pb) free

8100 SW Nyberg Road

Tualatin, OR 97062 USA
Telephone: 503.612.6700
FAX: 503.612.6713
www.pixelworks.com

P/N 001-0097-00 Rev B

July 2003

PRELIMINARYCONFIDENTIAL

Analog/HDMI Dual Display Interface

Preliminary Datasheet

AD9880

3/26/2004

FEATURES

8-bit Triple Analog to Digital Converters

150 MSPS Maximum Conversion Rate
Macrovision Detection
2:1 Input Mux
Full Sync Processing
Sync Detect for Hot Plugging
Mid-Scale Clamping

Digital Video Interface

HDMI 1.0, DVI 1.0
150 MHz HDMI Receiver
Supports High-Bandwidth Digital Content Protection
(HDCP 1.1)

Digital Audio Interface

HDMI 1.0 compatible audio interface
S/PDIF (IEC90658 compatible) digital audio output
Multi-channel I2S audio output (up to 8 channels)
APPLICATIONS
Advanced TV
HDTV
Projectors
LCD Monitor
GENERAL DESCRIPTION
The AD9880 offers designers the flexibility of an analog interface
and High-Definition Multimedia Interface (HDMI) receiver
integrated on a single chip. Also included is support for High
bandwidth Digital Content Protection (HDCP).
Analog Interface
The AD9880 is a complete 8-bit 150 MSPS monolithic analog
interface optimized for capturing Component Video (YPbPr) and
RGB graphics signals. Its 150 MSPS encode rate capability and
full power analog bandwidth of 300 MHz supports all HDTV
formats (up to 1080p) and FPD resolutions up to SXGA (1280 x
1024 at 75 Hz).
The analog interface includes a 150 MHz triple ADC with
internal 1.25V reference, a Phase Locked Loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only 1.8V and 3.3V power supply, analog input, and Hsync.
Three-state CMOS outputs may be powered from 1.8V to 3.3V.
The AD9880s on-chip PLL generates a pixel clock from Hsync.
Pixel clock output frequencies range from 12 MHz to 150 MHz.

AD9880 Preliminary Technical Information

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.

Analog Interface
R/G/B or YPbPrIN0
R/G/B or YPbPrIN1
HSYNC 0
HSYNC 1
HSYNC 0
HSYNC 1
SOGIN 0
SOGIN 1
COAST
CLAMP
CKINV
CKEXT
FILT

2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX

Clamp

R/G/B 8X3

A/D

or YCbCr

2
Sync
Processing and
Clock
Generation

DATACK
HSOUT
VSOUT
SOGOUT

REFOUT
REFIN

Ref

SCL
SDA

Serial Register and

Power Management

RGB YCbCr Matrix

Analog Interface

FUNCTIONAL BLOCK DIAGRAM

MUXES

Analog/HDMI Dual Interface

Supports High-Bandwidth Digital Content Protection
RGB to YCbCr two-way color conversion
Automated clamping level adjustment
1.8/3.3V Power Supply
100-pin LQFP Pb-Free Package
RGB and YCbCr Output Formats

R/G/B 8X3
YCbCr (4:2:2
or 4:4:4)
2

DATACK
HSOUT
VSOUT /A0
SOGOUT
DE

Digital Interface
R/G/B 8X3
or YCbCr

RX0+
2

RX0RX1+
RX1RX2+
RX2-

DATACK
DE
Hsync

HDMI Receiver

Vsync

RXC+

SPDIF OUT

RXCRTERM

8 Channel
I2S OUT

MCL
MDA
DDCSCL
DDCSDA

MCLK
LRCLK
HDCP

AD9880

PLL clock jitter is typically less than 500 ps p-p at 150 MHz. The
AD9880 also offers full sync processing for composite sync and
Sync-on-Green (SOG) applications.
Digital Interface
The AD9880 contains a HDMI 1.0 compatible receiver and
supports all HDTV formats (up to 1080p) and display resolutions
up to SXGA (1280 x 1024 at 75 Hz). The receiver features an
intra-pair skew tolerance of up to one full clock cycle. With the
inclusion of HDCP, displays may now receive encrypted video
content. The AD9880 allows for authentication of a video receiver,
decryption of encoded data at the receiver, and renewability of that
authentication during transmission as specified by the HDCP 1.1
protocol.
Fabricated in an advanced CMOS process, the AD9880 is provided
in a space-saving 100-lead LQFP surface-mount plastic package
and is specified over the 0 C to 70 C temperature range.

Analog Devices, Inc., 2004

One Technology Way, P.O Box 9106, Norwood, MA 020629106, USA

Tel: 617/3294700
Fax: 6173268703

VPC 323xD

PRELIMINARY DATA SHEET

Comb Filter Video Processor

1. Introduction
peaking, contrast, brightness, color saturation and
tint for RGB/ YCrCb and CVBS/S-VHS

The VPC 323xD is a high-quality, single-chip video

front-end, which is targeted for 4:3 and 16:9, 50/60-Hz
and 100/120 Hz TV sets. It can be combined with other
members of the DIGIT3000 IC family (such as
DDP 331x) and/or it can be used with 3rd-party products.

high-quality soft mixer controlled by Fast Blank

The main features of the VPC 323xD are

15 predefined PIP display configurations and expert

mode (fully programmable)

high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking

control interface for external field memory

1
- , or
PIP processing for four picture sizes ( 1--4- , 1--9-, ----16
1
--of
normal
size)
with
8-bit
resolution
36

I2C-bus interface

multi-standard color decoder PAL/NTSC/SECAM

including all substandards

one 20.25-MHz crystal, few external components

four CVBS, one S-VHS input, one CVBS output

80-pin PQFP package

two RGB/YCrCb component inputs, one Fast Blank

(FB) input

1.1. System Architecture

integrated high-quality A/D converters and associated clamp and AGC circuits

Fig.11 shows the block diagram of the video processor

multi-standard sync processing

linear horizontal scaling (0.25 ... 4), as well as
non-linear horizontal scaling Panoramavision
PAL+ preprocessing
line-locked clock, data and sync, or 656-output
interface

CIN
VIN1

Adaptive
Comb
Filter

Analog
Front-end

VIN2

Color
Decoder

NTSC
PAL
SECAM

Cr

Cb

VIN3
VIN4

AGC
2ADC

NTSC
PAL

VOUT

Saturation
Tint

Mixer

2D Scaler
PIP

Output
Formatter

Cr

Panorama
Mode

ITU-R 656
ITU-R 601

Cb

Contrast
Brightness

Memory
Control

Peaking

FB
RGB/
YCrCb

Processing Y
Analog
Component U/B
Cr
Matrix
Front-End
Contrast
V/R
Saturation Cb
Brightness
4 x ADC
FB
FB
Tint

I2C Bus

Clock
Gen.

20.25 MHz I2C Bus

Fig. 11: Block diagram of the VPC 323xD

Micronas

CrCb
OUT
YCOE

Y/G

RGB/
YCrCb

Y OUT

Sync
+
Clock
Generation

FIFO
CNTL

LL Clock
H Sync
V Sync
AVO

4'.+/+0#4; 41&7%6#2'%+(+%#6+10

<

  
+0'

'%1&'4








 
   


 
 

 
! "


Preprogrammed to Provide Full Compliance with

EIA608 Specifications for Extended Data Services

Minimal Communications and Control Overhead Provide Simple Implementation of Violence Blocking,
Closed Captioning, and Auto Clock Set Features

Automatic Extraction and Serial Output of Special

XDS Packets (Time of Day, Local Time Zone, and
Program Blocking)

Programmable, On-Screen Display (OSD) for Creating Full Screen OSD or Captions inside a Picture-inPicture (PiP) Window

User-Programmable Horizontal Display Position for

easy OSD Centering and Adjustment

I2C Serial Data and Control Communication

Complete Stand-Alone Line 21 Decoder for ClosedCaptioned and Extended Data Services (XDS)

#$ 
%
& % 



  
  
"
 '




Programmable XDS Filter for a Specific XDS Packet

Cost-Effective Solution for NTSC Violence Blocking
inside Picture-in-Picture (PiP) Windows

Supports 2 Selectable I2C Addresses

 
 
Capable of processing Vertical Blanking Interval (VBI)
data from both fields of the video frame in data, the Z86229
Line 21 Decoder offers a feature-rich solution for any television or set-top application. The robust nature of the
Z86229 helps the device conform to the transmission format
defined in the Television Decoder Circuits Act of 1990, and
in accordance with the Electronics Industry Association
specification 608 (EIA608).
The Line 21 data stream can consist of data from several data
channels multiplexed together. Field 1 consists of four data
channels: two Captions and two Texts. Field 2 consists of
five additional data channels: two Captions, two Texts, and
Extended Data Services (XDS). The XDS data structure is



defined in EIA608. The Z86229 can recover and display

data transmitted on any of these nine data channels.
The Z86229 can recover and output to a host processor via
the I2C serial bus. The recovered XDS data packet is further
defined in the EIA608 specification. The on-chip XDS filters in the Z86229 are fully programmable, enabling recovery of only those XDS data packets selected by the user. This
functionality allows the device to extract the required XDS
information with proper XDS filter setup for compatibility
in a variety of TVs, VCRs, and Set-Top boxes.
In addition, the Z86229 is ideally suited to monitor Line 21
video displayed in a PiP window for violence blocking,
CCD, and other XDS data services. A block diagram of the
Z86229 is illustrated in Figure 1.

MSP 34x0G

PRELIMINARY DATA SHEET

Multistandard Sound Processor Family

Release Note: Revision bars indicate significant
changes to the previous edition. The hardware and
software description in this document is valid for
the MSP 34x0G version B8 and following versions.

1. Introduction
The MSP 34x0G family of single-chip Multistandard
Sound Processors covers the sound processing of all
analog TV-Standards worldwide, as well as the NICAM
digital sound standards. The full TV sound processing,
starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip.
Figure 11 shows a simplified functional block diagram
of the MSP 34x0G.
This new generation of TV sound processing ICs now
includes versions for processing the multichannel television sound (MTS) signal conforming to the standard
recommended by the Broadcast Television Systems
Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free.
Other processed standards are the Japanese FM-FM
multiplex standard (EIA-J) and the FM Stereo Radio
standard.

ADC
Sound IF2

Demodulator

I2S1

All MSP 34xxG versions are pin compatible to the

MSP 34xxD. Only minor modifications are necessary
to adapt a MSP 34xxD controlling software to the
MSP 34xxG. The MSP 34x0G further simplifies controlling software. Standard selection requires a single
I2C transmission only.
The MSP 34x0G has built-in automatic functions: The
IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore,
pilot levels and identification signals can be evaluated
internally with subsequent switching between mono/
stereo/bilingual; no I2C interaction is necessary (Automatic Sound Selection).
The MSP 34x0G can handle very high FM deviations
even in conjunction with NICAM processing. This is
especially important for the introduction of NICAM in
China.
The ICs are produced in submicron CMOS technology.
The MSP 34x0G is available in the following packages:
PLCC68 (not intended for new design), PSDIP64,
PSDIP52, PQFP80, and PLQFP64.

Preprocessing

Prescale

I2S2

Source Select

Sound IF1

Current ICs have to perform adjustment procedures in

order to achieve good stereo separation for BTSC and
EIA-J. The MSP 34x0G has optimum stereo performance without any adjustments.

Loudspeaker
Sound
Processing

DAC

Headphone
Sound
Processing

DAC

Loudspeaker
Subwoofer

Headphone

I2S

SCART1
DAC
SCART2
SCART3

SCART
DSP
Input
Select

SCART1
ADC

Prescale

SCART4
MONO

Fig. 11: Simplified functional block diagram of the MSP 34x0G

Micronas

DAC

SCART
Output
Select
SCART2

PI5V330

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

Low ON Resistance Wideband/Video

Quad 2-Channel MUX/DEMUX

Product Features:
High-performance, low-cost solution to switch
between video sources
Wide bandwidth: 200 MHz
Low ON-resistance: 3
Low crosstalk at 10 MHz: 58 dB
Ultra-low quiescent power (0.1 A typical)
Single supply operation: +5.0V
Fast switching: 10 ns
High-current output: 100 mA
Packages available:
16-pin 300-mil wide plastic SOIC (S)
16-pin 150-mil wide plastic SOIC (W)
16-pin 150-mil wide plastic QSOP (Q)

Product Description:
Pericom Semiconductors PI5V series of mixed signal video
circuits are produced in the Companys advanced CMOS
low-power technology, achieving industry leading performance.
The PI5V330 is a true bidirectional Quad 2-channel
multiplexer/demultiplexer that is recommended for both
RGB and composite video switching applications. The
VideoSwitch can be driven from a current output
RAMDAC or voltage output composite video source.
Low ON-resistance and wide bandwidth make it ideal for
video and other applications. Also this device has exceptionally high current capability which is far greater than most
analog switches offered today. A single 5V supply is all that
is required for operation.
The PI5V330 offers a high-performance, low-cost solution
to switch between video sources. The application section
describes the PI5V330 replacing the HC4053 multiplier and
buffer/amplifier.

Functional Block Diagram

S1A
S2A

DA

16-Pin Product Configuration

S1B
S2B

DB
IN
S1A

S1C
S2C

DC

S2A
DA
S1B

S1D
S2D

S2B

DD

DB
GND

1
2
3
4
5
6
7
8

16
15
14
16-PIN 13
Q16
12
S16
11
W16
10
9

VCC
EN
S1D
S2D
DD
S1C
S2C
DC

DECODER/DRIVERS

Product Pin Description

EN

IN

Pin Name
S1A, S2A
S1B, S2B
S1C, S2C
S1D, S2D
IN
EN
DA, DB,
DC, DD
GND
VCC

Truth Table
EN
0
0
1

IN
0
1
X

ON Switch
S1A, S1B, S1C, S1D
S2A, S2B, S2C, S2D
Disabled

Description
Analog Video I/O

Select Input
Enable
Analog Video I/O
Ground
Power

PS7032C

08/07/97

Features
Low-Voltage and Standard-Voltage Operation

5.0 (VCC = 4.5V to 5.5V)

2.7 (VCC = 2.7V to 5.5V)
2.5 (VCC = 2.5V to 5.5V)
1.8 (VCC = 1.8V to 5.5V)
Low-Power Devices (ISB = 2=A @ 5.5V) Available
Internally Organized 4096 x 8, 8192 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate
Write Protect Pin for Hardware Data Protection
32-Byte Page Write Mode (Partial Page Writes Allowed)
Self-Timed Write Cycle (10 ms max)
High Reliability
Endurance: 1 Million Write Cycles
Data Retention: 100 Years
ESD Protection: >3,000V
Automotive Grade and Extended Temperature Devices Available
8-Pin JEDEC PDIP, 8-Pin JEDEC SOIC, 8-Pin EIAJ SOIC,
and 8-pin TSSOP Packages

2-Wire
Serial EEPROM
32K (4096 x 8)
64K (8192 x 8)

AT24C32
AT24C64

Description
The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The devices cascadable feature allows up to 8 devices to share a common 2wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C32/64 is
available in space saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC,
and 8-pin TSSOP (AT24C64) packages and is accessed via a 2-wire serial interface.
In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V),
2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

Pin Configurations
8-Pin TSSOP

Pin Name

Function

A0 - A2

Address Inputs

SDA

Serial Data

SCL

Serial Clock Input

WP

Write Protect

A0
A1
A2
GND

1
2
3
4

8
7
6
5

8
7
6
5

VCC
WP
SCL
SDA

2-Wire, 32K
Serial E2PROM

8-Pin SOIC

8-Pin PDIP
A0
A1
A2
GND

1
2
3
4

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

8
7
6
5

VCC
WP
SCL
SDA
Rev. 0336G04/01

Absolute Maximum Ratings*

Operating Temperature.................................. -55C to +125C
Storage Temperature ..................................... -65C to +150C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V

*NOTICE:

Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

DC Output Current........................................................ 5.0 mA

Block Diagram

Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1
and A0 pins are device address inputs that are hard wired
or left not connected for hardware compatibility with
AT24C16. When the pins are hardwired, as many as eight
32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail under the

AT24C32/64

Device Addressing section). When the pins are not hardwired, the default A2, A1, and A0 are zero.
WRITE PROTECT (WP): The write protect input, when tied
to GND, allows normal write operations. When WP is tied
high to V CC, all write operations to the upper quandrant
(8/16K bits) of memory are inhibited. If left unconnected,
WP is internally pulled down to GND.

Memory Organization
AT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is
internally organized as 256 pages of 32 bytes each. Random word addressing requires a 12/13 bit data word
address.

HT48R06A-1/HT48C06
8-Bit Cost-Effective I/O Type MCU
Features
Operating voltage:

HALT function and wake-up feature reduce power

fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V

consumption
Up to 0.5ms instruction cycle with 8MHz system clock

13 bidirectional I/O lines

at VDD=5V

An interrupt input shared with an I/O line

Allinstructionsinoneortwomachinecycles

8-bit programmable timer/event counter with over-

14-bit table read instruction

flow interrupt and 8-stage prescaler

Two-level subroutine nesting

On-chip crystal and RC oscillator

Bit manipulation instruction

Watchdog Timer

63 powerful instructions

102414 program memory ROM

Low voltage reset function

648 data memory RAM

16-pin SSOP package

Buzzer driving pair and PFD supported

18-pin DIP/SOP package

General Description
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem controllers, etc.

The HT48R06A-1/HT48C06 are 8-bit high performance, RISC architecture microcontroller devices specifically designed for cost-effective multiple I/O control
product applications. The mask version HT48C06 is
fully pin and functionally compatible with the OTP version HT48R06A-1 device.

Block Diagram
IN T /P C 0

In te rru p t
C ir c u it
S T A C K 0
P ro g ra m
R O M

P ro g ra m
C o u n te r

T M R

S T A C K 1

IN T C

P r e s c a le r

M P

U
X

D A T A
M e m o ry

W D T S
W D T P r e s c a le r

P B C

S T A T U S

fS

/4

X
R C O S C

P C 0 ~ P C 1

C 1

P O R T B

P B

S h ifte r

P A C

Rev. 1.30

B Z /B Z
A L U

O S
R E
V D
V S

W D T

P O R T C

P C

M U X

T im in g
G e n e ra to r

O S C 2

Y S

P C 1

P C C
In s tr u c tio n
D e c o d e r

Y S

T M R C

P C 0
In s tr u c tio n
R e g is te r

fS

T M R /P C 1
X

P A

A C C

P O R T A

P B 0 ~ P B 2

P A 0 ~ P A 7

August 7, 2003

HT48R06A-1/HT48C06
Pin Assignment

1 6

P A 4

P A 3

P A 3
1

1 8

P A 4

P A 2
2

1 7

P A 5

P A 2
2

1 5

P A 5

P A 1
3

1 6

P A 6

P A 1
3

1 4

P A 6

P A 0
4

1 5

P A 7

P A 0
4

1 3

P A 7

P B 2
5

1 4

O S C 2

P B 0 /B Z
5

1 2

O S C 2

P B 1 /B Z
6

1 3

O S C 1

V S S
6

1 1

O S C 1

P B 0 /B Z
7

1 2

V D D

P C 0 /IN T
7

1 0

V D D

V S S
8

1 1

R E S

P C 1 /T M R
8

R E S

P C 0 /IN T

1 0

P C 1 /T M R

H T 4 8 R 0 6 A -1 /H T 4 8 C 0 6
1 6 S S O P -A

H T 4 8 R 0 6 A -1 /H T 4 8 C 0 6
1 8 D IP -A /S O P -A

Pad Assignment
HT48C06
P A 1

P A 2

P A 3

P A 4

P A 5

P A 6

1 8

1 7

1 6

1 5

1 4

1 3

(0 ,0 )
1

P A 0

1 2

P B 2

P B 1 /B Z

1 1

O S C 2

1 0
O S C 1

V D D

V S S

R E S

P B 0 /B Z

P C 1 /T M R

P C 0 /IN T

P A 7

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.30

August 7, 2003

HT48R06A-1/HT48C06
Pad Description
Pad Name

PA0~PA7

I/O

I/O

Options

Description

Pull-high*
Wake-up

Bidirectional 8-bit input/output port. Each bit can be configured as wake-up

input by options. Software instructions determine the CMOS output or
Schmitt trigger input with a pull-high resistor (determined by pull-high options).
Bidirectional 3-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with a pull-high resistor (determined by
pull-high options).
The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once the
PB0 and PB1 are selected as buzzer driving outputs, the output signals come
from an internal PFD generator (shared with a timer/event counter).

PB0/BZ
PB1/BZ
PB2

I/O

Pull-high*
I/O or BZ/BZ

VSS

PC0/INT
PC1/TMR

Negative power supply, ground

Bidirectional I/O lines. Software instructions determine the CMOS output or
Schmitt trigger input with a pull-high resistor (determined by pull-high options). The external interrupt and timer input are pin-shared with the PC0 and
PC1, respectively. The external interrupt input is activated on a high to low
transition.

I/O

Pull-high*

RES

Schmitt trigger reset input. Active low

VDD

Positive power supply

OSC1
OSC2

I
O

Crystal
or RC

OSC1, OSC2 are connected to an RC network or Crystal (determined by options) for the internal system clock. In the case of RC operation, OSC2 is the
output terminal for 1/4 system clock.

* All pull-high resistors are controlled by an option bit.

Absolute Maximum Ratings

Supply Voltage ...........................VSS-0.3V to VSS+6.0V

Storage Temperature ............................-50C to 125C

Input Voltage..............................VSS-0.3V to VDD+0.3V

Operating Temperature...........................-40C to 85C

Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

Rev. 1.30

August 7, 2003

HT48R06A-1/HT48C06
D.C. Characteristics
Symbol

VDD

IDD1

Parameter

Operating Voltage

Ta=25C
Test Conditions
Conditions

VDD

5.5

fSYS=8MHz

3.3

5.5

0.6

1.5

mA

mA

0.8

1.5

mA

2.5

mA

mA

mA

10

mA

mA

mA

3V
Operating Current (RC OSC)

No load, fSYS=4MHz

No load, fSYS=4MHz

5V

ISTB1

Standby Current (WDT Enabled)

5V

No load, fSYS=8MHz

3V
No load, system HALT
5V

ISTB2

Unit

2.2

3V

Operating Current (Crystal OSC)

Max.

fSYS=4MHz

Operating Current (Crystal OSC)

IDD3

Typ.

5V
IDD2

Min.

3V
Standby Current (WDT Disabled)

No load, system HALT

5V

VIL1

Input Low Voltage for I/O Ports,

TMR and INT

0.3VDD

VIH1

Input High Voltage for I/O Ports,

TMR and INT

0.7VDD

VDD

VIL2

Input Low Voltage (RES)

0.4VDD

VIH2

Input High Voltage (RES)

0.9VDD

VDD

VLVR

Low Voltage Reset

LVR enabled

2.7

3.0

3.3

IOL

mA

I/O Port Sink Current

10

20

mA

-2

-4

mA

-5

-10

mA

3V

VOL=0.1VDD

5V
IOH

3V
I/O Port Source Current

VOH=0.9VDD

5V
RPH

Rev. 1.30

3V

40

60

80

kW

5V

10

30

50

kW

Pull-high Resistance

August 7, 2003

AKAI
MODEL : PDP42X2####
CAUTION
1. BEFORE SERVICING THE PDP MODULE,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
2. WHEN REPLACEMENT PARTS ARE REQUIRED, BE SURE TO USE
REPLACEMENT PARTS SPECIFIED BY THE MANUFACTURER..

English

PDP PANEL

AKAI

SPECIFICATION
FOR
APPROVAL

( ) Preliminary Specification
(
) Final Specification

Title
Customer

PDP42X2#### (42 PDP MODULE)

Supplier

LG Electronics Inc.

Model Name

Model Name

PDP42X2#000

Part No.

Part No.

Signature
Approved by

Reviewed by

NAKS

Date

Signature

Date

Approved by
G.S. Lim/G.Manager
Reviewed by
J.S. Lee

Reviewed by
Ted. Lee

Prepared by
J.H.Yeom

Agreed by
J.Y.Kim

Prepared by
/

PDP Engineering Department

PDP Division LG Electronics Inc.

Please return 1 copy with your signature and comments for our confirmation.

Confidential
Revision No. 00

10 /OCT / 2004

Page 0/40

AKAI
1. GENERAL DESCRIPTION
DESCRIPTION
The PDP42X2#### 42-inch 16:9 color plasma display module with resolution of 1024(H) 768(V) pixels.
This is the display device which offers vivid colors with adopting AC plasma technology by LG Electronics Inc.

FEARURES
High peak brightness (1000cd/m2 Typical) and high contrast ratio (5000:1 Typical) enables user to create
high performance PDP SETs.

APPLICATIONS
9 General television systems
9 Public information display
9 Video conference systems
9 Education and training systems

Confidential
Revision No. 00

10 /OCT / 2004

Page 7/40

AKAI

ELECTRICAL INTERFACE OF PLASMA DISPLAY

The PDP42X2#### requires 8bits or 10bits of digital video signals for each RGB color.
In addition to the video signals, six different DC voltages are required to operate the display.
The PDP42X2#### is equipped with P-CUBE function which analyzes display signals to optimize system
control factor for showing the best display performance.

GENERAL SPECFICATIONS
9 Model Name
9 Number of Pixels
9 Pixel Pitch
9 Cell Pitch
9 Display Area
9 Outline Dimension
9 Pixel Type
9 Number of Gradations
9 Weight
9 Aspect Ratio
9 Peak Brightness
9 Contrast Ratio
9 Power Consumption
9 Expected Life-time

: PDP42X2#### (42X2#### Model)

: 1024(H) 768(V) (1pixel=3 RGB cells)
: 900 (H) 676 (V)
: 300 (H) 676 (V) (Green Cell basis)
: 920.1(H) 518.4(V) 0.5mm
: 1005(H) 597(V) 61.2(D)1mm
: RGB Closed type
: (R)1024 (G)1024 (B)1024
: 16.1 Kg 0.5 Kg (Net 1EA)
109 Kg 5 Kg (5EA/1BOX)
: 16:9
: Typical 1000cd/ (1/100 White Window)
: Average 60:1 (In a bright room with 150Lux at center)
: Typical 5000:1 (In a dark room 1/100 White Window pattern at center)
: Typical 300 W (Full White), Max.330W
: more than 60,000 Hours of continuous operation

Life-time is defined as the time when the brightness level becomes half of its initial value.

9 Display Dot Diagram

1st
pixel
column

2nd
pixel
column

Pixel Pitch(width)
0..900
1st pixel
row
2nd pixel
row

cell

R:0.28
G:0.30
B:0.32

1023th 1024th
pixel
pixel
column column
Cell Width

R G B R G B

R G B R G B

R G B R G B

R G B R G B

767th pixel
row

R G B R G B

R G B R G B

768th pixel
row

R G B R G B

R G B R G B

3rd pixel
row

pitch(height)

R G B R G B

0.676

R G B R G B

pixel

Confidential
Revision No. 00

10 /OCT / 2004

Page 8/40

English

. Formation and Specification of Module

External Cable Connection

NO

Connector

Input Voltage & Signal

P151[Z SUS B/D]

5V, Va, Vs

P151[Y SUS B/D]

5V, Va, Vs

P300[CTRL B/D]

5V

P201[CTRL B/D]

Video Signal

NO

Part No.

6871QCH038A

PWB(PCB) ASSY

LVDS CTRL B/D ASSY

6871QDH068A

PWB(PCB) ASSY

Y DRV UPPER B/D ASSY

6871QDH069A

PWB(PCB) ASSY

Y DRV LOWER B/D ASSY

6871QYH030A

PWB(PCB) ASSY

Y SUS B/D ASSY

6871QZH034A

PWB(PCB) ASSY

Z SUS B/D ASSY

6871QLH037A

PWB(PCB) ASSY

X LEFT B/D ASSY

6871QRH043A

PWB(PCB) ASSY

X RIGHT B/D ASSY

Description

- 5 -

. Block Diagram

English

Input Signal: Full White

Current(typ.): rms

- 19 -

. Trouble Shooting
1. Checking for no Picture
A screen doesnt display at all and condition of black pattern or power off.

English

(1) Check whether the CTRL B/D LED(D1, D14) is turned on or not.
(2) Check the power and signal cable of CTRL B/D.
(3) X B/D, Y B/D, Z B/D is well plugged in.
(4) Check the connection of X B/D, Y B/D and Z B/D to CTRL B/D.
(5) Measure the output wave of X, Y, Z B/D with oscilloscope(more than 200MHz)
and find the trouble of B/D by comparing the output wave with below figure.
- Measure Point fo Y B/D : TP(Bead B1)
- Measure Point fo Z B/D : TP(Bead B1)
(6) Check the SCAN(Y side) IC
(7) Check the DATA(X side) TCP IC
(8) Replace the CTRL B/D.

<A: Y B/D Output wave - 1 FRAME>

<B: Y B/D Output wave - 1 SF>

<A: Y B/D Output wave - 1 FRAME>

<B: Y B/D Output wave - 2, 3, 4 SF>

- 9 -

<A: Y B/D Output wave - 1Frame>

<B: Y B/D Output wave - 5~10 SF>

<A: Z B/D Output wave - 1Frame>

<B: Z B/D Output wave - 1~10 SF>

<X B/D Output wave - 1 FRAME>

<X B/D Output wave - 1 SF>

<X B/D Output wave - Enlargement>

- 10 -

2. Hitch Diagnosis Following

Display Condition
2-2. The screen doesnt be shown as Data
TCP

2-1. 1/2 of the screen is not turned on

(Include not be shown part of Data COF quantity or a part)

(1) Confirm the power connection of X B/D is well plugged in
which is correspond to not showing screen.
(2) Confirm the power connector that is connected between
CTRL B/D and X B/D correspond to not showing part.
(3) Replace relevant X B/D. When replace X B/D, TCP should
have been connected accurately, it confirms certainly.

[ Relationship between screen and X B/D

Screen
X B/D
Left of the Screen 1/2 <--> Right X B/D
Right of the Screen 1/2 <--> Left X B/D

[ Example of the screen display form

(Anything of the 16 Data TCP can be shown beside below
pictures)

[ Screen Display Form

: All
: Partial
: not at all
Left of the Screen(1/2)

Right of the Screen(1/2)

Display
Not display

[ 1/4 of the screen doesnt be shown

Equality with 2-1

- 11 -

English

(1) Replace the cable between the CTRL B/D and X B/D,
when there is not change, replace the CTRL B/D.
(2) Check the Data TCP of point screen does not come out is
fail and when it is not problem, connect again with
correspondence TCP.
(3) In case of fail the correspondence Data TCP, replace the
Module.

2-3. It Generates Unusual Pattern of Data

TCP IC unit

2-4. The screen display has a problem for

Scan FPC.

(1) In case of line shape or dotted line occurs, check the screw
on X B/D and make sure it is tight. When the there is not
change, replace the X B/D.
(2) In case of <case 1>
- confirm the connection of Data TCP connector
- Replace relevant XB/D or CTRL B/D
(3) In case of <case 2, 3>
- confirm the connector that is connected from CTRL B/D to
relevant X B/D
- Replace relevant XB/D or CTRL B/D

(1) It may be a problem between Scan FPC and Y DRVB/D.

(2) Check the connection of Y DRV B/D and Scan FPC.
(3) If the Scan IC is failed, replace the Y DRV B/D.
(Check the compatibility)

[ Screen Display Form

1/12
of screen

[ Screen Display Form

The screen display is very good

<Case 1>

Unusual screen comes

out about one IC quantity
in one COF

<Case 2>

Unusual screen comes out

as a unit of Data COF IC
through one X B/D

<Case 3>

The screen display is poor

[ Check a method of SCAN IC

Unusual screen comes out

as a unit of Data COF IC
through Top or Bottom
screen

Change the Vpp Pin into ANODE and GND Pin into CATHOD
and then test the Diode with forward or reverse direction.

- 12 -

2-5. The screen has a vertical line with

regular gap.
(A vertical stripe flash at especial color)

2-7. The screen has one or several vertical

line
(1) In this case, It isnt a problem about controller B/D or X
B/D.
(2) It may cause followings.
- Its out of order a panel
- Open or short of DATA TCP FPC attached panel
- DATA TCP attached on panel is out of order

(1) This problem comes from Control B/D.

(2) Replace Control B/D.

[ Screen Display Form

(3) Replace Module.

It may show several vertical

lines in a quarter or other
division part of screen
including left case.
The screen has a vertical line
with regular gap

2- 8. The screen has one or several

horizontal line

2-6. A data copy is happened into vertical

direction

(1) In this case, it isnt a problem about controller B/D or X

B/D.
(2) It may cause followings.
- Its out of order a panel
- Open or short of SCAN FPC attached panel
- SCAN FPC attached on panel is out of order.

(1) In this case, its due to incorrect marking of scan wave.

(2) Replace a Y DRV B/D or Y SUS B/D.

[ Screen Display Form

(3) Replace Module.

<Display Pattern>

<Case 1 : Entire Copy>

[ Screen Display Form

<Case 2 : Top Copy> <Case 3 : Bottom Copy> <Case 4 : Entire Copy>

- 13 -

It may be shown on several

horizontal lines including
left case.

English

[ Screen Display Form

Vsetup = 801V @42X2##2# Module

3-2. FET Assy(Y B/D: HS11, 51, 91) damage

(1) When Set_Up FET is damaged, screen doesnt be shown
O Test Point: Enlarge the after measuring GND~B1(Y B/D)
O Waveform state: As shown (Fig. 2)

Set Up waveform
does not come out

(Fig. 2) When the Set_Up FET is damaged

(2) When Set_Down FET/Pass_Top FET is damaged, mis
discharge of entire screen is generated.
O Test Point: Enlarge the after measuring GND~B1(Y B/D)
O Waveform state: As shown (Fig. 3)

Set Down waveform

does not come out
(Fig. 3) When the Set_Down FET is damaged

(3) When Ramp FET is damaged

O Test Point: Enlarge the after measuring GND~B1(Y B/D)
O Waveform state: As shown (Fig. 4)

(Fig. 4) When the Ramp FET is damaged

- 15 -

Measurement position: Reset section enlargement wave

of TP B1(Y B/D) (Full White Pattern)

English

<FET Assy Normal Output Waveform >

Vsc = 120V @ 42X2##2# Moduel

3-5. Crystal(CTRL B/D: X2) damage

(1) In case of shorting or opening of IC output of TCP several

vertical lines occured.
O Test Point: Enlarge the after measuring output TP of
GND~TCP.
O Waveform state: As shown Output of (Fig. 8)
In case of normal wave output, when STB signal is
applied, STB signal remains High. And when STB signal
is applied again, it must be fall Low.
But when TCP IC is bad, even STB signal is not
generated, Output falls to Low.

(1) When Crystal is damaged, the screen doesnt be turned

on.
O Test Point: Measuring 3pin of GND~Crystal(Ctrl B/D: X2)
O Waveform state: Output wave doesnt come out

(2) In case of unusual launch of the Crystal, it may blink the

screen.
O Waveform state: As shown (Fig. 9)

Output voltage of the signal is dropped

(Fig. 8) When IC output of TCP is poor

[ Since the output TP of TCP is covered with SR, when
measurement is needed, remove the SR, measures. And
after measuring insulates TCP leads with insulation tape.

(Fig. 9) When Crystal is bad

(2) In case of being damaged on TCP IC, the screen doesnt

be shown or happens discharge partially. When IC fail
occurs, it will be able to discover the trace which is burned.
O Test Point: Enlarge the after measuring output TP of
GND~TCP
O Waveform state: Output wave doesnt come out

<Crystal Normal Output Waveform >

<TCP Normal Output Wave >

O

Measurement position: Enlarge the after measuring

output TP of TCP (Full White Pattern)

- 17 -

Measurement position: Measuring output 3pin of

Crystal(X2: 100MHz) on Ctrl B/D (Full White Pattern)

English

3-4. TCP damage

Use B/D applicated SN755870

TOP:6871QDH090B
BTM:6871QDH091B

Digital PDP Division, LG Electronics Inc.

NO : P04#C-###

Product Specification of PDP Module

6. OUTLINE DRAWING
Front View

Confidential
Revision No. 00

10 /OCT / 2004

Page 33/40

 Rear View

Confidential
Revision No. 00

10 /OCT / 2004

Page 34/40

. Records of Revision for Boards,components and ROM DATA

1. Boards
No.

Date

Board

Part Number

Note

2004.06.17 CTRL B/D ASSY(LVDS)

6871QCH038A

Initial Product

2004.06.17 YDRV UPPER B/D ASSY

6871QDH068A

Initial Product

2004.06.17 YDRV LOWER B/D ASSY

6871QDH069A

Initial Product

2004.06.17 Y SUS B/D ASSY

6871QYH030A

Initial Product

2004.06.17 Z B/D ASSY

6871QZH034A

Initial Product

2004.06.17 X RIGHT B/D ASSY

6871QRH043A

Initial Product

2004.06.17 X LEFT B/D ASSY

6871QGH037A

Initial Product

2004.12.05 YDRV UPPER B/D ASSY

6871QDH068B

To improve the Scan

Noise

2004.12.05 Y SUS B/D ASSY

6871QYH030C

To improve the EMI

10

2004.12.05 Z B/D ASSY

6871QZH034C

To improve the EMI

11

2005.01.18 CTRL B/D ASSY(LVDS)

6871QCH060B

PDP42X2##2#
42X2A initial Product

12

2005.03.07 YDRV UPPER B/D ASSY

6871QDH090B

PDP42X2##2#
42X2A initial Product

13

2005.03.07 YDRV LOWER B/D ASSY

6871QDH091B

PDP42X2##2#
42X2A initial Product

14

2005.03.07 Y SUS B/D ASSY

6871QYH042B

PDP42X2##2#
42X2A initial Product

15

2005.03.07 Z B/D ASSY

6871QZH047B

PDP42X2##2#
42X2A initial Product

16

2005.05.25 Y SUS B/D ASSY

6871QYH042C

PDP42X2##4#
For gap+pad apply Model

17

2005.05.25 Z B/D ASSY

6871QZH047C

PDP42X2##4#
For gap+pad apply Model

18

2005.06.22 CTRL B/D ASSY(LVDS Out)

6871QZH071C

PDP42X2##3#
For Ctrl LVDS out Model

- 20 -

2. Component
No.

Date

Component

Part Number

Note

2004.06.17 Y IPM (IC81)

4921QP1027A

Initial Product

2004.06.17 Z IPM (IC81)

4921QP1028A

Initial Product

2004.06.17 Y Path FET Assy(HS91)

4921QF3002A

Initial Product

2004.06.17 Scan IC

0ILNRTI020A

Initial Product

2004.06.17 Crystal

0ILNRDI001A

Initial Product

2004.06.17 TCP

6007QD0007A

Initial Product

2005.05.17 Y Path FET Assy(HS91)

4921QF3005A

Apply to 42X2A
Model

2005.05.17 Y Setdn Fet Assy(HS11)

4921QF1009B

Apply to 42X2A
Model

2005.05.17 Y Vsetup Fet Assy(HS51)

4921QF2002B

Apply to 42X2A
Model

10

2005.06.22 Y IPM (IC81)

4921QP1027P

For Pb_free

11

2005.06.22 Z IPM (IC81)

4921QP1028P

For Pb_free

12

2005.06.22 TCP_13Pf(NEC160300)

6007QD0018B

Apply to 42X2A
Model

13

2005.06.22 Scan IC(SN755870)

0ILNRTI020B

Apply to 42X2A
Model

- 22 -

3. ROM DATA
No.

Date

ROM data Version

Contents

2004.06.30

42X2DN01

initial ROM Data

(42X2####. 42X2)

2004.07.07

42X2DN01A

2004.07.23

42X2DN02

2004.07.28

42X2DN02A

2004.08.10

42X2DN02B

2004.08.10

42X2DN03

2004.09.08

42X2DN03A

2004.09.08

42X2DN03B

2004.10.04

42X2DN03C

10

2004.10.04

42X2DN03D

11

2004.11.18

42X2DN03E

12

2004.12.01

42X2DN03G

13

2004.12.27

42X2DN03L

14

2004.12.27

42X2DN03M

15

2004.12.31

42X2DN03P

Temporary ROM to improve

the afterglow in Peak P/T
(42X2####, 42X2)
ROM to improve
the EMI,contournoise(42X2####, 42X2)
Temporary ROM to improve high&low
Temp. miswriting(42X2####, 42X2)
Temporary ROM to improve
miswriting(for July)(42X2####, 42X2)
ROM to improve the Flicker, afterglow
and miswriting (42X2####, 42X2)
ROM to improve high temp.
miswriting(after august)
(42X2####, 42X2)
ROM to improve miswriting
(after august)(42X2####, 42X2)
ROM to improve miswriting & afterglow
(after august)(42X2####, 42X2)
ROM to improve white_blinking
(after august) (42X2####, 42X2)
Temporary ROM to improve R-miswriting
(for october,november)
(42X2####, 42X2)
ROM to improve R_margin(for november)
(42X2####, 42X2)
Temporary ROM to improve
white_blinking-afterglow
(42X2####, 42X2)
Temporary ROM to improve
white_blinking-afterglow
(42X2####, 42X2)
Rom to improve contrast_ratio (to
january for defect_module)
(42X2####, 42X2)
- 23 -

B_Dielec. : Blue dielectric Substance

T_Dielec : Transparency dielectric Substance

No.

Date

ROM data Version

16

2005.01.05

42X2_DN03N

17

2005.01.24

42X2_DN03R

18

2005.02.22

42X2DN03T

19

2005.03.02

42X2DN04A

20

2005.03.16

42X2A_DNA03

21

2005.04.28

42X2DN04B

22

2005.04.28

42X2A_DNA06

23

2005.04.27

42X2A_DNA06A

24

2005.05.11

42X2A_TD02B

25

2005.05.28

42X2A_TD02C

26

2005.07.01

42X2A_DNA7A

27

2005.07.14

42X2A_TD03

28

2005.07.28

42X2A_TD03A

29

2005.07.29

42X2DN05B

Contents
ROM to improve high temp.
miswriting(to january for defect
module)(42X2####, 42X2)
ROM to improve Data_Noise & Peaking
(42X2####, 42X2)
Temporary ROM to improve
white_blinking( for february & march)
(42X2####. 42X2)
ROM to improve afterglow &
white_blinking (42X2####, 42X2)
42X2A initial ROM DATA
(42X2##2#,42X2A B_Dielec.)
Temporary ROM to improve
white_blinking(April,May)
(42X2####, 42X2)
Temporary ROM to improve high temp.
miswriting (April)
(42X2##22, 42X2A B_Dielec)
ROM to improve 50 Peak Brightness
(42X2##22, 42X2A B_Dielec)
42X2A Initial ROM for T_Dielec
(42X2#522, 42X2A T_Dielec)
ROM to improve Low Temp.
Miswriting&White_Blinking
(42X2#522, 42X2A T_Dielec)
ROM to improve afterglow-whiteblinking
(42X2##22, 42X2A B_Dilect)
ROM to improve afterglow-whiteblinking
(42X2#522, 42X2A T_Dielec)
ROM to improve High Temp. miswriting
(42X2#522, 42X2A T_Dielec)
ROM to improve afterglow-whiteblinking
(42X2####, 42X2)
- 24-

PD42HAASUSXS1-A01
Item Component

AKAI R&D SA PDP4216M

Description/Country Origin

Unit

Quantity

, ELECT PART
1 771-42AB01-01
2 771-42AB01-05
3 771-42D110-01
4 771E42AA02-01
5 771L42AA01-01
6 774P42AB01-01
7 77M42D103-02
8 786-SPA103-01
9 E3403-004001
10 E3421-926007
11 E3421-926045
12 E3421-926046
13 E6205-001004
, MECH PART
1 200-42D121-25A
2 244-34B811-01
3 248-46D201-01
4 263-42D101-01S
5 269-42D101-01L
6 329-053010-70
7 329-095510-70
8 361-101261-01
9 384-42D103-08H
10 387-42D101-13H
11 388-42D102-01
12 388-42D103-01H
13 388-42SB04-01H
14 388-50AD01-01H
15 402-42D114-01S
16 423-42D117-01S
17 423-42D11C-01S
18 423-42D11E-01S
19 423-42D122-01S
20 423-42D12D-01S
21 423-42SD12-01S
22 423-42SD21-01S
23 457-42D101-01
24 553-002007-40A
25 553-002509-25A

KEY PCB ASSY

SPK JACK PCB ASSY
IR RECEIVE PCB ASSY
MAIN PCB ASSY
AUDIO PCB ASSY
POWER ASSY
MECH CHASSIS ASSY
INT. SPK ASSY
TUBE SUMITUBE D5.0 BLK 600V
WIRE ASSY 1H2.5-2H2.5 L330 31P (LV
WIRE ASSY 6P/4P+2P 2.54MM L=200MM
WIRE ASSY 2.54MM 11P/12P+7P L=220MM
DISPLAY PDP 42" LG-42X2 (XGA) 107CM

SET
SET
SET
SET
SET
SET
SET
SET
M
PCS
PCS
PCS
PCS

1
1
1
1
1
1
1
1
0.35
1
1
1
1.00006

CABINET FRONT BLACK AKAI PD42HAA USA

GIFT BOX HANDLE
34B8
HANDLE FOR PLASMA
POWER LENS
42D1
REMOTE LENS
42D1
SPONGE 530X10X7.0MM W/ADHESIVE
SPONGE 955X10X7.0MM W/ADHESIVE
CABLE TIE
PVC SHEET FOR AKAI PCB PD42HAA USA
MODEL PLATE AKAI ENG PD42HAA USA H
PC SHEET FOR REMOTE PCB42D1 94V0 0.3
CAUTION PLATE ENG 42D1
H
POWER PLATE SANSUI 42SB
SPEAKER PLATE FOR PDP50HAD
BACK COVER W/O SWITCH HOLE S
PANEL PATCH V6
42D1
SUPPORT FOR PW BKT 42D1
S
POWER BKT FOR E-ROOM 42D1 S
FILTER SUPPORT L&R 42D1
MAIN BKT FOR HOME CHASSIS 42D1 S
FILTER SUPPORT TOP 42SD
FILTER SUPPORT BOTTOM 42SD
CLAMP ID=4.3MM L=46MM
SHIELD GASKET 20X7X4.0MM W/CONDUCTIV
SHIELD GASKET 25X9X2.5MM W/CONDUCTIV

PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS

1
2
2
1
1
2
2
24
1
1
1
1
1
1
1
4
1
1
2
2
1
1
7
4
2

26 553-004009-40A
27 553-005009-25A
28 553-012509-40A
29 553-020009-40A
30 553-024509-40A
31 553-056009-40A
32 553-095009-40A
33 554-080030-01
34 563-11935 568-P46T02-02
36 579-42D102-09
37 579-42D102-16
38 579-42D103-02
39 579-42D105-01
40 580-P42AAHS-MU01L
41 590-42D101-07
42 593-42D101-01
43 599-BM0902-01
44 601-305008-00
45 602-305006-00
46 602-305006-10
47 604-601020-00
48 60D-407010-40
49 610-300210-00
50 614-260208-10
51 614-400408-10
52 614-400412-00
53 615-400214-00
54 619-300210-10
55 634-100050-20
56 734-BM0903-01
57 790-002517-A1
58 844-42D101-01
59 844-42D102-01
60 900-420103-01B
, PACKING
1 300-42D105-02C
2 300-42D106-02C
3 300-42D107-01C
4 300-42D118-01C
5 310-111404-07V
6 310-504004-01
7 510-42D101-20K
8 511-42D111-01K
9 512-42D101-01

SHIELD GASKET 40X9X4.0MM W/CONDUCTIV

SHIELD GASKET 50X9X2.5MM W/CONDUCTIV
SHIELD GASKET 125X9X4.0MM W/CONDUCTI
SHIELD GASKET 200X9X4.0MM W/CONDUCTI
SHIELD GASKET 245X9X4.0MM W/CONDUCTI
SHIELD GASKET 560X9X4.0 W/CONDUCTIVE
SHIELD GASKET 950X9X4.0 W/CONDUCTIVE
SHIELD CLOTH 80X30MM W/CONDUCTIVE AD
SERIAL NO. LABEL
WARNING LB ENG
42SF NIL
SERIAL NO/BAR CODE LABEL 42D1
BAR CODE LABEL AKAI PD42HAA USA
ON/OFF LB ENG
42D1 NIL
PROTECTIVE EARTH LABEL FOR ESA 42TD1
IB E FOR AKAI PD42HAA MONITOR LGX2A
WARRANTY CARD AKAI PD42HAA USA
INSERTION CARD AKAI PDP4216M MONITOR
IB SHEET E OF TEARDOWN FOR BM09 42AA
MACH.SCREW CTS 3X8
BZN +
MACH. SCREW PAN-WASHER 3X6 B ZNP +H
MACH.SCREW WHR 3X6
NIP +
MACHINE SCREW BINDING M6X1.0PX20MM B
MACH. SCREW W/SPRING WASHER M4.0X0.7
S-TAP.SCREW RND 3X10
A BZN +
S-TAP.SCREW BID 2.6X8
A NIP +
S-TAP.SCREW BID 4X8
D NIP +
S-TAP.SCREW BID 4X12
T BZN +
SELF-TAPPING SCREW W/BIG WASHER
SPECIAL SCREW 3X10 NP "+"
PLANE WASHER 10X5.0X2.0MM
STAND BM09
REMOTE CONTROL 0025
WOODEN PALLET 1160X940X104
WOODEN PALLET 1160X1250X104
DISPLAY FILTER 42" OPTIMAX FOR LG (9

PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS

1
1
11
4
2
2
2
1
1
1
1
2
1
1
1
1
1
1
2
16
11
6
21
2
2
2
34
1
23
4
1
1
0.1428
0.1428
1

POLYFAM FOR MAIN UNIT+BM09 BTM

POLYFOAM FOR MAIN UNIT+BM09 TOP
POLYFOAM SHEET 42D1
POLYFOAM LEFT 42TD1
POLYBAG
11"X14"X0.04
POLYBAG EPF 50"X40"X0.04
GIFT BOX AKAI ENG PD42HAA USA K
BOTTOM BOX 42D1
SHEET 1160X1160
42D1

PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS

1
1
2
1
1
1
1
1
0.2857

10
11
12

512-42D102-01
E3404-157004
E7301-011002

SHEET 1160X1480
42D1
AC CORD UL 1.88M (YY-3/ST3 YUNBIAO)
BATTERY AA R6P1.5V <2>

PCS
PCS
PCS

0.2857
1
2

If you forget your V-Chip Password

- Omnipotence V-Chip Password: 5898.
- Press MENU button.
- Press Up, Down and CH+, CH-buttons to highlight "V-Chip" Control.
- Press OK button to pop up "INPUT PASSWORD".
- Use the Number buttons (0~9) to enter the omnipotence Password 1234.
- Press Down to highlight "Password change" Control.
- Press OK button to confirm and will pop up "Password Change" item.
- Change to your familiar Password again.

Software upgrade
- Connect the RS-232C input jack to an external control device (such as a computer) and software upgrade.

Type of connector; D-Sub 9-pin male

No.
1
2
3
4
5
6
7
8
9

Pin name
No connection
RXD (Receive data)
TXD (Transmit data)
DTR (DTE side ready)
GND
DSR (DCE side ready)
RTS (Ready to send)
CTS (Clear to send)
No Connection

9
6

RS-232C configurations
3-wire configuration
(Not standard)

7-wire configuration
(Standard RS-232C cable)

RXD
TXD
GND
DTR
DSR
RTS
CTS

PC

PDP

2
3
5
4
6
7
8

3
2
5
6
4
8
7

D-Sub 9

D-Sub 9

TXD
RXD
GND
DSR
DTR
CTS
RTS

RXD
TXD
GND
DTR
DSR
RTS
CTS

PC

PDP

2
3
5
4
6
7
8

3
2
5
4
6
7
8

D-Sub 9

D-Sub 9

TXD
RXD
GND
DTR
DSR
RTS
CTS

Software upgrade Process

- Power Switch OFF.
- Connect the serial port of the control device to the RS-232 jack on the PDP back panel.
RS-232C connection cables are not supplied with the PDP.
- Power Switch ON. The power indicator on the front of the panel should now display red, means
that the PDP is in standby mode.
- Copy the software (Flash Upgrader) to the computer.
- Open the software (Flash Upgrader.exe)
- Point "Flash" on the interface of the Flash Upgrader.exe.
- Press STANDBY button on the front panel or POWER button of Remote control, Power indicator
green, the PDP is in power ON mode, software start upgrader immediately.
- Waiting for the upgrader programing, when it is finished, the PDP will auto power on.
- After the upgrader is finished, shut down the power switch, take out the RS-232C connection
after the power indicator is extinguished.
Note: The computer and PDP must be keep Power ON in the software upgrade processing.