LAB MANUAL

ANALOG AND DIGITAL CIRCUITS LABORATORY

III SEMESTER- II YEAR- ECE

REGULATION: 2013
SUBJECT CODE: EC6311

EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY

LIST OF ANALOG EXPERIMENTS:
1. Frequency Response of CE / CB / CC amplifier

2. Frequency response of CS Amplifiers

3. Darlington Amplifier
4. Differential Amplifiers- Transfer characteristic.
5. CMRR Measurment
6. Cascode / Cascade amplifier
7. Determination of bandwidth of single stage and multistage amplifiers
8. Spice Simulation of Common Emitter and Common Source amplifiers
LIST OF DIGITAL EXPERIMENTS
9. Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa
(ii) Binary to gray and vice-versa
10. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483
11. Design and implementation of Multiplexer and De-multiplexer using logic gates
12. Design and implementation of encoder and decoder using logic gates
13. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
14. Design and implementation of 3-bit synchronous up/down counter
15. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops

INDEX
S.NO

DATE

NAME OF THE EXPERIMENT

SIGNATURE

DATE:
EX.NO:
STUDY OF BASIC GATES
AIM:
To study the functions of the basic logic gates.

COMPONENTS REQUIRED:
S.N
O

APPARATUS

QUANTITY

1
2
3
4
5

Digital Trainer kit

IC 7432, IC 7408, IC 7400, IC 7402, IC7404 , IC 7486
IC 7411, IC 7410
Patch cords
Connecting wires

1
1 each
1 each
As Required
As Required

THEORY:
The basic elements that make up a digital system are Logic Gates. The most common
gates are AND, OR, NOT, NAND, NOR, EX-OR and EX-NOR gates. The NAND and NOR
gates are called as the universal gates because all the other gates can be implemented using these
two gates. A simple logic element whose binary output is a Boolean function (AND, OR...) of the
input is known as a GATE.
AND GATE:
In AND gate, the output Y is the product of the two inputs A and B. Hence, even
if one input is zero, the output becomes zero. If both the inputs are equal to one then the
output is also one.
Y=A B
OR GATE:
In OR gate, the output Y is the sum of the two inputs A and B.Hence, even if any
one of the input is one or both the input is one the output becomes one. The output
becomes zero only when both the inputs are zero.
Y = A+B
NOT GATE:
In NOT gate, the output Y is the complement of the input A. Hence, the output is
one when the input is zero and vice versa.
Y = A'
NAND GATE:
In NAND gate, the output Y is the complement of the product of two inputs A and
B. Hence, the output is one if any one of the input is zero. The output is zero if both the
inputs are one.
Y = (A B)'
NOR GATE:
In NOR gate, the output Y is the complement of the sum of two inputs A and B.
Hence, if any one of the input is one, the output is zero and if both inputs are zero, the
output is one.
Y = (A+B)'
EXCLUSIVE OR GATE:

In EX-OR gate, the output Y is zero when both the inputs A and B are same (Both
are zero or both are one) otherwise the output is one.
Y=A B
EXCLUSIVE NOR GATE:
In EX-NOR gate, the output Y is one when both the inputs A and B are same
(Both are zero or both are one) otherwise the output is zero.
Y = (A B)'
PROCEDURE:
1. Make connections as per the logic diagram.
2. Give inputs as per truth table. For logic 1, connect the input pin to +5V and for logic zero
connect the input pin to Ground.
3. Verify the corresponding outputs for the given inputs, using the truth table of AND gate.
4. Verify the truth tables for all the other gates.
AND GATE:
SYMBOL:

OR GATE:

PIN DIAGRAM:

NOT GATE:
SYMBOL:

X-OR GATE:

PIN DIAGRAM:

SYMBOL:

NAND GATE:
SYMBOL:

NOR GATE:

PIN DIAGRAM:

PIN DIAGRAM:

3-INPUT AND GATE:

3-INPUT NAND GATE:

RESULT:

DATE:

EX.NO:
DESIGN AND IMPLEMENTATION OF CODE CONVERTERS USING
LOGIC GATES
AIM:
To design and implement the following code converters using logic gates.
a. BINARY code to GRAY code and vice versa.
b. BCD to EXCESS-3 code and vice versa.
COMPONENTS REQUIRED:
S.N
O
1
2
3
4

APPARATUS
Digital Trainer kit
IC 7432, IC 7408, IC 7404 , IC 7486
Patch cords
Connecting wires

QUANTITY
1
1 each
As Required
As Required

THEORY:
BINARY CODE:
Any discrete element of information distinct among a group of quantities can be
represented with a binary code. The code must be in binary because computers can hold only 0s
and 1s. Binary codes merely change the symbol and not the meaning of the elements of
information that they represent. An n-bit binary code is a group of n bits that assumed up to 2 n
distinct combinations of 0s and 1s with each representing one element of the set that is being
coded. In general, a set of 2n elements can be coded with n bits. The bit combination of n-bit
code is determined from the count in binary form 0 to 2n-1.
GRAY CODE:
It is convenient to use gray code to represent the digital data when it is converted from
analog data. The advantage of the Gray code over the straight binary number sequence is that
only one bit in the code group changes when going from one number to the next. The gray code
is used in applications where the normal sequence of binary numbers may produce error or
ambiguity during the transition from one number to the next. A typical application occurs when
the analog data are represented by continuous change in the shaft position.
BCD CODE:
It is possible to perform arithmetic operations directly with decimal numbers when they
are stored in the computer in a coded form. Different binary codes can be obtained by arranging
four bits in 10 distinct combinations. The code most commonly used for the decimal digits is the
straight binary assignment. This is called Binary coded decimal (BCD). It is a weighted code.

EXCESS-3 CODE:
The excess-3 code has been used in some older computers because of its selfcomplementing property. Such codes have the property that the 9s complement of a decimal
number is obtained directly by changing 1s to 0s and 0s to 1s in the code. This is an unweighted code where each coded combination is obtained from the corresponding binary value
added with 3.
PROCEDURE:
1.

Give connections as per the logic diagram.

2. Give inputs as per truth table. For logic 1, connect the input pin to +5V and for logic zero; connect
the input pin to Ground.
3. Verify the corresponding truth table.

GRAY CODE TO BINARY CONVERTOR

TRUTH TABLE:
|
Gray Code

Binary Code

G3

G2

G1

G0

B3

B2

B1

B0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0

0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0

0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

K-Map for B3:

B3 = G3
K-Map for B2:

B2= G3G2+G3G2,
K-Map for B1:

K-Map for B0:

LOGIC DIAGRAM:

BINARY TO GRAY CODE CONVERTER

TRUTH TABLE:
|
Binary input
B3
B2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

|
B1

B0

G3

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

K-Map for G3:

G3 = B 3
K-Map for G2:

G2=B3B2+B3B2,
K-Map for G1:

Gray code output

G2
G1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0

0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0

|
G0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

G1=B2B1+B2B1,
K-Map for G0:

G0=B1B0+B1B0,

LOGIC DIAGRAM:

EXCESS-3 TO BCD CONVERTER:

TRUTH TABLE:
|

Excess 3 Input
X1
X2
0
0
0
0
0
1
1
1
1
1

0
1
1
1
1
0
0
0
0
1

|
X3

X4

1
0
0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0
1
0

0
0
0
0
0
0
0
0
1
1

BCD Output
B
C
0
0
0
0
1
1
1
1
0
0

K-Map for A:

A = X1 X2 + X3 X4 X1=X1(X2+X3X4)
K-Map for B:

B=X2X3X4+X2X3+X2X4=X2X3X4+X2(X3+X4)
=X2(X3+X4) +X2(X3+X4) =(X2 X3X4)

0
0
1
1
0
0
1
1
0
0

|
D
0
1
0
1
0
1
0
1
0
1

K-Map for C:

C=X3X4+X3X4,
K-Map for D:

LOGIC DIAGRAM:

BCD TO EXCESS-3 CONVERTOR

TRUTH TABLE:
|
BCD input
|
B3
B2
B1
B0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1

E3
0
0
0
0
0
1
1
1
1
1
x
x
x
x
x
x

Excess 3 output
E2
E1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
x
x
x
x
x
x
x
x
x
x
x
x

|
E0
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x

K-Map for E3:

E3 = B3+B2B0+B2B1=B3 + B2 (B0 + B1)

K-Map for E2:

E2= B2B1B0+B2B0+B2B1 =B2(B1+B0)+B2(B1+B0) =B2 (B1+B0)

K-Map for E1:

E1=B1B0+B1B0=
K-Map for E0:

LOGIC DIAGRAM:

RESULT:

DATE:
EX.NO:
DESIGN AND IMPLEMENTATION OF 4-BIT BINARY ADDER/SUBTRATOR USING
MSI DEVICES(IC 7483)
AIM:
To design and implement 4-bit binary Adder/Subtractor using IC7483.
COMPONENTS REQUIRED:
S.N
O
1
2
3
4
5

APPARATUS
Digital Trainer kit
IC 7483
IC 7486, IC 7432, IC 7408
Patch cords
Connecting wires

QUANTITY
1
2
1 each
As Required
As Required

THEORY:
BINARY ADDER/SUBTRACTOR:
A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with four adders connected in cascade, with the output carry from
each full adder connected to the input carry of the next full adder in the chain. An n-bit adder
requires n full adders with each output carry from each full adder connected to the input carry
of the next neighbor order full adder.
A 4-bit parallel Adder/Subtractor performs the operations of both addition and
subtraction. The ex-or gates are used as control inverters. To perform subtraction, the control
input is kept high. Now the controlled inverter produces 1s complement of the addend. Since
one is given to Cin of the least significant bit of the adder, it is added to the complement of the
addend, producing 2s complement of the addend. Now the data will be added to the 2s
complement of the addend to produce SUM.
If the control input is low, the controlled inverter allows the addend without any change
to the input of full adder and the carry output Cin of least significant bit of full adder becomes
zero. Now augend and addend are added with C in equal to zero. Hence the circuit functions as 4bit adder resulting in SUM and CARRY.

PROCEDURE:
1.
2.

Give connections as per the logic diagram.

Give inputs as per truth table. For logic 1, connect the input pin to +5V and for
logic zero; connect the input pin to Ground.
3. Verify the corresponding truth table.

4-BIT BINARY ADDER/SUBTRACTOR

PIN DIAGRAM FOR IC 7483:

TRUTH TABLE:
Input Data A
Input Data B
A A A A B B B B
4
3 2 1 4 3 2 1
1
0 0 0 0
0 1 0
1
0
0
1
1
1

0
0
0
0
1
0

0
1
0
1
1
1

0
0
1
0
0
0

1
1
0
1
1
1

0
0
1
0
1
1

0
0
1
1
1
0

0
0
1
1
1
1

Addition
C S S S
4 3 2
0 1 0
1

S
1
0

Subtraction
B D D D D1
4 3 2
1 0 1 1 0

1
0
0
1
1
1

0
0
0
1
1
1

1
0
0
0
0
0

0
1
1
0
1
0

0
0
0
1
1
1

0
1
0
0
0
1

0
1
1
1
1
1

0
0
0
1
1
1

0
1
1
1
1
0

0
0
0
1
1
1

LOGIC DIAGRAM:

RESULT:

DATE:

EX.NO:
DESIGN AND IMPLEMENTATION OF BCD ADDER USING MSI DEVICES
(IC 7483)
AIM:
To design and implement BCD adder using IC7483.
COMPONENTS REQUIRED:
S.N
O
1
2
3
4
5

APPARATUS
Digital Trainer kit
IC 7483
IC 7486, IC 7432, IC 7408
Patch cords
Connecting wires

QUANTITY
1
2
1 each
As Required
As Required

BCD ADDER:
A BCD adder is a circuit that adds two BCD digits in parallel and produces a SUM digit
which is also BCD. A BCD adder must include the correction logic in its internal construction. A
BCD circuit must be able to do the following
i.
Add two 4-bit BCD numbers using straight binary addition.
ii.
If the 4-bit SUM is less than or equal to 9, the SUM is in proper BCD form And no
correction is needed.
iii.
If the 4-bit sum is greater than 9 or if a carry is generated from the SUM, the SUM is not in
BCD form. Then the BCD result is produced by adding 6 to the obtained SUM.
PROCEDURE:
1. Give connections as per the logic diagram.
2. Give inputs as per truth table. For logic 1, connect the input pin to +5V and for logic
zero; connect the input pin to Ground.
3. Verify the corresponding truth table

TRUTH TABLE:

A4
1
1
0
0
0
1
0

Input Data A
A3 A2
A1
0
0
0
0
1
0
0

0
0
1
0
1
0
1

LOGIC DIAGRAM:

0
0
1
1
0
1
0

Input Data B
B4 B3 B2 B1
0
1
1
0
0
0
0

0
0
0
1
1
1
1

1
0
0
1
1
0
0

0
0
1
1
1
1
1

OUTPUT
S4 S3 S2

S1

1
1
1
0
1
1
0

0
0
0
1
0
0
0

0
0
0
0
1
0
1

0
1
0
0
0
1
1

0
1
1
0
1
0
1

RESULT:
DATE:
EX.NO:
DESIGN AND IMPLEMENTATION OF MULTIPLEXERS/DE-MULTIPLEXERS
AIM:
To design and implement multiplexer and De-multiplexer using logic gates and study of
IC 74150 (Multiplexer IC), IC 74154 (De-Multiplexer IC).
COMPONENTS REQUIRED:
S.N
O

APPARATUS

QUANTITY

1
2
3
4
5
6

Digital Trainer kit

IC 7404
IC 7411
IC 7432, IC 74150, IC 74154
Patch cords
Connecting wires

1
1
4
1 each
As Required
As Required

THEORY:
MULTIPLEXER:
A multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of selection lines. Normally there are 2 n input lines and n selection lines
whose bit combinations determine which input is selected.
A multiplexer function like an electronic switch that selects one of the multiple sources. It
suggests visually how a selected one of multiple data source is directed into a single destination.
In a 4-to-1 line multiplexer, each of the four input lines (I 0 to I3) is applied to one input of
AND gate. Selection lines A and B are decoded to select a particular AND gate. The outputs of
the AND gates are applied to a single OR gate that provides the one output line. As a multiplexer
selects one of many input lines and steers the binary information to the output line, it is also
called as Data selector. The AND gates and inverters in the multiplexer resemble a decoder
circuit and indeed they decode the selection input lines.
IC 74150 is 16-to-1 Multiplexer IC. It has 16 input lines (E 0 to E15), 4 selection lines (A,
B, C, D) and 1 output line. The output of IC 74150 is active low.

DE-MULTIPLEXER:
A De-multiplexer is a combinational logic circuit that receives information on a single
input line and transmits it through anyone of the 2n output lines (where n is the number of
selection lines).The word de-multiplexer
means one into many. De-multiplexing is a process
of taking information from one input line and transmitting the same over one of the several
output lines.
The operation of a de-multiplexer is opposite to that of a multiplexer. The circuit has one
input line, n selection lines and 2n output lines. The selection inputs determine to which output
line the input data will be connected. As the serial data is changed to a parallel data , i.e. the input
caused to appear on any one of the 2n output lines, the de-multiplexer is also called as a
Distributor or a serial-to-parallel convertor.

1-to-4 De-multiplexer can be implemented using four 3-input NAND gates and two NOT
gates. Here the input data line is connected to all the AND gates. The two selection lines enable
only one gate at a time and the data that appears on the input line passes through the selected
gate to the associated output line.
PROCEDURE:
1.

Give connections as per the logic diagram.

2. Give inputs as per truth table. For logic 1, connect the input pin to +5V and for
logic zero; connect the input pin to Ground.
3. Verify the corresponding truth table.

4:1 MULTIPLEXER USING LOGIC GATES:

BLOCK DIAGRAM:

TRUTH TABLE:
S1

S0

Y = OUTPUT

D0

D1

D2

D3

Y= S1S0D0+S1S0D1+S1S0D2+S1S0D3
CIRCUIT DIAGRAM FOR MULTIPLEXER:

1:4 DEMULTIPLEXER USING LOGIC GATES:

BLOCK DIAGRAM:

TRUTH TABLE:
DATA SELECT
S1
S0
0
0

D0
D

OUTPUTS
D1 D2
0
0

D3
0

0
1
1

1
0
1

0
0
0

D
0
0

0
D
0

0
0
D

LOGIC DIAGRAM FOR DEMULTIPLEXER:

D0= S1S0D;
D1=S1S0D;

D2=S1S0D
D3=S1S0D

RESULT:
DATE:
EX.NO:
DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER USING LOGIC
GATES
AIM:
To design and implement ENCODER and DECODER using logic gates.
COMPONENTS REQUIRED:
S.N
O

APPARATUS

QUANTITY

1
2
3
4
5

Digital Trainer kit

IC 7404 , IC 74147, IC 7442
IC 7410, IC 7432
Patch cords
Connecting wires

1
1 each
3 each
As Required
As Required

THEORY:
DECODER:
A Decoder is a combinational circuit which converts binary information from n input
lines to a maximum of 2n unique output lines. If n-bit decoded information is unused or dont
care combination, the decoder output will have fewer than 2 n outputs. In general the number of
output lines in n to m line decoder is m2 n.In 3 to 8 line decoder, there are three inputs which are
decoded into eight outputs. The three inverters provide the complement of the inputs and each
one of the eight AND gates generate one of the minterms. The particular application of this
decoder would be a binary-to-octal conversion. The input variables may represent a binary
number and the outputs will then represent the eight digits in octal number system. Any one of
the output line is one at any given time. The output line whose value is equal to 1 represents the
minterm equivalent of the binary number presently available in the input lines.
ENCODER:
An encoder is a combinational circuit that performs the inverse operation of a decoder.
An encoder has 2n (or fewer) input lines and n output lines. The output lines generate the
binary ode corresponding to the input value.In octal-to-binary encoder there are eight inputs, one
for each of the octal digits and three outputs that generate the corresponding binary number. It is
assumes that only one input has a value of 1 at any given time. Then encoder can be
implemented with three OR gates whose inputs are determined directly from truth table. Output
Z=1 when the input octal digit is 1, 3, 5, 7. Output Y=1 for octal digits 2, 3, 6, 7. Output X=1 for
octal digits 4, 6, 5, 7.
Z=D1+D3+D5+D7
Y=D2+D3+D6+D7
X=D4+D5+D6+D7

PROCEDURE:
1. Make the connections as per the logic diagram.
2. Give the inputs as per the truth table. For logic 1, the input pin is connected to +5V and
for logic zero, the input pin is connected to the Gnd.
3. Verify the corresponding outputs for the given inputs using the truth table.
ENCODER USING LOGIC GATES:
TRUTH TABLE:
INPUT
Y1
Y2
Y3
Y4
Y5
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1

Y6
0
0
0
0
0

Y7
0
0
0
0
0

A
0
0
0
1
1

OUTPUT
B
0
1
1
0
0

C
1
0
1
0
1

0
0

0
0

0
0

0
0

DECODER USING LOGIC GATES:

TRUTH TABLE:
INPUT
E
A
B
1
0
0
0
0
0
0
0
1
0
1
0
0
1
1

0
0

1
0

D0
1
0
1
1
1

0
1

OUTPUT
D1
D2
1
1
1
1
0
1
1
0
1
1

1
1

1
1

D3
1
1
1
1
0

0
1

D0=EAB; D1=EAB; D2=EAB;D3=EAB

RESULT:

DATE:
EX.NO:
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS AND ASYNCHRONOUS
COUNTERS
4-BIT RIPPLE, MOD-10 RIPPLE COUNTER AND MOD-12 RIPPLE COUNTER
AIM:

To construct and verify 4-bit ripple counter, MOD-10 and MOD-12 ripple counters using
flip flop.
COMPONENTS REQUIRED:
S.N
O
1
2
3
4
5

APPARATUS
Digital Trainer kit
IC 7476
IC 7400
Patch cords
Connecting wires

QUANTITY
1
2
1
As Required
As Required

THEORY:
RIPPLE COUNTER:
A register that goes through a prescribed sequence of states upon the application of input
pulses is called counter. The input pulses may be clock pulses or they may originate from
external source. The sequence of states may follow the binary number sequence or any other
sequence of states. A counter that follows the binary number is called binary counter.
Counters are available in two categories
Ripple counter
Synchronous counter
In a Ripple counter, the flip flop output transition serves as the source of triggering the
flip flop.
4-BIT RIPPLE COUNTER:
It refers to first nine binary numbers. The count starts with binary 0 and increments by
one with each clock pulse input. After the count 15, the counter goes to 0. The least significant
bit is complemented at each clock pulse input. Every time A0 goes from 1 to 0, A1 is
complemented.
MOD COUNTERS:
Counters can be designed to generate any desired sequence of states. A divide by N
counter is also known as Modulo-N counter, a counter that goes through a repeated sequence of
N states. The sequence may follow the binary count or may be any other arbitrary sequence.
Counters are used to generate timing signals to control the sequence of operations in a digital
system. Counters can also be constructed using shift registers.
PROCEDURE:
1. Make connections as per the logic diagram.
2. Give input signals. For logic 1, connect the input pin to +5V and for logic zero;
connect the input pin to Ground.
3. Give Clock pulse one by one and verify the corresponding outputs for the given
inputs using the indication lamps.
IC 7676:

4 BIT RIPPLE COUNTER:

TRUTH TABLE:

CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

QD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

QC
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

QB
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

QA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

QA,QB,QC AND QD are OUTPUTS

CLK
0
1
2
3
4
5
6
7
8
9
10

QD
0
0
0
0
0
0
0
0
1
1
0

QC
0
0
0
0
1
1
1
1
0
0
0

QB
0
0
1
1
0
0
1
1
0
0
0

QA
0
1
0
1
0
1
0
1
0
1
0

MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:

LOGIC DIAGRAM FOR MOD - 10

RIPPLE COUNTER:

QA,QB,QC AND QD are OUTPUTS

MOD - 12 RIPPLE COUNTER:

TRUTH TABLE:

CLK
0

QD
0

QC
0

QB
0

QA
0

1
2
3
4
5
0
7

0
0
0
0
0
0
0

0
0
0
1
1
1
1

0
1
1
0
0
1
1

1
0
1
0
1
0
1

8
9

1
1

0
0

0
0

0
1

10
11
12

1
1
0

0
0
0

1
1
0

0
1
0

LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:

QA,QB,QC AND QD are OUTPUTS

RESULT:
DATE:
EX.NO:
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS AND ASYNCHRONOUS
COUNTERS
3-BIT SYNCHRONOUS UP/DOWN COUNTER
AIM:
To design and implement a 3-bit synchronous up/down counter.
COMPONENTS REQUIRED:
S.N
O
1
2
3
4
5

APPARATUS
Digital Trainer kit
IC 7476
IC 7432, IC 7486, IC 7411, IC 7404
Patch cords
Connecting wires

QUANTITY
1
2 each
1 each
As Required
As Required

THEORY:
To design a 3-bit up/down counter, the control inputs (count-up and count-down) are used
to allow either the normal output or the inverted output of the flip flop o the J and K inputs of the
flip flop. A 3-bit up/down counter will count from 000 to 111 when the count-up = 1 and when
count-down = 0. When count-down = 1 and count-up = 0, it counts from 111 to 000.
A logical 1 on the count-up line while count-down = 0 enables AND gates 1,3 and
disables AND gates 2 and 4. This allows the q A and qB outputs through the AND gates to J and K
inputs of the following flip flop. So the counter counts up when clock pulses are applied. The
reverse action takes place when count-up = 0 and count-down = 1.
PROCEDURE:
1. Make connections as per the logic diagram.
2. Give input signals. For logic 1, connect the input pin to +5V and for logic zero;
connect the input pin to Ground.
3. Give Clock pulse one by one and verify the corresponding outputs for the given
inputs using the indication lamps.

SYNCHRONOUS UP/ DOWN COUNTER:

STATE DIAGRAM:

CHARACTERISTICS TABLE:
Q

Qt+1

TRUTH TABLE:
Input
Up/Down(UD
)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Present State
QA QB QC

Next State
QA+1 Q B+1 QC+1

JA

KA

JB

KB

JC

KC

0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1

1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0

1
X
X
X
X
0
0
0
0
0
0
1
X
X
X
X

X
0
0
0
1
X
X
X
X
X
X
X
0
0
0
1

1
X
X
0
1
X
X
0
0
1
X
X
0
1
X
X

X
0
1
X
X
0
1
X
X
X
0
1
X
X
0
1

1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X

X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1

0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

SIMPLIFICATION USING K MAP:

LOGIC DIAGRAM:

1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

RESULT:

DATE:
EX.NO:
DESIGN AND IMPLEMENTATION OF SHIFT REGISTER
AIM:
To implement SIPO, SISO, PISO and PIPO shift registers using D-flip flop.
COMPONENTS REQUIRED:
S.N
O
1
2
3
4
5

APPARATUS
Digital Trainer kit
IC 7474, IC 7408
IC 7404, IC 7432
Patch cords
Connecting wires

QUANTITY
1
2 each
1 each
As Required
As Required

THEORY:
A register that is used to store binary information is known as a memory register. A Shift
register is a register which is capable of shifting binary information either to right or to the left.
SERIAL IN SERIAL OUT SHIFT REGISTER (SISO):

This type of shift register accepts data serially i.e. one bit at a time on a single input line.
It produces the store information on its single output also in serial form. Data may be shifted left
(from low to higher order bits) or right (from high to lower order bits) using shift left and shift
right registers respectively.
a) SHIFT LEFT REGISTER:
Using D-flip flops input o
f the rightmost flip flop is used as a serial input line. For input data 1,
one is applied at the D input and for input data 0, a zero is applied at the D
input. The clock pulse is applied to all the flip flops simultaneously. When the
shift or clock pulse occurs each flip flop is set or reset according to the data at the
respective flip flop input.
b) SHIFT RIGHT REGISTER:
A shift right register can also be constructed using D-flip flop. Entry of 4bits 1101 into the register, beginning with the right most bit. One is applied at the
serial input line i.e. at Delay input of the first flip flop. When the first clock pulse
is applied, flip flop A is set storing 1. Then a zero is applied to the serial input,
making D = 0 for flip flop A and D = 1 for flip flop B because D input of flip flop
B is connected to qA output. Similarly every bit is shifted right serially.
SERIAL IN PARALLEL OUT SHIFT REGISTER (SIPO):
It consists of one serial input and the outputs taken from all the flip flops are parallel. In
this register data is shifted in serially but shifted out in parallel. In order to shift the data out in
parallel it is necessary to have all the data available at the outputs at the same time. One the data
is stored, each bit appears on its respective output line and all the bits are available
simultaneously.
PARALLEL IN SERIAL OUT SHIFT REGISTER (PISO):
A 4-bit parallel in serial out register has four parallel input data lines (A, B, C, D) and a
control input (SHIFT/LOAD') that allows the four bits of data at the input lines to enter into the
register in parallel or shift the data in serial. When SHIFT/LOAD' is low, AND gates G 1 through
G3 are enabled allowing the data at the parallel inputs B,C and D to the Delay input of its
respective flip flop. The A input is directly connected to the Delay input of the first flip flop.
When the clock pulse is applied, the flip flops with D = 1 will be set and the flip flops with D = 0
will be reset, there by restoring all 4-bits simultaneously.
When SHIFT/LOAD' is high, AND gates G1 through G3 are disabled and the remaining
AND gates G4 through G6 are enabled allowing the data bits to shift right from one stage to the
next. The OR gates allow the normal shifting operation depending on which the AND gates are
enabled by the level on the SHIFT/LOAD' input.
PARALLEL IN PARALLEL OUT SHIFT REGISTER (PIPO):
In this type of register, data inputs can be shifted in or out of the register in parallel. The
parallel entry of the data is carried out and the output is also taken parallel. In this register, there
is no interconnection between successive flip flops since no serial shifting is required. Therefore
the moment the parallel entry of the input data is accomplished, the respective bits will appear at
the parallel output.
PROCEDURE:
1. Make connections as per the logic diagram.

2. Give input signals. For logic 1, connect the input pin to +5V and for logic zero;
connect the input pin to Ground.
3. Give Clock pulse one by one and verify the corresponding outputs for the given
inputs using the indication lamps.
IC 7474:

SERIAL IN SERIAL OUT:

LOGIC DIAGRAM:
SHIFT RIGHT

SHIFT LEFT

TRUTH TABLE:
CLK

DATA IN

DATA
OUTPUT

SERIAL IN PARALLEL OUT:

LOGIC DIAGRAM:

TRUTH TABLE:
OUTPUT
CLK

DATA

Q3
1

Q2
0

Q1
0

Q0
0

2
3

0
0

0
0

1
0

0
1

0
0

PARALLEL IN SERIAL OUT:

LOGIC DIAGRAM:

TRUTH TABLE:
SHIFT/
LOAD
1
0
0
0
0

CLK

O/P

0
1
2
3
4

1
X
X
X
X

1
X
X
X
X

0
X
X
X
X

1
X
X
X
X

0
1
0
1
1

PARALLEL IN PARALLEL OUT:

LOGIC DIAGRAM:

TRUTH TABLE:
CLK
1
2
3
4

RESULT:

D3
1
1
1
1

DATA INPUT
D2
D1
0
0
0
1
1
0
0
1

D0
1
0
0
1

Q3
1
1
1
1

OUTPUT
Q2
Q1
0
0
0
1
1
0
0
1

Q0
1
0
0
1