INTEGRATION, the VLSI journal 50 (2015) 1627

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INTEGRATION, the VLSI journal

journal homepage: www.elsevier.com/locate/vlsi

A new write assist technique for SRAM design in 65 nm

CMOS technology
Hooman Farkhani a,n, Ali Peiravi a, Farshad Moradi b
a
b

Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran

Integrated Circuits and Electronics Lab., Department of Engineering, Aarhus University, Aarhus, Denmark

art ic l e i nf o

a b s t r a c t

Article history:
Received 18 May 2014
Received in revised form
25 November 2014
Accepted 12 January 2015
Available online 21 January 2015

In this paper, a new write assist technique for SRAM arrays is proposed. In this technique, to improve the
write features of the SRAM cell, a negative voltage is applied to one of the bitlines in the SRAM cell while
another bitline is connected to a boosted voltage. Improved write features are attributed to the boosting
scheme from both sides of the SRAM cell. This technique is applied to a 10T-SRAM cell with
transmission-gate access devices. The proposed design gives 2.7
, 2.1
faster write time, 82% and
18% improvement in write margin compared with the standard 8T-SRAM cell with and without write
assist, respectively. All simulations have been done in TSMC 65 nm CMOS technology. The proposed
write assist technique enables 10T-SRAM cell to operate with 24% lower supply voltage compared with
standard 8T-SRAM cell with negative bitline write assist. Due to the improved supply voltage scalability a
33% leakage power reduction is achieved.
& 2015 Elsevier B.V. All rights reserved.

Keywords:
SRAM
Write margin
Read static noise margin
Write assist

1. Introduction
CMOS technology has been the cornerstone of semiconductor
devices for years. Moore's law motivates the technology scaling in
order to improve the performance features such as speed, power
consumption and area. Although circuits and systems benet from
technology down-scaling in some aspects, the undesired features
such as short channel effects (SCEs) and sensitivity to process
variations are also consequential. The effect of process variations on
performance is a key issue in scaled CMOS technology. This effect
gets more pronounced as the size of transistors is reduced. One of the
highly sensitive circuits to process variations is SRAM due to using
extremely small devices in order to achieve high density. Process
variations can be due to global or local mismatches between devices.
Global mismatch refers to die-to-die variation in device and local
mismatch refers to mismatch between transistors on the same die
[1]. Local mismatch in SRAM devices can easily lead to read stability
degradation (stored data is ipped during read), read failure (data is
not read during read period), writeability decrease or write time
increase. On the other hand, the trade-off between read and write
operations makes it difcult to improve both simultaneously.
Fig. 1(a) shows the standard 6T-SRAM cell structure. It consists
of two back to back inverters (PUL-PDL and PUR-PDR) that keep
n

Corresponding author.
E-mail addresses: Farkhani.hooman@stu.um.ac.ir (H. Farkhani),
Peiravi@um.ac.ir (A. Peiravi), moradi@eng.au.dk (F. Moradi).
http://dx.doi.org/10.1016/j.vlsi.2015.01.001
0167-9260/& 2015 Elsevier B.V. All rights reserved.

the data and its inverse on nodes Q and QB, respectively. The
access transistors (ACL-ACR) are used to perform read and write
operations. Due to using a common path (ACL-ACR) for read and
write operations, improving the read stability will lead to degradation of the writeability of the cell and vice versa. To improve the
read stability of an SRAM cell, beta ratio ( WPD/WAC) can be
increased, while lower alpha ratio ( WPU/WAC) is desirable to
improve the cell writeability. Finally, during hold mode, equal
strength for pull up and pull down transistors (WPU WPD) sets the
trip point of the two back-to-back inverters at VSUPPLY/2 and
ensures maximum noise margin.
Several solutions have been proposed in literature from device to
architecture level to improve SRAM cell functionality. For instance,
at the device level, using new devices such as FinFET, leads to
signicant SRAM performance improvement [15]. At the cell level,
new cells such as 7T, 8T, 9T, 10T, and 11T [515] have been proposed
that have resulted in a higher cell area. Among them standard 8TSRAM cell shows a very good compromise between cell features
improvement and cell area penalty [6]. Fig. 1(b) shows the standard
8T-SRAM cell. This cell consists of a 6T storage cell and a 2T read
buffer which isolates read path from write path and storage nodes.
In this way, read and write features can improve simultaneously.
However, the write margin of the SRAM cell varies signicantly due
to the process variations of access transistors. This is due to the fact
that the write current ows through the access transistors and
corresponding variations will affect the write margin of the SRAM
cell signicantly. On the other hand, while reading the cell, the read

H. Farkhani et al. / INTEGRATION, the VLSI journal 50 (2015) 1627

17

Fig. 1. (a) Standard 6T- (b) Standard 8T- (c) PPN 10T- [13] (d) 10T- [14] (e) TGA 10T-SRAM cells [15].

current ows through the read buffer (R1 and R2) which its
variation does not affect read margin. As a result, the write margin
is a key parameter especially in the scaled supply voltages which
the effect of process variation is more pronounced. Supply voltage
scaling is an effective way to decrease the power consumption of
the System-on-Chips (SoCs). 10T-SRAM cells are mainly proposed to
work in ultra-low voltages (near/subthreshold region). Fig. 1(c)
(e) shows three 10T-SRAM cell schematics. Lo et al. proposed a PP
N 10T-SRAM cell in [13]. This cell is called PPN due to the fact that
each of the cross-coupled inverters consists of three transistors
cascaded in a PPN sequence as shown in Fig. 1(c). This cell shows
a low cell leakage due to the three stacked transistors as inverter
and it also has a good immunity to data dependent bitline leakage
[13]. However, the use of stacked transistors limits supply voltage scaling. Fig. 1(d) shows another 10T-SRAM cell in the literature
which uses two transistors in series as access device [14]. Utilizing
two control signals (WL and W_WL) enables implementation of bitinterleaving structure. The main drawback of this cell is related to its
weak writeability due to the cascaded access transistors which can
limit the power supply scaling. Fig. 1(e) shows the TransmissionGate Access transistor SRAM cell (TGA-SRAM) proposed in [15]. The
transmission gate access devices are used to improve the writeability of the cell that improves the supply voltage scalability, as
well. On the other hand, the read path is isolated from storage nodes
that results in a high read noise margin. Single ended read sensing
scheme will decrease the TGA-SRAM cell access time. However,
utilizing pseudo-differential sensing improves the access time,
signicantly [16]. All in all, each of the 10T-SRAM cells has some
pros and cons which mentioned above. However, comparing the
cells is not the focus of this paper and we will use only one of the
above mentioned cells in order to apply the proposed write assist
technique.
At the architecture level, read and write assist techniques
improve SRAM robustness and performance while occupying less
area compared to the cell techniques (e.g. 8T and 10T) and can be
used with any type of SRAM.
In this paper, a new write assist technique is proposed that
improves SRAM writeability, signicantly. This new technique
applies a boosted voltage (VDD V) to the high-going bitline
and a negative voltage on the low-going bitline simultaneously.
This technique results in a signicant improvement in Write

Margin (WM) and Write Time (WT). In this technique, coupling

capacitances are used to produce boosted and negative voltages.
In order to make Boosted-Negative Bit-Line (BNBL) technique
more efcient, the TGA 10T-SRAM cell is used. Simulation results in
65 nm CMOS technology show 2.7
and 2.1
faster write time and
82% and 18% improvement in write margin compared with 8T-SRAM
cell without and with write assist technique, respectively.
The remainder of this paper is organized as follows. In Section 2,
a brief survey of existing write assist techniques is presented. In
Section 3, the basic concept of the proposed BNBL technique is
presented and validated by mathematical analysis. The efcacy of
BNBL technique is shown in Section 4 through simulation results.
Finally, the conclusions are drawn in Section 5.

2. State of the art

In this section, existing write assist techniques such as cell VDD
collapse, negative bit-line, boosted word-line and cell GND boost
are discussed. The circuit implementation of the best technique
amongst them (negative bit-line) is discussed with three examples.
2.1. Write assist techniques
In order to improve the write margin of SRAMs, several write assist
techniques have been proposed. Some of these techniques rely on cell
VDD collapse [1720], Negative Bit-Line (NBL) [2125], Boosted WordLine (BWL) and cell GND boost [26]. Negative bitline write assist circuit
applies a small negative voltage ( V) instead of GND at the lowgoing BL. This negative voltage on BL increases the strength of the
access transistor by increasing VGS from VWL to VWL V (VWL is the
wordline voltage). Strengthening the access transistor without any
effect on back-to-back inverters leads to improved writeability.
The BWL technique increases the word line voltage (VWL)
connected to the gate of access transistors (ACL and ACR in Fig. 1)
during write operation. This increases the gate source voltage of
access transistors (VGS-ACL and VGS-ACR) and improves its driveability.
Cell VDD collapse and cell GND boost techniques improve the
writeability of the cell by weakening the back to back inverters
during write operation. However, these techniques degrade the

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H. Farkhani et al. / INTEGRATION, the VLSI journal 50 (2015) 1627

Hold Static Noise Margin (HSNM) of the half-selected cells and are
not suitable for low voltage applications.
Among the existing techniques, negative bitline write assist is
the most effective one to reduce SRAM minimum supply voltage,
especially when considering dynamic failure metrics [27].

2.2. Negative bit-line write assist technique

Negative Bit-Line (NBL) write assist technique improves write
margin of SRAMs by producing a negative voltage on the low-going
bitline instead of ground. Instead of using a negative voltage source,
recent works [21,23,25] use capacitive-coupling to generate the
required negative voltage level on bitline. In NBL technique which
uses capacitive-coupling, the negative voltage level on BL and the
time this voltage is applied to the bitline are very important. A
smaller negative voltage on the bitline will be achieved if the boost
capacitor (Cboost) is applied before fully discharging the bitline to
ground. This results in insufcient write margin improvement. On
the other hand, the use of a large Cboost leads to a larger negative
voltage level on the bitline. This negative voltage can turn on the
access transistors of the unselected cells in the accessed column and

Fig. 2. Use of a replica column along with write buffer in order to make a negative
bitline voltage during write operation [25].

result in reliability issues. Another important issue while using NBL

write assist technique is that Cboost can increase the bitline capacitance. This will lead to a longer access time. Therefore, Cboost has to
be disconnected from bitline during read operation.
The write assist technique in [25] is shown in Fig. 2. In this
technique, a negative voltage is applied to the low-going bitline
during write cycle. Cboost is used to make the negative voltage on the
desired bitline. This structure uses a replica column (bitline capacitance monitor) in order to apply the negative voltage at the most
suitable time with appropriate charge on Cboost. By means of this
technique, the NBL voltage level is kept at a suitable range. In replica
column, two bitlines are connected to each other to produce a
capacitor with 2CBL capacitance (CBL is the capacitance of bitline).
Therefore, when the replica column discharges to VDD/2, the bitline is
almost discharged to ground. Consequently, the appropriate time to
apply the negative voltage to the bitline is determined. However, the
main issue of this structure is related to the mismatch between N1t,
N1c, and NA which can affect the negative voltage level at the bitline.
Another proposed design in the literature is to use a replica
column with a replica write buffer in order to nd the best time for
connecting the boosting capacitor to the bitline (Fig. 3) [21]. During
write cycle, the write signal triggers the replica write buffer in order
to discharge the replica bitline (RBL). RBL together with the delay
block generates the required negative bitline enable signal (EN_NBL).
When EN_NBL signal goes low Cboost is coupled with ground of the
bitline drivers and makes a negative voltage on the low-going bitline.
Mukhopadhyay et al. proposed a technique in [23] that is
shown in Fig. 4. Two boosting capacitors (Cboost) connected to
the bitlines (BL and BR) are used to make a negative voltage level
on the appropriate bitline. The write operation starts by enabling
the BIT_EN and NSEL signals. NSEL turns on the column select
transmission gates and then BR starts to discharge to ground.
Furthermore, Cboost connected to the BR starts to charge through
BIT_EN and BR. In the middle of the write operation (when BR is
discharged to ground), BIT_EN and NSEL go down. These cause a
drop on bitlines (BL and BR) due to capacitive coupling. It makes
BR negative and the drop on BL is compensated by the crosscoupled PMOS pair (P1P2). In this structure, by directly connecting the Cboost to the bitline, the capacitance of BLs increases that
leads to a longer access time. On the other hand, the most
appropriate time for connecting Cboost to BR is exactly after
discharging BR to ground (T0). However, T0 varies due to the
existing process variations. Therefore, connecting Cboost at the

Fig. 3. Use of a replica column with a replica write buffer in order to nd the best time of connecting the boost capacitor [21].

H. Farkhani et al. / INTEGRATION, the VLSI journal 50 (2015) 1627

19

In the following section, a new technique is proposed to

improve write margin and write time by applying a voltage higher
than supply voltage to the high-going BL while the low-going BL is
connected to a negative voltage. The proposed technique results in
a larger improvement in write margin and write time compared to
NBL technique.

3. Proposed boosted-negative bitline write assist technique

The basic concept of the proposed write assist technique along
with its circuit implementation and mathematical analysis are
discussed in this section.
3.1. Basic concept

Fig. 4. Using two boosted capacitors in order to make a negative voltage on the
appropriate bitline [23].

BL

BLB
WL

WL
Q=0'

QB=1'

ACR

ACL

SACL

SACR

BL

BLB

WL
TNL

WL
TNR
Q=0

1
TPL
WLB

QB=1

RBL

RWL
0

TPR
WLB

R2
R1

STNL-TPL

STNR-TPR

Fig. 5. Write operation on (a) SRAM cells with conventional write path and
(b) TGA-SRAM cell [14].

middle of write operation only ensures that coupling will happen

after BR discharges to ground and it is not the best time for
achieving maximum write time.
In the structures used in [21,23], the bootstrapped capacitor does
not put extra capacitance on the bit-line during read operation.
Therefore, these NBL structures do not have any effect on access time.

The write path in most of SRAM cells consists of two NMOS

transistors which connect the storage nodes to the BLs. Fig. 5(a) shows
how the conventional write path (NMOS access devices connected to
storage nodes) can be considered as a see-saw with two stable states.
In order to change one state to another (write operation), sufcient
forces (strength of the access transistors) are required from both sides.
Changing the state is possible by applying only one force to one side.
However, applying forces on both sides of this see-saw in the opposite
direction (as shown in Fig. 5(b)), helps to change the state much easier
(equivalent to write improvement in SRAM cell). For simplicity, in the
rest of this section, it is assumed that node Q holds 0 and node QB
holds 1. Once write cycle starts the strength of access transistors (ACL
and ACR) are equal (VGS-ACL VGS-ACR VWL). As soon as the voltage of
node Q0 starts to increase, VGS-ACL starts to decrease. It leads to a
degradation in the strength of ACL and this transistor enters to the cut
off region at VQ VWL  VTH-ACL. Therefore, in most of the SRAM cells,
write operation is mostly done by the access transistor connected to
the node holding 1 (ACR in this case). This is the reason of why most
of the write assist techniques improve the strength of the access
transistor connected to the node storing 1.
In order to improve writeability, through keeping the ACL
transistor ON during entire write cycle, we can use TGA-SRAM cell
with transmission gate access devices (TNL-TPL and TNR-TPR) as
shown in Fig. 5(b) [15]. The main advantage of TGA-SRAM cell is that
it lets to apply write assist technique to both sides of the cell. When
the write cycle starts in TGA-SRAM cell, the voltage of node Q starts
to increase and the strength of TNL will decrease accordingly.
However, VGS-TPL VWLB-VBL remains constant and TPL continues to
charge node Q to the end of write cycle with maximum strength.
Therefore, one of the NMOS or PMOS transistors in the transmission
gate structure always conducts during write operation with the
maximum strength (the one with its source connected to the bitline).
It means that the forces applied to both sides of the cell remain at the
appropriate levels during write cycle that result in writeability
improvement (Fig. 5(b)). Moreover, TGA-SRAM cell allows applying
write assist techniques to both sides of the cell simultaneously that
leads to signicant write improvement. In the following section we
propose a new write assist technique which uses this feature of the
TGA-SRAM cell in order to improve the writeability of the cell
through applying forces to both sides of the cell.
3.2. Proposed boosted-negative bitline scheme
Fig. 6 shows the SRAM array design including the proposed write
assist circuit. The TGA-SRAM cell is used to achieve a higher WM. The
write assist circuit consists of two capacitors, CP-boost and CN-boost, to
produce the boosting (VDD ) and the negative ( ) voltage levels,
respectively. The replica column is used to determine the best time of
connecting the boosting capacitors to the bitlines [25]. The bitlines in
the replica column are connected to each other in order to make a

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H. Farkhani et al. / INTEGRATION, the VLSI journal 50 (2015) 1627

RWL[0]

WLB[0]

RBL[m]

BLB[m]

BL[m]

RBL[0]

CELL

BLB[0]

BL[0]

t0

WL[0]

t1

WR

RBL
RP

RWL[n]

VDD+

WL[n]
BL

CELL
WLB[n]

BLB

BLS[0-m]

Column Decoder

BLBS[0-m]

REBL

Sense Amp.

C1

WR

C2 C1

C1 C2

C2

C1 C2

DB

MP
CP-boost
+

WD1
VB

WD2

CN-boost
-

WR

VN
RP

Replica Column

MN

Write Assist Circuit

Data

Fig. 6. Proposed boosted bitline scheme.

2CBL. Therefore, when the replica column discharges to VDD/2, the

bitline is almost discharged to ground. Suppose that the data needs to
be written on the selected cell is 1 (Data1). When the write cycle
starts, WR signal is enabled and REBL starts to discharge (t0).
Meanwhile, MP and MN transistors in write assist circuit turn on
and start to charge CP-boost and CN-boost, respectively with a polarity
shown in Fig. 6. On the other hand, C2 control signal is enabled (C1 is
disabled) and BLB starts to discharge to ground through the transistors in write path. When replica bitline is discharged to VDD/2 (BLB
discharged to GND), RP is enabled (t1). When RP goes high, transistors
MP and MN turn off and the control signal C1 is enabled (C2 is
disabled). These make a boosted voltage (VDD ) and a negative
voltage ( ) on VB and VN, respectively. This is done through the
charges stored on CP-boost and CN-boost and the left side inverters
connected to them. These boosted and negative voltages are transferred to the bitlines through WD1 and WD2, respectively. Hence, not
only the gate-source voltage of NMOS transistor of transmission gate
connected to BLB (TNR) increases but also the source-gate voltage of
PMOS transistor of transmission gate connected to BL (TPL) will
increase in the selected cell. Therefore, two simultaneous forces are
applied to both sides of the selected cell during write operation that
lead to a noticeable improvement in writeability.
3.3. Control signals implementation
The implementation of the control signals C1 and C2 and data
signals D and DB are depicted in Fig. 7. When the write cycle starts,
before RP signal goes high (t0 otot1), RP 0 and WR is equal to
1. Therefore, signals C2 and C1 are enabled and disabled, respectively. This will result in discharged BLB to ground via the inverter

RP
C2
WR

RP

D
Data

C1

DB

Fig. 7. Data and control signals implementation.

connected to DB (i.e. inverse of input data). When RP goes high (t1),

C2 is disabled and C1 is enabled to connect the boosted and
negative voltages to BL and BLB, respectively. Hence the negative
and boosted capacitors (CN-boost and CP-boost) will connect to the
bitlines at the most appropriate time (i.e. immediately after
discharging the BLB) that will give the maximum writeability.
3.4. Mathematical analysis
The mathematical model of the TGA-SRAM cell is prepared in this
section in order to explore the effect of proposed write assist
technique on the write operation. The equivalent simple circuit of
TGA-SRAM cell (Fig. 5(b)) at the side of node QB is shown in Fig. 8(a).
Node QB holds 1, hence pull up transistor PUR is in its linear region
and is considered as a resistor (RPUR). CQB is the total capacitance at
node QB. Transmission gate transistors (TNR-TPR) are considered as
current sources ITNR and ITPR. CBLB and CN-boost are the total capacitance of BLB and the boosting capacitor of write assist circuit,

H. Farkhani et al. / INTEGRATION, the VLSI journal 50 (2015) 1627

RPUR

ITNR

Similarly, a KCL at node Q while TNL and TPL are in saturation

region and considering PDL as a resistor, gives VQ as follows:
!
a2 t


p



q
2

b2
 b2 2 4a2 c2
1  e CQ b2  4a2 c2

ITNR
CN

VQB

VQB

CQB

!
a2 t
p
 p
2
b2 j  b2  4a2 c2
j
b2 2  4a2 c2
CQ
p

2a 1 
e
jb2 j b2 2  4a2 c2

VQ

VBLB
VN

VBLB
ITPR

ITPR

CBLB

where
a2

TNL

2


1
b2  TNL V DD V THN
RPDL

TGA_SRAM Cell

WLB

21

SRAM Cell with

conventional write path
WT
improvement

c2

TNL
2

V DD  V THN 2

TPL
2

jV BL j jV THP j2

WL

RPDL
Fig. 8. (a) The equivalent simple circuit of TGA-SRAM cell at the side of QB node
and (b) voltage variation of Q and QB while write operation in SRAM cell with
conventional write path and TGA-SRAM cell.

respectively. In order to see the effect of BNBL write assist on TGASRAM cell writeability, we nd equations for VQB and VQ. To simplify
the equations, VBL and VBLB are assumed to be constant. When the
write cycle starts, PUR is in its linear region and TNR and TPR are in
saturation region. A KCL at node QB gives:
C QB

dV QB
I PUR  I TNR  I TPR
dt

I PUR

I TNR
I TPR

V DD  V QB
RPUR

TNR
2

TPR
2

V DD  V BLB  V thn 2

V QB  j V thp j 2

From (1) to (4) and considering VQB VDD at t0 s, VQB is

calculated as follows:

V QB

a1 t
  p


q


q
2
2
2

b1
 b1  4a1 c1 Ze CQB b1  4a1 c1
b1
 b1  4a1 c1
!
a1 t
p

2
Ze CQB b1  4a1 c1  1 j2a1 j

PD V QB V THN

Eq. (6) shows the voltage equation for the node Q holding 0
while writing 1 on it in TGA-SRAM cell. The parameters a2 and c2
are positive while b2 is negative. By boosting the voltage on BL using
the proposed write assist technique, c2 value will increase. In order
to explore the effect of growth in c2 on VQ, we simplied Eq. (6) in
(7) and the increment and decrement in each parenthesis are
shown withand , respectively. As can be seen in (7), increase of
c2 leads to an increase in both numerator and denominator of
Eq. (7). However, the pace of increase in the numerator is much
faster than the denominator that causes a faster rise in VQ. As a
result, it improves write margin and write time of the proposed cell.
Faster increase of VQ has two positive effects on the write operation
as it can be seen in Fig. 8(b). First, faster increase of VQ leads to a
much shorter write time. This is due to the fact that contrary to that
of conventional SRAM cells, where charging the VQ is mainly done
by the back to back inverters, in TGA-SRAM cell, charging node Q is
done through both access devices connected to the boosted bitline
and back to back inverters. The second reason is that faster increase
in VQ means faster decrease of VSG-PUR (source-gate voltage of TPUR)
that will lead to a faster decrease in the strength of TPUR. Therefore,
access devices (TNR-TPR) can discharge the storage node QB easier
(Fig. 8(b)). Faster discharge of node QB has the same effect on node
Q and it works like a positive feedback that improves write margin
and write time, signicantly.
VQ

1 


2a 1 

5
where a1 , b1 , c1 , and Z are:
a1 

TPR
2

b1 TPR jV THP j

c1

4. Simulation results

1
RPUR

V DD TPR

V THP 2  TNR V DD  V BLB  V THN 2


RPUR
2
2

q





2a V b b 2  4a c

1
1
1 1


1 DD
q

Z





2

2a1 V DD b1  b1  4a1 c1

RPUR

PU V DD  V Q  jV THP j

Simulation results of TGA-SRAM cell in 65 nm CMOS technology

conrm that the use of the proposed BNBL technique results in a 2.7

faster WT and 82% improvement in WM compared to the standard 8TSRAM cell without write assist. The 8T-SRAM cell is used to represent
conventional write path. On the other hand, the use of BNBL technique
enables more aggressive supply voltage scaling by 24% which leads to
a 33% leakage power improvement. The proposed BNBL circuit is used
for an 8Kb SRAM array (256
32). In order to implement the boosting capacitors CN-boost and CP-boost, MOSCAPs with LCN-boost 1 m,
WCN-boost 2.5 m, LCP-boost 1 m, and WCP-boost 2.5 m are used.
The total area of SRAM cell is determined by the SRAM array and the
peripheral circuits take less than 30% of the total area [28]. BNBL write
assist circuit has an extra MOSCAP and ve transistors compared with
NBL circuit. Hence, it does not have a signicant impact on the total
area. Simulations are performed at 1 V supply voltage and

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H. Farkhani et al. / INTEGRATION, the VLSI journal 50 (2015) 1627

Temp 27 1C in Cadence. The widths of the transistors in the 8T- and

TGA-SRAM cells are tabulated in Table 1. The length of all transistors is
the minimum channel length, 60 nm.

4.1. Comparison of write assist techniques

In this section, the effect of the proposed BNBL write assist
technique on write margin of TGA-SRAM cell is compared with
existing NBL, BWL, cell VDD collapse and cell GND boost

techniques. Different methods have been used to nd the WM of

an SRAM cell [29]. Due to the fact that in pervious SRAM cells the
write operation is mainly done from the side of the cell connected
to low-going bitline, most of the developed methods to calculate
WM only consider the effect of low-going bitline. To take the effect
of both bitline voltages on WM into consideration, we choose the
Word-Line (WL) voltage sweep method. In this method the
bitlines will be connected to the appropriate voltages to enable
ipping the data on the storage node. Then WL and WLB are swept
from 0 V to 1 V and 1 V to 0 V, respectively. WM is calculated as

Table 1
Transistors width of standard 8T- and TGA-SRAM cells.
PUR (nm)

PDR (nm)

R1 (nm)

R2 (nm)

ACL (nm)

ACR (nm)

TNL (nm)

TPL (nm)

TNR (nm)

TPR (nm)

150
150

150
150

150
150

150
150

180
180

180
180

180

180

180

230

180

230

Storage node voltage (V)

PDL (nm)

Storage node voltage (V)

Standard 8T
TGA

PUL (nm)

1.2
1
Q node
QB node

0.8
0.6
0.4

Write Margin

0.2
0
-0.2

0.2

0.4

0.6

0.8

1.2
1

Q node
QB node

0.8
0.6

238mV

0.4
0.2
0
-0.2

0.2

1.2
1
Q node
QB node

0.8
0.6

186mV

0.4
0.2
0
-0.2
0

0.2

0.4

0.6

0.8

Q node
QB node

0.6

162mV

0.4
0.2
0
-0.2
0

Storage node voltage (V)

Storage node voltage (V)

Q node
QB node
82mV

0.2
0
-0.2
0.2

0.4

0.6

WL voltage (V)

0.2

0.4

0.6

0.8

1.2

WL voltage (V)

0.8

0.8

1
0.8

0.4

0.6

1.2

WL voltage (V)

0.6

0.4

WL voltage (V)

Storage node voltage (V)

Storage node voltage (V)

WL voltage (V)

0.8

1.2
1
Q node
QB node

0.8
80mV

0.6
0.4
0.2
0

0.2

0.4

0.6

0.8

WL voltage (V)

Fig. 9. Write margin (VDD minus ipping point voltage) of the TGA-SRAM cell when utilizing (a) no write assist, (b) proposed BNBL technique with VBL 1.2 V and
VBLB 0.2 V, (c) NBL technique with VBLB 0.2 V, (d) boosted WL technique with VWL 1.2 V, (e) cell VDD collapse technique with VDD 0.8 V, (f) cell GND boost with
VGND 0.2 V. The difference between the dashed line and the ipping point of the storage nodes shows the write margin improvement.

H. Farkhani et al. / INTEGRATION, the VLSI journal 50 (2015) 1627

23

Write margin (normalized)

Normalized to 8T-SRAM cell with NBL

t0

t1

Normalized to TGA 10T without write assist

Normalized to 8T-SRAM cell without write assist

Case 1:
WL enabled after discharging
the low-going bitline to ground

1.5

WL

VDD+
Case 2:
WL enabled at the start of
write cycle

1
0.5

BL

BLB
-

0,1

-0.1 , 1.1

-0.2 , 1.2

-0.3 , 1.3

Negative and boosted voltage (V , V)

1.2

the difference between VDD and WL voltage when the data stored
in the cell is ipped.
Fig. 9 shows the write margin for the TGA-SRAM cell when
utilizing: (1) no write assist technique; (2) proposed BNBL technique (VBL 1.2 V and VBLB  0.2 V); (3) NBL technique (VBLB
0.2 V); (4) BWL technique (VWL 1.2 V); (5) cell VDD collapse
(VDD 0.8 V), and; (6) cell GND boost (VGND 0.2 V) techniques. A
20% voltage increase for boosted BL, cell GND boost and boosted
WL techniques is considered while a 20% voltage decrease is used
for cell VDD collapse and negative BL techniques in order to make a
fair comparison.
The WM of the proposed BNBL technique (2) is higher than the
existing techniques (36). The WM improvements of BNLB, NBL, BWL,
cell VDD collapse and cell GND boost techniques over the cell without
write assist technique are 54%, 42%, 36%, 19% and 18%, respectivly. The
BNBL technique has the highest WM improvement. This is attributed
to the assisted write operation from both sides of the cell. Cell GND
boost and cell VDD collapse techniques have the minimum WM
improvement. This is due to the fact that boosting cell GND decreases
VDS of the access devices connected to Q and increases the trip point
of the right hand side inverter (Fig. 1(e)). On the other hand, cell VDD
collapse technique decreases VDS of the access devices connected to
QB and decreases the trip point of the right hand side inverter.
The NBL write assist technique is the best technique among the
existing techniques in order to improve the WM. In the rest of the
paper, the effect of proposed BNBL technique on TGA-SRAM cell is
compared with TGA-SRAM cell without write assist and 8T-SRAM
cell with NBL write assist technique.
4.2. Write margin
Fig. 10 shows the normalized WM for different negative and
boosted bitline voltages. WM is normalized to the WM of TGASRAM cell without write assist, 8T-SRAM cell with NBL write assist
and without write assist. Fig. 10 justies the idea that applying
simultaneous forces to both sides of the cell improves its writeability.
As illustrated in Fig. 10, increasing the VBBL and |VNBL| improves WM of
TGA-SRAM cell compared with 8T-SRAM cell without write assist
signicantly (2.2
improvement at VBBL 1.3 V and VNBL  0.3 V).
On the other hand, applying BNBL technique improves WM by 18%
compared with 8T-SRAM SRAM cell with NBL write assist. It should be
noted that higher VBBL and |VNBL| voltages needs larger boosting
capacitors which increase the area overhead. Besides, it can cause
higher failure probability in unselected cells by turning on their access
transistors. In order to deal with this issue, we chose  0.2 V and 1.2 V
voltage levels for negative and boosted bitlines, respectively. In this
way the gate-source voltage of access transistors in unselected cells
are far enough from their threshold voltage and they will be OFF

Write time (normalized)

Normalized to 8T-SRAM cell with NBL

Fig. 10. Write margin of the TGA-SRAM cell while using proposed write assist
technique. Write margin normalized to the write margin of TGASRAM cell without
write assist and standard 8T-SRAM cell with and without NBL write assist.

Normalized to TGA 10T without write assist

Normalized to 8T-SRAM cell without write assist

0.8
0.6
0.4
0.2
0

-0.1 , 1.1

0,1

-0.2 , 1.2

-0.3 , 1.3

Negative and boosted voltage (V , V)

Fig. 11. (a) Timing diagram of write cycle. (b) Write time of proposed write assist
technique vs. negative and boosted bitline voltages. Write time normalized to the
write time of TGA-SRAM cell without write assist (gray columns), standard 8T-SRAM
cell without write assist (black columns) and with NBL write assist (dashed columns).

during write cycle. Besides, the negative and boosted voltages are
sufcient enough to make a large improvement in WM. For VBL and
VBLB at  0.2 V and 1.2 V, WM is improved by 54%, 18% and 82%
compared with TGA-SRAM cell without write assist, standard 8TSRAM cell with and without NBL write assist, respectively.
4.3. Write time
In order to nd the write time, the time between asserting WL
and when both storage nodes reach to 90% of their nal values is
measured. Fig. 11(a) shows the timing diagram during write cycle
where t0 is the beginning of write cycle and t1 is when low-going
bitline is discharged to ground. The write operation can be divided
into two parts: (a) Discharging the appropriate bitline to ground
(t0 ot ot1). (b) Applying the write assist technique to the bitlines
(t4 t1). As illustrated in Fig. 11(a), during write cycle, WL signal
can be asserted from the beginning of write operation (case 1) or
after low-going bitline is discharged to ground (case 2). However,
in NBL write assist technique, the coupling capacitor needs to be
connected to the low-going bitline after it is fully discharged to
ground, otherwise the negative voltage will be higher and WM
improvement decreases drastically [21]. Fig. 11(b) shows the effect
of the proposed write assist technique on the write-time. As
illustrated in Fig. 11(b), applying a  0.2 V negative voltage and
1.2 V boosted voltage to the bitlines leads to 2.7
and 1.5

improvement in the write time compared to the 8T-and TGASRAM cells without write assist circuit. Besides, the proposed
write assist technique results in 2.1
improvement in write time
compared with the 8T-SRAM cell using NBL write assist circuit.
4.4. Half-selected cells
In this section, the effect of the proposed write assist technique
on the half-selected cells of TGA-SRAM cell is explored.

24

H. Farkhani et al. / INTEGRATION, the VLSI journal 50 (2015) 1627

WM-8T with NBL

WM-TGA

Voltage (mV)

600

WM-TGA with BNBL

RSNM-8T & TGA
HSNM-TGA with BNBL

500
400
300
200

4.6. Supply voltage scalability

100
0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

Supply Voltage (V)

WM-8T with NBL

WM-TGA

200

-6 (mV)

WM-TGA with BNBL

WM-TGA with BNBL

RSNM-8T & TGA
HSNM-TGA with BNBL

150
100

WM-8T with NBL

50
WM-TGA

0
0

0.1

0.2

0.3

0.4

0.5

-50

65mV
-100

Dynamic Write Power consumption (DWP) is calculated for the time

between asserting WL and when both storage nodes reach 90% of
their nal values. The DWP of 8T-SRAM array with NBL technique,
TGA-SRAM array with BNBL technique, and TGA-SRAM array without
write assist technique are 1.63 fJ, 1.93 fJ, and 1.53 fJ, respectively. The
higher DWP when utilizing the NBL and BNBL write assist techniques
is related to write assist circuit power consumption and higher write
currents. However, it has to be considered that lowering the operating supply voltage due to the use of these write assist techniques will
decrease the DWP. This will be discussed in the next sub-section.

135mV
Supply Voltage (V)

Fig. 12. (a) Write margin, half-column selected HSNM and RSNM vs. supply voltage
(b) 6-worst case vs. supply voltage for 8T-SRAM cell with NBL, TGA-SRAM cell
with BNBL write assist, and without write assist. Note that the negative points on
this gure are averages over 1000 runs that indicate error in 6-worst case of
related parameters.

Considering the fact that the proposed write assist technique

changes the voltage level of the bitlines during write operation,
it has no effect on the cells of unselected columns on the same row
as the selected cell. On the other hand, in the TGA-SRAM memory,
the whole row is written simultaneously (word-wise) in order to
prevent data disturbance. Thus, only the effect of half-selected
cells on the same column as the selected cell (half-column
selected) is important and will be discussed in this section. The
proposed BNBL technique applies a boosted voltage to the highgoing bitline and a negative voltage to the low-going bitline
simultaneously. This can drive the unselected access transistors
of the half-column selected cells to the subthreshold region.
However, it has negligible effect on their HSNM. The HSNM of
the half-column selected cells of TGA-SRAM cell without write
assist is 340.5 mV that is the same as that of 8T-SRAM cell.
Applying the BNBL technique has no signicant effect on the
performance of the cells since it only decreases the HSNM of the
half-column selected cells to 337.2 mV that is still high enough.
4.5. Dynamic power consumption
In this section, the dynamic power consumption during write
operation is calculated for 8T-SRAM array with NBL technique, TGASRAM array with BNBL technique, and TGA-SRAM array without
write assist technique. A 256
32 array is used for all cases. The

Lowering the operating supply voltage helps to lower the total

power consumption (both static and dynamic) of the SRAM array.
In this part of the paper, the improvement in supply voltage
scalability of the proposed design compared with the best existing
technique is explored. The driveability of the access transistors
limits the supply voltage scalability of 8T-SRAM cell. The proposed
BNBL technique improves the strength of the access devices which
allows us to reduce the 272 mV minimum supply voltage to
207 mV. Thus, a 24% supply voltage reduction can be achieved.
In order to nd the minimum supply voltage, both read and write
operations along with hold mode stability have to be considered. A
metric to evaluate the read stability of an SRAM cell is Read Static
Noise Margin (RSNM). It is dened as the length of the side of the
largest square that can t into the lobes of the buttery curve.
Buttery curve is obtained by drawing and mirroring the inverter
characteristics while the read buffer is ON and the read bitline is
precharged to VDD [30]. The hold stability of an SRAM cell is
evaluated using Hold Static Noise Margin (HSNM). The method of
calculating HSNM is similar to RSNM except that the read buffer is
kept off. Isolating the read path from the write path and storage nodes
leads to two signicant advantages in 8T- and TGA-SRAM cells. First,
the read and write features can improve simultaneously. Second, their
RSNM increases as much as their HSNM. As a result, RSNM and HSNM
of standard 8T- and TGA-SRAM cells are the same. However, as
mentioned in the previous section, the BNBL technique can decrease
the half-column selected HSNM. Hence, the half-column selected
HSNM is calculated while applying the BNBL technique.
In order to nd VB and VN in scaled supply voltages, the write
assist circuit is designed in such a way that it produces 1.2VDD
boosted voltage and 0.2 VDD negative voltage. Then, the supply
voltage is reduced from 1 V to 0.2 V and the boosted and negative
voltages are calculated.
Fig. 12 shows the mean value and 6-worst case variation of
WM, half-column selected HSNM and RSNM when the supply
voltage changes from 1 V to 0.2 V for the 8T-SRAM with NBL write
assist, the TGA-SRAM cell without write assist and the TGA-SRAM
with BNBL write assist circuits. As shown in Fig. 12(a), by
decreasing the supply voltage the mean value of the half-column
selected HSNM of TGA-SRAM cell with BNBL technique is expected
to be the rst parameter which reaches zero.
In order to nd the minimum supply voltage for each cell in the
presence of process variations, a Monte Carlo (MC) simulation with
1000 iterations is used for supply voltages 0.5 V, 0.4 V, 0.3 V, and
0.2 V. Then the mean value () and the standard deviation () of the
MC simulation results for each cell are calculated using MATLAB and
tting a Guassian function to them. Finally 6 variations below the
average value (  6) of WM, half-column selected HSNM and RSNM
are calculated as shown in Fig. 12(b). As illustrated in Fig. 12(b),
minimum supply voltage (VDD-min) is determined by WM (6-worst
case of RSNM and half-column selected HSNM reaches 0 at lower
supply voltage compared with 6-worst case of WM). This shows less
dispersion of RSNM and half-column selected HSNM due to process
variation compared to WM. As illustrated in Fig. 12(b), the use of

H. Farkhani et al. / INTEGRATION, the VLSI journal 50 (2015) 1627

10000

1.22

Boosted BL voltage (V)

8T with NBL

Write Time (ps)

TGA
TGA with BNBL

1000

25

100

10

80
1.21

60

1.2

40
20

1.19

500

1000

0
1.188 1.198 1.208 1.218 1.228

Iteration number
1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

-0.18

Supply Voltage (V)

Negative BL voltage (V)

Fig. 13. Write time versus supply voltage for 8T-SRAM cell with NBL, TGA-SRAM
cell with BNBL write assist, and without write assist.

-0.192

80

-0.194

60

60

-0.2

40

-0.21

20

-0.22
-0.23

40

500
Iteration number

-0.198

1000

0
-0.228 -0.218 -0.208 -0.198 -0.188

Negative BL voltage (V)

Fig. 15. The effect of process variation on (a) negative voltage level and (b) boosted
voltage level

20
-0.2
0

500

1000

0
-0.204

Iteration number

Boosted BL voltage (V)

80
-0.19

-0.196

Boosted BL voltage (V)

0.2
Negative BL voltage (V)

-0.2

-0.196 -0.192

Negative BL voltage (V)

1.204

80

1.202

60

1.2

40

1.198

20
1.196
0

500

Iteration number

1000

1.194

1.198

1.202

1.206

Boosted BL voltage (V)

SRAM array without write assist technique has 1.14x lower DWP.
However, considering the signicant leakage power consumption
improvement (1.48
and 2.47
) of TGA-SRAM array with BNBL
technique, it has the minimum total power consumption.
Fig. 13 shows the write time of 8T-SRAM cell with NBL, TGASRAM cell with BNBL and TGA-SRAM cell without write assist
circuit at different supply voltages. The write time of TGA-SRAM cell
with BNBL write assist technique is signicantly shorter than 8TSRAM cell with NBL and TGA-SRAM cell without write assist
technique at all simulated supply voltages (e.g. 2.11
and 4.8

more than 8T with NBL and TGA without write assist at 0.4 V supply
voltage). This is attributed to turned-on strengthened access transmission gate devices in TGA-SRAM cell during whole write cycle.

Fig. 14. The effect of process variation on (a) negative voltage level and (b) boosted
voltage level.

4.7. Process variation effect

TGA-SRAM cell along with BNBL write assist gives the possibility of
scaling down the supply voltage to 207 mV. In other words, the
proposed design gives the possibility of lowering the supply voltage
by 65 mV (24%) and 135 mV (40%) compared to the standard 8TSRAM cell with NBL write assist and TGA-SRAM cell without write
assist circuit, respectively.
The improvement in minimum operating supply voltage leads to
a signicant leakage and dynamic power reduction. The contribution
of leakage in total power consumption of SRAM memories considerably increases with technology scaling [31]. This can be more than
60% of total power consumption for 64 kB SRAM array at 32 nm
technology node [32]. Simulation results shows 1.48
and 2.47

leakage power reduction of 8 kB TGA-SRAM array (256
32) with
BNBL write assist technique at VDD 207 mV compared with the
standard 8T-SRAM cell with NBL write assist at VDD 272 mV and
TGA-SRAM cell without write assist at VDD 342 mV. The DWP of 8TSRAM array with NBL technique, TGA-SRAM array with BNBL
technique, and TGA-SRAM array without write assist technique at
their minimum supply voltages are 0.092 fJ, 0.093 fJ, and 0.081 fJ,
respectively. The DWP of the 8T-SRAM array with NBL technique and
TGA-SRAM array with BNBL technique are sort of equal and the TGA-

In order to see the effect of process variation on write operation for

the TGA-SRAM cell with BNBL write assist technique, a Monte Carlo
(MC) analysis with 1000 iterations at T27 1c is used. Fig. 14(a)
and (b) illustrates the result of process variation on negative voltage
level and boosted voltage level, respectively. The mean value and
standard deviation of boosted voltage level (negative voltage level)
are 1.2 V ( 0.197 V) and 0.508 mV (0.939 mV), respectively. It shows
more variation for negative voltage level. This is due to the fact that
not only mismatches between transistors in write assist circuit affect
negative voltage level but also mismatch between write driver circuit
in replica and write assist circuit affect the time where negative
voltage is applied. Therefore, the negative voltage level shows more
variation than boosted voltage. As it can be seen from Fig. 14, the effect
of process variations on BL voltage levels (71% and72.1% for boosted
and negative voltage, respectively) and WM (0.7% degradation in
worst case) is very small.
Furthermore, the effect of process variation on the proposed
design for an 8 Kb SRAM array is explored. Fig. 15 shows the
negative and boosted voltage variation while considering the
process variation of BLs and write assist circuit. The maximum

26

H. Farkhani et al. / INTEGRATION, the VLSI journal 50 (2015) 1627

and minimum values are  225 mV and 191 mV for negative

voltage level and 1.191 V and 1.217 V for positive voltage level.
[22]

5. Conclusion
[23]

In this paper a new write assist technique was proposed. In

contrast to the existing write assist circuits, the proposed technique improves the write operation by strengthening the access
transistors from both sides (BL and BLB) of the cell. This is
achieved by applying a negative voltage to one bitline while
another bitline is voltage-boosted. The proposed write assist
technique allows SRAM cells to work at lower supply voltages
which leads to a signicant leakage power consumption reduction.
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Hooman Farkhani received the B.Sc. degree in electrical engineering from Kashan University, Kashan, Iran,
in 2004. He received the M.S. and Ph.D degrees in
electrical engineering from Ferdowsi University of
Mashhad, Mashhad, Iran, in 2008 and 2015, respectively. He is a research assistant in Integrated Circuit
Design (ICD) laboratory in Ferdowsi University of
Mashhad. He visited the ICE-LAB, Aarhus University,
Aarhus, Denmark from August 2013 to November 2013
and currently collaborates with ICE-LAB on beyondCMOS circuit and memory design. He is working on
spin-transfer torque random access memory (STTRAM). His other elds of interest are low power and
low voltage SRAM design and ADCs.

Ali Peiravi received the B.S. and the M.S. degrees in

Electrical Engineering from the University of Pittsburgh
(1976) and the University of California at Berkeley
(1978), respectively. He studied for a second M.S.
degree in Electronics Engineering at the California State
University at San Jose (19781979). He received the Ph.
D. degree in Electrical Engineering from the University
of California at Irvine (1984). He served as an RA at the
Electronics Research Laboratory of the University of
California at Berkeley from 1976 to 1978, worked as a
senior design engineer at Intersil, Inc. (Sunnyvale, CA.)
from 1978 to 1980 and at American Microsystems Inc.
(Sunnyvale, CA.) from 1980 to 1981 where he was
responsible for the design and reliability testing of microprocessors, microcontrollers, RAMs, ROMs and EPROMS. He taught at the California State University at
Long Beach, California State University at Pomona and the University of California
at Irvine during the period from 1980 to 1984. He has been a full time faculty
member at the Ferdowsi University of Mashhad since 1984 and is currently a full
time Professor and the director of the Ofce of Professional Authoring. He has (co)
authored more than 100 Journal and Conference papers. His current research
interests are reliability of wireless applications in microgrids, reliable design of
modern power distribution systems, design of modern nano-scale memory
circuits, design of biomedical integrated circuits and systems, and real time control
systems.

H. Farkhani et al. / INTEGRATION, the VLSI journal 50 (2015) 1627

Farshad Moradi (SM'08M'11) Farshad Moradi (S'09

M'11) received the B.Sc. in electrical engineering from
Isfahan University of Technology, Isfahan, Iran, in 2001,
the M.S. degree in electrical engineering from Ferdowsi
University of Mashhad, Iran, in 2005, and his Ph.D.
degree from the University of Oslo, Oslo, Norway, in
2011. From 2009 to 2010, he visited the Nanoelectronic
Laboratory, Purdue University, West Lafayette, IN, USA.
He is currently an Assistant Professor with the Integrated Circuit and Electronics Laboratory, at department of Engineering at Aarhus University, Aarhus,
Denmark. His current research interests include ultralow-power digital/memory circuit/device design. He is
the author/co-author of more than 50 scientic papers. He is the associate editor of
Integration, the VLSI Journal.

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