Vous êtes sur la page 1sur 18

Xilinx XC4000 FPGA Devices

World of ASICs

World of ASICs ASIC (Application Specific Integrated Circuit) Semi-Custom (designed by users) Full-Custom (ordered by

ASIC

World of ASICs ASIC (Application Specific Integrated Circuit) Semi-Custom (designed by users) Full-Custom (ordered by

(Application Specific Integrated Circuit)

World of ASICs ASIC (Application Specific Integrated Circuit) Semi-Custom (designed by users) Full-Custom (ordered by
World of ASICs ASIC (Application Specific Integrated Circuit) Semi-Custom (designed by users) Full-Custom (ordered by

Semi-Custom

(designed by users)

Integrated Circuit) Semi-Custom (designed by users) Full-Custom (ordered by users) User Programmable PLD
Integrated Circuit) Semi-Custom (designed by users) Full-Custom (ordered by users) User Programmable PLD

Full-Custom

(ordered by users)

User

Programmable

users) Full-Custom (ordered by users) User Programmable PLD PAL PLA MAX FPGA MUX Gates TLU (Table
PLD PAL PLA MAX
PLD
PAL
PLA
MAX
FPGA
FPGA

MUX

Gates
Gates

TLU

(Table Look-Up)

by users) User Programmable PLD PAL PLA MAX FPGA MUX Gates TLU (Table Look-Up) ECE 449

Which Way to Go?

Which Way to Go? Custom ASIC s FPGA s Off-the-shelf Low development cost Short time to

Custom ASICs

Which Way to Go? Custom ASIC s FPGA s Off-the-shelf Low development cost Short time to

FPGAs

Off-the-shelf Low development cost Short time to market Reconfigurability
Off-the-shelf
Low development cost
Short time to market
Reconfigurability
High performance Low power Low cost in high volumes
High performance
Low power
Low cost in
high volumes
to market Reconfigurability High performance Low power Low cost in high volumes ECE 449 – Computer
to market Reconfigurability High performance Low power Low cost in high volumes ECE 449 – Computer

Other FPGA Advantages

Other FPGA Advantages • Manufacturing cycle for ASIC is very costly, lengthy and engages lots of
Other FPGA Advantages • Manufacturing cycle for ASIC is very costly, lengthy and engages lots of

Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower

Mistakes not detected at design time have large impact on development time and cost

FPGAs are perfect for rapid prototyping of digital circuits

Easy upgrades like in case of software

Unique applications

reconfigurable computing

What is the FPGA?

What is the FPGA? • FPGA – Field Programmable Gate Array • Originally a large array
What is the FPGA? • FPGA – Field Programmable Gate Array • Originally a large array

FPGA – Field Programmable Gate Array

Originally a large array of gates with programmable interconnections

a large array of gates with programmable interconnections • Now much more complex arrays of various

Now much more complex arrays of various components

Major FPGA Vendors

Major FPGA Vendors • Xilinx, Inc. • Altera Corp. • Lattice Semiconductor • Actel Corp. •
Major FPGA Vendors • Xilinx, Inc. • Altera Corp. • Lattice Semiconductor • Actel Corp. •

Xilinx, Inc.

Altera Corp.

Lattice Semiconductor

Actel Corp.

Agere Systems

Cypress Semiconductor

Atmel

Quick Logic Corp.

• Cypress Semiconductor • Atmel • Quick Logic Corp. Share over 60% of the market ECE

Share over 60% of the market

Xilinx FPGA Families

Xilinx FPGA Families • Mature Products • XC3000, XC4000 , XC5200 • Old 0.5µm, 0.35µm and

Mature Products

Xilinx FPGA Families • Mature Products • XC3000, XC4000 , XC5200 • Old 0.5µm, 0.35µm and

XC3000, XC4000, XC5200

Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs.

Modern Virtex FPGAs

Virtex (0.22µm)

Virtex-E, Virtex-EM (0.18µm)

Virtex-II, Virtex-II PRO (0.13µm)

Low Cost Family

Spartan/XL – derived from XC4000

Spartan-II – derived from Virtex

Spartan-IIE – derived from Virtex-E

XC4000 Family (1)

XC4000 Family (1) • Densities from 3k to 180k gates • System performance beyond 80MHz •
XC4000 Family (1) • Densities from 3k to 180k gates • System performance beyond 80MHz •

Densities from 3k to 180k gates

System performance beyond 80MHz

0.35µm process

PCI compliant (faster grades)

SRAM-based in-system configuration

IEEE 1149.1-compatible boundary scan

Flexible architecture

Abundant flip-flops

Flexible functions generators

Dedicated high-speed carry logic

Wide edge decoders

Internal 3-state bus capability

Low-skew clock networks

Distributed Select-RAM memory

XC4000 Family (2)

Device CLB Array Logic cells LUT Maximum Available Number of Flip-flops Distributed RAM bits I/O
Device
CLB
Array
Logic cells
LUT
Maximum
Available
Number of
Flip-flops
Distributed
RAM bits
I/O
XC4002XL
8x8
128
64
256
2,048
XC4003E
10x10
200
80
360
3,200
XC4005E/XL
14x14
392
112
616
6,272
XC4006E
16x16
512
128
768
8,192
XC4008E
18x18
648
144
936
10,368
XC4010E/XL
20x20
800
160
1,120
12,800
XC4013E/XL
24x24
1,152
192
1,536
18,432
XC4020E/XL
28x28
1,568
224
2,016
25,088
XC4025E
32x32
2,048
256
2,560
32,768

XC4000 Family (3)

XC4000 Family (3) Device CLB Logic cells LUT Maximum Number of Flip-flops Distributed RAM bits Array
XC4000 Family (3) Device CLB Logic cells LUT Maximum Number of Flip-flops Distributed RAM bits Array

Device

CLB

Logic cells LUT

Maximum

Number of Flip-flops

Distributed RAM bits

Array

Available

 

I/O

   

XC4028EX/XL

32x32

2,048

256

2,560

32,768

XC4036EX/XL

36x36

2,592

288

3,168

41,472

XC4044XL

40x40

3,200

320

3,840

51,200

XC4052XL

44x44

3,872

352

4,576

61,952

XC4062XL

48x48

4,608

384

5,376

73,728

XC4085XL

56x56

6,272

448

7,168

100,356

XC4000 Architecture (1)

XC4000 Architecture (1) I / O B lock C onfigurable L ogic B lock ECE 449
XC4000 Architecture (1) I / O B lock C onfigurable L ogic B lock ECE 449

I/O

Block

Configurable

Logic

Block

XC4000 Architecture (2)

XC4000 Architecture (2) • CLBs provide the functional elements for constructing logic • IOBs provide interface
XC4000 Architecture (2) • CLBs provide the functional elements for constructing logic • IOBs provide interface

CLBs provide the functional elements for constructing logic

IOBs provide interface between the package pins and the CLBs

Configurable Logic Block

carry carry up down C1 C4 control DIN G4 A4 SR F D D G3
carry
carry
up
down
C1 C4
control
DIN
G4
A4
SR
F
D
D
G3
A3
LUT
G
FF
ROM
H
Q
YQ
G2
A2
LATCH
RAM
G1
CE
CK
A1
A3
G
D
Y
A2
LUT
H
A1
control
F4
A4
DIN
D
SR
F3
A3
LUT
F
D
ROM
G
F2
A2
CE
FF
RAM
H
Q
XQ
LATCH
F1
A1
CK
H
X
F
CLK

LUT Functionality

LUT Functionality x x x 1 1 1 x x 2 x 3 x 4 x

x

x

x

1

1 1

x

x 2 x 3 x 4

x

2

2

x

x

3 3

x

x

4

4

y

y

y

0 0 0

0001

0001

0001

0 0 0

0

0

0

0

0

0

0010

0010

0010

0011

0011

0011

0100

0100

0100

0101

0101

0101

0110

0110

0110

0111

0111

0111

1000

1000

1000

1001

1001

1001

1010

1010

1010

1011

1011

1011

1100

1100

1100

1101

1101

1101

1110

1110

1110

1111

1111

1111

1

1 1

1

1 1

1

1 1

1 1

1

1

1 1

1

1 1

1

1 1

1

1 1

1

1 1

1

1 1

1

1 1

1

1 1

0

0 0

0

0 0

0

0 0

0 0

0

x x

x 1

1 1

x x

x 2

2 2

LUT LUT
LUT
LUT

y y

x

x 1

x

1 1

x

x 2

x

2

2

x

x 3

x

3 3

x

x 4

x

4

4

x

x

x

1

1 1

x

x

x 2 x 3 x 4

2

2

x

x

3 3

x

x

4

4

y

y

y

0 0 0

0001

0001

0001

0 0 0

0

0

0

0

0

0

0010

0010

0010

0011

0011

0011

0100

0100

0100

0101

0101

0101

0110

0110

0110

0111

0111

0111

1000

1000

1000

1001

1001

1001

1010

1010

1010

1011

1011

1011

1100

1100

1100

1101

1101

1101

1110

1110

1110

1111

1111

1111

0

0 0

1

1 1

0

0 0

0

0 0

0

0 0

1

1 1

0

0 0

1

1 1

0

0 0

1

1 1

0

0 0

0

0 0

1

1 1

1

1 1

0

0 0

0 0

0

y

y

y

0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0

Look-Up tables are

primary elements for

logic implementation

Each LUT can implement any function of 4 inputs

Capacity limited by number of inputs,

not complexity

Can be configured as LUT, ROM or RAM

y

y

y

Input/Output Block

T O FF D LATCH CE CLK Q CK PAD I FF Q LATCH CE
T
O
FF
D
LATCH
CE
CLK
Q
CK
PAD
I
FF
Q
LATCH
CE
CLK
D
delay
CK
CE

IOB Functionality

IOB Functionality • IOB provides interface between the package pins and CLBs • Each IOB can
IOB Functionality • IOB provides interface between the package pins and CLBs • Each IOB can

IOB provides interface between the package pins and CLBs

Each IOB can work as uni- or bi-directional I/O

Outputs can be forced into High Impedance

Inputs and outputs can be registered

advised for high-performance I/O

Inputs can be delayed to achieve 0 ns hold time

Routing Resources

Routing Resources CLB CLB CLB PSM PSM PSM CLB CLB CLB CLB CLB CLB PSM P
Routing Resources CLB CLB CLB PSM PSM PSM CLB CLB CLB CLB CLB CLB PSM P

Routing Resources CLB CLB CLB PSM PSM PSM CLB CLB CLB CLB CLB CLB PSM P

CLB

Routing Resources CLB CLB CLB PSM PSM PSM CLB CLB CLB CLB CLB CLB PSM P

CLB

Routing Resources CLB CLB CLB PSM PSM PSM CLB CLB CLB CLB CLB CLB PSM P

CLB

PSM

PSM

PSM

Routing Resources CLB CLB CLB PSM PSM PSM CLB CLB CLB CLB CLB CLB PSM P

CLB

CLB
CLB

Routing Resources CLB CLB CLB PSM PSM PSM CLB CLB CLB CLB CLB CLB PSM P

CLB

CLB
CLB
CLB
CLB

CLBRouting Resources CLB CLB CLB PSM PSM PSM CLB CLB CLB CLB CLB PSM P rogrammable

PSM

PSM

Programmable

Switch

Matrix

Questions?

Questions? ECE 449 – Computer Design Lab 18
Questions? ECE 449 – Computer Design Lab 18