Outline

Common Source(CS) Configuration

Transfer Characterstics in Common Source(CS)
Configuration

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Recap
Body Effect
CMOS

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Chapter 4

MOS field-Effect
Effect Transistors (MOSFETs)
Figure 4.9

CMOS Transistor

Common Source Amplifier

Two port Network

Biasing to be done
To work at appropriate VGS
and corresponding ID

Common Source Amplifier

V0 = VDD- iDRD

Transconductance
Amplifier
Converted to Voltage
Amplifier

I-V Characterstics of common Source

amplifer
iD

C
B

vGS= vIQ

A
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vDS = vo

I-V Characterstics of common Source

amplifer

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I-V Characterstics of common Source

amplifer
iD

C
B
Load Line
Q

vGS= vIQ
Slope of
Load Line ?
A

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vDS = vo

I-V Characterstics of common Source

amplifer

Y= mx+C

Equation of straight line

Slope of Load line

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I-V Characterstics of common Source

amplifer
iD

C
B

vGS= vIQ

A
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vDS = vo

Transfer Characterstics of common

Source amplifer
v = 5V
DD

Case I

RD = 1K

vGS = 0.6
vt = 0.7

Case II

vGS = 1.2V

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I-V Characterstics of common Source amplifer

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Transfer Characterstics of common Source amplifer

XA :Cut off

AB: Saturation

iD
VDD

VDD =VDSQ

VOB
VOC

BC:Triode
Region

Transfer Characterstics of common Source amplifer

Digital Applications

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I-V
V and Transfer Characterstics

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Operation as Switch

Digital Applications

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Saturation

VDD =VDSQ

VOB

Operation as Linear Amplifier

Saturation

VDD =VDSQ

VOB

VDSQ close to VDD ?

The positive peaks of the output signals might bump into VDD

VDSQ close to Triode region ?

MOS field-Effect
EffectQ
Transistors
(MOSFETs)
Selection
of
point

Chapter 4

Figure E4.27

Slope of Load line

based on RD

Cutoff Region

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Saturation Region

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Saturation Region
Saturation

VDD =VDSQ
VOB

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Saturation Region

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Triode Region

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Triode Region

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Triode Region

We know

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Biasing by Fixing VGS

Selection of R ?
D

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EEE C424/ECE C313

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Chapter 4
MOS field-Effect
Effect Transistors (MOSFETs)
Biasing
by Fixing
VGS
and Connecting
Figure 4.30
Resistance in the source

FIGURE 4.30 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a)
basic arrangement; (b) reduced variability in ID

Practical implementation using single and

two supplies

FIGURE 4.30 (c) practical implementation using a single supply

(e) practical implementation using two

supplies.

Coupling of a Signal Source to the gate

using a capacitor CC1

FIGURE 4.30 (d) coupling of a signal source to the gate using a capacitor CC1

Biasing MOSFET using large drain to gate

feedback resistor RG

Biasing MOSFET using constant current

source

Implementation of constant current source

using Current Mirror