Lecture 3

ECE2072/TRC2300/TEC2172 Digital Systems:
Implementations of two-level logic

(Sec3.2.3 Katz2e)
based on textbook
Contemporary Logic Design, 2nd Edition
by R. H. Katz and G. Borriello
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III - Working with

Combinational Logic
Copyright 2004, Gaetano Borriello and Randy H. Katz
Implementations of two-level logic (Sec3.2.3)
Sum-of-products
AND gates to form product terms (minterms)

OR gate to form sum
Product-of-sums
OR gates to form sum terms (maxterms)

AND gates to form product
III - Working with

Combinational Logic
Two-level logic using NAND and NOR gates
NAND-NAND and NOR-NOR networks
de Morgans law: (A + B) = A B
written differently: A + B = (A B)
(A B) = A + B
(A B) = (A + B)
In other words
OR is the same as NAND with complemented inputs

AND is the same as NOR with complemented inputs
NAND is the same as OR with complemented inputs
NOR is the same as AND with complemented inputs
III - Working with

Combinational Logic
Two-level logic using NAND gates
Replace minterm AND gates with NAND gates

Place compensating inversion at inputs of OR gate
III - Working with

Combinational Logic
Two-level logic using NAND gates (contd)
OR gate with inverted inputs is a NAND gate
de Morgans:
A + B = (A B)
Two-level NAND-NAND network
inverted inputs are not counted

in a typical circuit, inversion is done once and signal distributed
III - Working with

Combinational Logic
Two-level logic using NOR gates
Replace maxterm OR gates with NOR gates

Place compensating inversion at inputs of AND gate
III - Working with

Combinational Logic
Two-level logic using NOR gates (contd)
AND gate with inverted inputs is a NOR gate
de Morgans:
A B = (A + B)
Two-level NOR-NOR network
inverted inputs are not counted

in a typical circuit, inversion is done once and signal distributed
III - Working with

Combinational Logic
Conversion between forms
Convert from networks of ANDs and ORs to networks of

NANDs and NORs
Each introduced "bubble" must be matched by a

corresponding "bubble"
introduce appropriate inversions ("bubbles")
conservation of inversions
do not alter logic function
Example: AND/OR to NAND/NAND

A
C
D
III - Working with
Combinational Logic
C
D
NAND
NAND
NAND
Conversion between forms (contd)
Example: verify equivalence of two forms

A
C
D
C
D
NAND
NAND
NAND
Z = [ (A B) (C D) ]
= [ (A + B) (C + D) ]
= [ (A + B) + (C + D) ]
= (A B) + (C D) 9
III - Working with
Combinational Logic
Example: map AND/OR network to NOR/NOR network

A
B
C
D
A
\A
NOR
\B
NOR
Z
C
D
conserve
"bubbles"
III - Working with
Combinational Logic
NOR
Step 1
NOR
\C
\D
NOR
Step 2
conserve
"bubbles"
10
Example: verify equivalence of two forms

\A
\B
NOR
NOR
\C
\D
NOR
Z = { [ (A + B) + (C + D) ] }
III - Working with

Combinational Logic
={
(A + B) (C + D)
(A + B) + (C + D)
(A B) + (C D) 9
11
Multi-Level Logic: Advantages (Sec3.3 Katz 2e)

Reduced sum of products form:
x=ADF + AEF + BDF + BEF + CDF + CEF + G
A
D
F
A
E
F
B
D
F
B
E
F
C
D
F
C
E
F
6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!)

25 wires (19 literals plus 6 internal wires)
1
A
B
C
D
E
F
G
Factored form:
x = (A D + A E + B D + B E + C D + C E) F + G
= (A (D + E) + B (D + E) + C( D + E) ) F + G
= (A + B + C) (D + E) F + G
III - Working with

Combinational Logic
1 x 3-input OR gate, 2 x 2-input OR gates,

1 x 3-input AND gate
10 wires (7 literals plus 3 internal wires)
12
Multi-Level Logic: Simplification

Multi-Level Optimization:
1. Factor out common sublogic (reduce fan-in, increase gate levels),
subject to timing constraints
2. Map factored form onto library of gates
3. Minimize number of literals (correlates with number of wires)
Factored Form:
sum of products of sum of products . . .
A
B
B
F1
C C
+ F
2
D
E
A
X = (A B + B' C) (C + D (E + A C')) + (D + E)(F G)
F5
+ F
G
D
E
III - Working with

Combinational Logic
F4
+
F3
13
Multi-Level Logic: Simplification contd.

Operations on Factored Forms:
Factoring
Decomposition
Extraction
Substitution
Manipulate network by interactively

issuing the appropriate instructions
There exists no algorithm that guarantees
"optimal" multi-level network will be
obtained
Collapsing
III - Working with

Combinational Logic
14

Factoring: expression in two level form re-expressed in multi-level form
F=AC + AD + BC + BD + E
(9 literals)
can be rewritten as:

(5 literals)
F = (A + B) (C + D) + E
A
C
A
D
A
B
B
C
B
D
C
D
E
Before Factoring
III - Working with

Combinational Logic
After Factoring
15

Decomposition:
Take a single Boolean expression and replace with collection of new
expressions:
F = A B C + A B D + A' C' D' + B' C' D' (12 literals)
F rewritten as:
F = X Y + X' Y'
X=AB
Y=C+D
A
B
C
A
B
D
A
C
D
B
C
D
A
B
F
F
C
D
Before Decomposition
III - Working with
Combinational Logic
(4 literals)
After Decomposition
16

Extraction: common intermediate subfunctions are factored out
F = (A + B) C D + E
G = (A + B) E'
H=CDE
11 literals, 8 gates
can be re-written as:

F=XY + E
G = X E'
H=YE
X=A+B
Y=CD
11 literals, 7 gates
"Kernels": primary divisors
E
A
B
C
D
A
B
C
D
E
Before Extraction
III - Working with
Combinational Logic
A
B
C
D
E
F
G
After Extraction
17

Substitution: function G into function F, express F in terms of G
F=A+BCD
G=A+BC
(4 literals for F)
F rewritten in terms of G:
(3 literals for F)
F = G (A + D)
Collapsing: reverse of substitution; use to eliminate levels to meet

timing constraints
F = G (A + D)
= (A + BC) (A + D)
=A+BCD
III - Working with

Combinational Logic
18

Key to implementing these operations: "division" over Boolean functions
F = PQ + R
divisor
quotient
remainder
example:
X=AC + AD + BC + BD + E
Y=A+B
X "divided" by Y is
X = Y (C + D) + E
Complexity: finding suitable divisors
F=AD + BCD + E
G=A+B
G does not divide F under algebraic division rules
G does divide F under Boolean rules (very large number of these!)
F/G = (A + C) D
F = [G (A + C) D] + E
= (A + B) (A + C) D + E
= (A A + A C + A B + B C) D + E
F written as G Q + R
= (A + B C) D + E
=AD+BCD+E
III - Working with
Combinational Logic
19
Conversion of multi-level logic to NAND gates

(Sec3.4.2 Katz 2e)
F = A (B + C D) + B C
original
AND-OR
network
introduction and
conservation of
bubbles
redrawn in terms
of conventional
NAND gates
III - Working with

Combinational Logic
C
D
Level 1
Level 2
Level 3
Level 4
F
B
A
B
\C
C
D
B
A
B
\C
C
D
\B
A
B
\C
20
Conversion of multi-level logic to NORs

Level 1
F = A (B + C D) + B C
original
AND-OR
network
Level 2
C
D
B
A
B
\C
Level 3
Level 4
F
C
introduction and
conservation of
bubbles
D
B
A
B
\C
redrawn in terms
of conventional
NOR gates
\C
\D
B
\A
\B
C
III - Working with

Combinational Logic
21
Conversion between forms
Example
A
B
C
D
B
C
\D
add double bubbles to

invert all inputs of OR gate
original circuit
B
C
X
X
F
B
C
\X
\D
add double bubbles to
invert output of AND gate
III - Working with

Combinational Logic
insert inverters to eliminate

double bubbles on a wire
22
Summary for multi-level logic
Key design approach
Advantages
Identify common Boolean subexpressions across logic functions

Share subexpressions among multiple functions to reduce literals
circuits may be smaller
gates have smaller fan-in
circuits may be faster
Disadvantages
more difficult to design

tools for optimization are not as good as for two-level
analysis is more complex
III - Working with

Combinational Logic
23
Time behavior of combinational networks

(Sec3.5 Katz2e)
Waveforms
Simulation tools are used to create these waveforms
visualization of values carried on signal wires over time

useful in explaining sequences of events (changes in value)
input to the simulator includes gates and their connections
input stimulus, that is, input signal waveforms
Some terms
gate delay time for change at input to cause change at output
min delay typical/nominal delay max delay

careful designers design for the worst case
rise time time for output to transition from low to high voltage
fall time time for output to transition from high to low voltage
pulse width time that an output stays high or stays low between changes
III - Working with

Combinational Logic
24
Momentary changes in outputs (Sec3.5.2 Katz2e)
Can be useful pulse shaping circuits

Can be a problem incorrect circuit operation
(glitches/hazards)
Example: pulse shaping circuit
A A = 0
delays matter
D remains high for

three gate delays after
A changes from low to high
III - Working with

Combinational Logic
F is not always 0
pulse 3 gate-delays wide
25
Oscillatory behavior (Sec3.5.3 Katz2e)
Another pulse shaping circuit
resistor
A
open
switch
B
C
D
close switch
initially
undefined
III - Working with

Combinational Logic
open switch
26
Hazards & Glitches (Sec3.5.4 Katz2e)

Hazards/Glitches and How to Avoid Them
Unwanting switching at the outputs
Occur because delay paths through the circuit experience
different propagation delays
Danger if logic "makes a decision" while output is unstable
OR hazard output controls an asynchronous input (these
respond immediately to changes rather than waiting for a
synchronizing signal called a clock)
Usual solutions:
wait until signals are stable (by using a clock & SYNCHRONOUS
TIMING METHODOLOGY)
never, never, never use circuits with asynchronous control inputs
design hazard-free circuits
Suggest that first two approaches be used, but we'll tell you about
hazard-free design anyway!
III - Working with
Combinational Logic
27
Hazards & Glitches contd.

Hazards/Glitches and How to Avoid Them
1
1
0
Static
1-hazard
Input change causes output to go from 1 to 0 to 1
Static
0-hazard
Input change causes output to go from 0 to 1 to 0
1
0
0
1
Dynamic
1 hazards
0
Input change causes a double change

from 0 to 1 to 0 to 1 OR
from 1 to 0 to 1 to 0
Kinds of Hazards
III - Working with
Combinational Logic
28
Hazard Detection & Elimination in 2-Level

Networks (Sec3.5.5 Katz2e)
AB
CD
00
Glitch Example (SoP form)

1
A
\C
G1
1
0
\A
D
G3
\A
D
G1
1
0
G2
A
\C
G3
01
01
11
10
1
D
ABCD = 1101
ABCD = 1100
00
G2
10
11
10
input change within product term

B
F = A' D + A C'
1
A
\C
G1
\A
D
1
0
1
A
\C
1
G3
G2
0
ABCD = 1101
F
\A
D
0
G1
1
0
1
0
G3
A
\C
F
G2
0
ABCD = 0101 (A is still 0)
\A
D
0
G1
1
1
0
1
G3
G2
ABCD = 0101 (A is 1)
input change that spans product terms

may cause output to change from 1 to 0 to 1
III - Working with
Combinational Logic
29

Networks contd.
Glitch Example
General Strategy: add redundant terms to cover all singe bit input
transitions
F = A' D + A C' becomes A' D + A C' + C' D
A
AB
00
01
11
10
00
01
CD
D
C
11
10
This eliminates 1-hazard.

0-hazard are not possible with SoP since no product switching
takes place
III - Working with
Combinational Logic
30

Networks contd.
AB
00
CD
Glitch Example
Consider now F in PoS form:
F = (A' + C')(A + D)
01
11
10
00
01
1
D
Glitch present!
C
Add term: (C' + D)
11
10
Note: 1-hazards not possible with

PoS form!
This expression is equivalent

to the hazard-free SoP form of F
III - Working with

Combinational Logic
31
Dynamic Hazards: (Sec3.5.8 Katz2e)

Example with Dynamic Hazard
\A
B
1
G1
01
\B 1 0
\C
1
01
Slow
G2
G3
1 01
10
G5
A 0
\B
10
G4
1 01 0
F
10
V ery slow
Three different paths from B or B' to output

ABC = 000, F = 1 to ABC = 010, F = 0
different delays along the paths:
G1 slow, G4 very slow
Handling dynamic hazards very complex
Beyond our scope
III - Working with
Combinational Logic
32
Implementations Summary
Transition from Simple Gates to more complex gate building blocks
Conversion from AND/OR, OR/AND to NAND/NAND, NOR/NOR
Multi-Level Logic: Reduced gate count, fan-ins, but increased delay
Time Response in Combinational Logic:
Gate Delay, Rise Time, Fall Time
Hazards and Hazard-free Design
III - Working with

Combinational Logic
33
Working with combinational logic summary
Design problems
Realizing two-level logic
filling in truth tables

incompletely specified functions
simplifying two-level logic
NAND and NOR networks
networks of Boolean functions and their time behavior
Time behavior
Later
combinational logic technologies

more design case studies
III - Working with

Combinational Logic
34

Lecture 3

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ECE2072/TRC2300/TEC2172 Digital Systems:

Implementations of two-level logic

III - Working with

Copyright 2004, Gaetano Borriello and Randy H. Katz

Implementations of two-level logic (Sec3.2.3)

AND gates to form product terms (minterms)

OR gates to form sum terms (maxterms)

III - Working with

Copyright 2004, Gaetano Borriello and Randy H. Katz

Two-level logic using NAND and NOR gates

NAND-NAND and NOR-NOR networks

OR is the same as NAND with complemented inputs

III - Working with

Copyright 2004, Gaetano Borriello and Randy H. Katz

Two-level logic using NAND gates

Replace minterm AND gates with NAND gates

III - Working with

Copyright 2004, Gaetano Borriello and Randy H. Katz

Two-level logic using NAND gates (contd)

OR gate with inverted inputs is a NAND gate

Two-level NAND-NAND network

inverted inputs are not counted

III - Working with

Copyright 2004, Gaetano Borriello and Randy H. Katz

Two-level logic using NOR gates

Replace maxterm OR gates with NOR gates

III - Working with

Copyright 2004, Gaetano Borriello and Randy H. Katz

Two-level logic using NOR gates (contd)

AND gate with inverted inputs is a NOR gate

Two-level NOR-NOR network

inverted inputs are not counted

III - Working with

Copyright 2004, Gaetano Borriello and Randy H. Katz

Conversion between forms

Convert from networks of ANDs and ORs to networks of

Each introduced "bubble" must be matched by a

introduce appropriate inversions ("bubbles")

Example: AND/OR to NAND/NAND

Copyright 2004, Gaetano Borriello and Randy H. Katz

Conversion between forms (contd)

Example: verify equivalence of two forms

Copyright 2004, Gaetano Borriello and Randy H. Katz

Conversion between forms (contd)

Example: map AND/OR network to NOR/NOR network

Copyright 2004, Gaetano Borriello and Randy H. Katz

Conversion between forms (contd)

Example: verify equivalence of two forms

III - Working with

Copyright 2004, Gaetano Borriello and Randy H. Katz

Multi-Level Logic: Advantages (Sec3.3 Katz 2e)

6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!)

III - Working with

1 x 3-input OR gate, 2 x 2-input OR gates,

Multi-Level Logic: Simplification

X = (A B + B' C) (C + D (E + A C')) + (D + E)(F G)

III - Working with

Multi-Level Logic: Simplification contd.

Manipulate network by interactively

III - Working with

Copyright 2004, Gaetano Borriello and Randy H. Katz

Multi-Level Logic: Simplification contd.

can be rewritten as:

III - Working with