ECE2072/TRC2300/TEC2172 Digital Systems:

Hardware Description Languages

(Sec3.6 Katz2e)

based on textbook
Contemporary Logic Design, 2nd Edition
by R. H. Katz and G. Borriello
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III - Working with

Combinational Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

Hardware description languages

Describe hardware at varying levels of abstraction

Structural description

Behavioral/functional description

textual replacement for schematic

hierarchical composition of modules from primitives
describe what module does, not how
synthesis generates circuit for module

Simulation semantics

III - Working with

Combinational Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

HDLs

ISP (circa 1977) - research project at CMU

Abel (circa 1983) - developed by Data-I/O

targeted to programmable logic devices

not good for much more than state machines

Verilog (circa 1985) - developed by Gateway (absorbed by Cadence)

simulation, but no synthesis

similar to Pascal and C

delays is only interaction with simulator
fairly efficient and easy to write
IEEE standard

VHDL (circa 1987) - DoD sponsored standard

similar to Ada (emphasis on re-use and maintainability)

simulation semantics visible
very general but verbose
IEEE standard

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Combinational Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

Verilog

Supports structural and behavioral descriptions

Structural

Behavioral

explicit structure of the circuit

e.g., each logic gate instantiated and connected to others
program describes input/output behavior of circuit
many structural implementations could have same behavior
e.g., different implementation of one Boolean function

Well mostly be using behavioral Verilog

rely on schematic when we want structural descriptions

III - Working with

Combinational Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

Example: XOR Gate

Write a structural and behavioral Verilog module for the

following XOR gate:

out

III - Working with

Combinational Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

Structural model

a
out

b
module xor_gate (out, a, b);
input
a, b;
output
out;
wire
abar, bbar, t1, t2;

inverter
inverter
and_gate
and_gate
or_gate

invA (abar, a);

invB (bbar, b);
and1 (t1, a, bbar);
and2 (t2, b, abar);
or1 (out, t1, t2);

endmodule

III - Working with

Combinational Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

Simple behavioral model

always block:

statements between begin-end are

run whenever signal in sensitivity list
changes

module xor_gate
input
output
reg

out
b

(out, a, b);
a, b;
out;
out;

always @(a or b) begin

#6 out = a ^ b;
specifies when block is executed
ie. triggered by which signals
end
endmodule

III - Working with

Combinational Logic

delay from input change

to output change
Copyright 2004, Gaetano Borriello and Randy H. Katz

Simple behavioral model

Continuous assignment statement:

shorthand for always block: executed whenever operands change

module xor_gate
input
output
reg

(out, a, b);
a, b;
out;
out;

simulation register keeps track of

value of signal

assign #6 out = a ^ b;
endmodule

III - Working with

Combinational Logic

delay from input change

to output change

Copyright 2004, Gaetano Borriello and Randy H. Katz

Driving a simulation through a testbench

module testbench (x, y);
output
x, y;
reg [1:0]
cnt;

2-bit vector

initial block executed

initial begin
only once at start
cnt = 0;
of simulation
repeat (4) begin
#10 cnt = cnt + 1;
$display ("@ time=%d, x=%b, y=%b, cnt=%b",
$time, x, y, cnt); end
#10 $finish;
print to a console
end

assign x = cnt[1];
assign y = cnt[0];
endmodule
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Combinational Logic

directive to stop
simulation

Copyright 2004, Gaetano Borriello and Randy H. Katz

Complete simulation

Instantiate stimulus component and device to test in a

schematic

test-bench

III - Working with

Combinational Logic

x
y

Copyright 2004, Gaetano Borriello and Randy H. Katz

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Comparator example

module Compare1 (Equal, Alarger, Blarger, A, B);

input
A, B;
output
Equal, Alarger, Blarger;
assign #5 Equal = (A & B) | (~A & ~B);
assign #3 Alarger = (A & ~B);
assign #3 Blarger = (~A & B);
endmodule

III - Working with

Combinational Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

11

More complex behavioral model

module life
input
output
reg
reg [7:0]
reg [3:0]
reg [3:0]

(n0, n1, n2, n3, n4, n5, n6, n7, self, out);
n0, n1, n2, n3, n4, n5, n6, n7, self;
out;
out;
neighbors;
count;
i;

assign neighbors = {n7, n6, n5, n4, n3, n2, n1, n0};
always @(neighbors or self) begin
count = 0;
for (i = 0; i < 8; i = i+1) count = count + neighbors[i];
out = (count == 3);
out = out | ((self == 1) & (count == 2));
end
endmodule
III - Working with
Combinational Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

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Hardware description languages vs.

programming languages

Program structure

Assignment

continuous assignment (logic always computes)

propagation delay (computation takes time)
timing of signals is important (when does computation have its effect)

Data structures

instantiation of multiple components of the same type

specify interconnections between modules via schematic
hierarchy of modules (only leaves can be HDL in Aldec ActiveHDL)

size explicitly spelled out - no dynamic structures

no pointers

Parallelism

hardware is naturally parallel (must support multiple threads)

assignments can occur in parallel (not just sequentially)

III - Working with

Combinational Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

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Hardware description languages and

combinational logic

Modules - specification of inputs, outputs, bidirectional, and

internal signals
Continuous assignment - a gates output is a function of its
inputs at all times (doesnt need to wait to be "called")
Propagation delay- concept of time and delay in input affecting
gate output
Composition - connecting modules together with wires
Hierarchy - modules encapsulate functional blocks

III - Working with

Combinational Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

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Hardware description languages summary

Provide a way to describe logic circuits texturally and take

advantage of software constructs including variables,
subprocedures, loops and conditional statements
Structural and behavioural description of functions
Parallelism continuous assignment statement
HDL allows designs to be simulated before construction:

Designs are easily modified

Shortens the development/debug cycle

Can be synthesized directly into hardware

III - Working with

Combinational Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

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