Chapter 5 :

Hardware Description
[5.1] Block Diagram
[5.2] Discription
5.2.1 Microcontroller
5.2.2 Android phone
5.2.3 Bluetooth module
5.2.4 LEDs
5.2.5 DC motor
5.2.6 Adaptor (12v)
5.2.7 Db-25 (Parallel port interface)
5.2.8 Transistor (For switching)
5.2.9 Bridge
5.2.10 7805 Ragulator
5.2.11 Power supply

5.1 Block Diagram

Following are the some description of the hardware:

Microcontroller: - Controller is heart of embedded system. We have used 89v51RD2

microcontroller for this project. As in every embedded systems we are having controller

to control or process all the activities and devices. It is connected to power supply,
Buzzer, led lights, motor driver, Motor and socket as well.

Android phone: We can use any android mobile phone but here project we use the
android mobile model is xolo q1010i.we use inbuilt mobile android application.

Bluetooth module: Here we use the hco5 Bluetooth module. It is receive the singal from
android application. it has range up to 10 meter.

Led: Here we use the two led light which are connected with the micro-controller.led
light is operated by the android application.

Dc motor driver: Here the dc motor driver connected with the micro-controller. dc
motor is connected with dc motor driver.dc motor driver operated at 12v.we can also
called as chopper circuit.

Buzzer: it is a notification device. it is also connect with micro-controller.it is activated

and deactivated by the application.

5.2 DESCRIPTION:
5.2.2 MICROCONTROLLER (P89V51RD2):
GENERAL DESCRIPTION:
The microcontroller is the heart of the system. The P89V51RD2 is an 80C51
microcontroller with 64 KB Flash and 1024 bytes of data RAM.
A key feature of the P89V51RD2 is its X2 mode option. The design engineer can choose
to run the application with the conventional 80C51 clock rate (12 clocks per machine cycle) or
select the X2 mode (6 clocks per machine cycle) to achieve twice the throughput at the same
clock frequency.
The Flash program memory supports both parallel programming and in serial In-System
Programming (ISP). Parallel programming mode offers gang-programming at high speed,
reducing programming costs and time to market. ISP allows a device to be reprogrammed in the
end product under software control. The capability to field/update the application firmware
makes a wide range of applications possible. The P89V51RD2 is also In-Application
Programmable (IAP), allowing the Flash program memory to be reconfigured even while the
application is running.

FEATURES:

80C51 Central Processing Unit

V Operating voltage from 0 to 40 MHz

64 KB of on-chip Flash program memory with ISP (In-System Programming) and

IAP (In-Application Programming)

Supports 12-clock (default) or 6-clock mode selection via software or ISP

SPI (Serial Peripheral Interface) and enhanced UART

Four 8-bit I/O ports with three high-current Port 1 pins (16 mA each)

Three 16-bit timers/counters

Programmable Watchdog timer (WDT)

Eight interrupt sources with four priority levels

Second DPTR register

TTL- and CMOS-compatible logic levels

BLOCK DIAGRAM:

Block diagram of P89V51RD2 microcontroller is shown in figure 5.2. This block

diagram is same as that of the 80C51, but some advanced features are included in the
P89V51RD2 which are given above.

PSW
Arithmetic and Logic Unit

SFR
RAM
To Port 1 &
Port 3

B
ROM

PC

DPTR DPH DPL

To Port 0
&
Port 2

Figure 5.2 Block diagram of P89V51RD2 microcontroller

PIN DIAGRAM:

Figure 5.3 Pin diagram of P89V51RD2 microcontroller

PIN DESCRIPTION:
P89V51RD2 is a 40 pin microcontroller as shown in figure 5.3. Each pin has some
specific function. Description of each pin is given below.
Port 0(0.1-0.7) Pins 39-32: Port 0 is an 8-bit open drain bi-directional I/O port. Port 0
pins that have 1 are written to them float, and in this state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to external code
and data memory. In this application, it uses strong internal pull-ups when transitioning to 1s.
Port 0 also receives the code bytes during the external host mode programming, and outputs the
code bytes during the external host mode verification. External pull-ups are required during
program verification or as a general purpose I/O port.

Port 1(1.0-1.7) Pins 1-8: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups.
The Port 1 pins are pulled high by the internal pull-ups when 1s are written to them and can be
used as inputs in this state. As inputs, Port 1 pins that are externally pulled LOW will source
current (IIL) because of the internal pull-ups. P1.5, P1.6, P1.7 have high current drive of 16 mA.
Port 1 also receives the low-order address bytes during the external host mode programming and
verification.
T2: External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2. Pin 1.0.
Port 2(2.0-2.7) Pins 21-28: Port 2 is an 8-bit bi-directional I/O port with internal pullups. Port 2 pins are pulled HIGH by the internal pull-ups when 1s are written to them and can
be used as inputs in this state. As inputs, Port 2 pins that are externally pulled LOW will source
current (IIL) because of the internal pull-ups. Port 2 sends the high-order address byte during
fetches from external program memory and during accesses to external Data Memory that use
16-bit address (MOVX @DPTR). In this application, it uses strong internal pull-ups when
transitioning to 1s. Port 2 also receives some control signals and a partial of high-order address
bits during the external host mode programming and verification.
Port 3(3.0-3.7) Pins 10-17: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 3 pins are pulled HIGH by the internal pull-ups when 1s are written to them and can be
used as inputs in this state. As inputs, Port 3 pins that are externally pulled LOW will source
current (IIL) because of the internal pull-ups. Port 3 also receives some control signals and a
partial of high-order address bits during the external host mode programming and verification.
Signal related to the port 1 are explained below.

RXD: serial input port

TXD: serial output port

INT0: external interrupt 0 input

INT1: external interrupt 1 input

T0

:external count input to Timer/Counter 0

T1

:external count input to Timer/Counter 1

WR :external data memory write strobe

RD

:external data memory read strobe

PSEN (Program Store Enable) Active Low Pin 29: PSEN is the read strobe for
external program memory. When the device is executing from internal program memory, PSEN
is inactive (HIGH). When the device is executing code from external program memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped during each
access to external data memory. A forced HIGH-to-LOW input transition on the PSEN pin while
the RST input is continually held HIGH for more than 10 machine cycles will cause the device to
enter external host mode programming.
Reset Pin 9: While the oscillator is running, a HIGH logic state on this pin for two
machine cycles will reset the device. If the PSEN pin is driven by a HIGH-to-LOW input
transition while the RST input pin is held HIGH, the device will enter the external host mode;
otherwise the device will enter the normal operation mode.
EA (External Access Enable) Active Low Pin 31: EA must be connected to VSS in
order to enable the device to fetch code from the external program memory. EA must be strapped
to VDD for internal program execution. However, Security lock level 4 will disable EA, and
program execution is only possible from internal program memory. The EA pin can tolerate a
high voltage of 12 V.
ALE (Address Latch Enable) Pin 30: ALE is the output signal for latching the low byte
of the address during an access to external memory.
Crystal 1 Pin 19: Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
Crystal 2 Pin 18: Output from the inverting oscillator amplifier.

Power Supply VDD Pin 40: It is connected to +5V power supply.

Ground Pin 20: It is connected to ground.

MEMORY ORGANIZATION:
The device has separate address spaces for program and data memory.

Flash program memory:

There are two internal flash memory blocks in the device. Block 0 has 64 Kbytes and
contains the users code. Block 1 contains the Philips-provided ISP/IAP routines and may be
enabled such that it overlays the first 8 Kbytes of the user code memory. The 64 KB Block 0 is
organized as 512 sectors; each sector consists of 128 bytes. Access to the IAP routines may be
enabled by clearing the BSEL bit in the FCF register. However, caution must be taken when
dynamically changing the BSEL bit. Since this will cause different physical memory to be
mapped to the logical program address space, the user must avoid clearing the BSEL bit when
executing user code within the address range 0000H to 1FFFH.

Data RAM memory:

The data RAM has 1024 bytes of internal memory. The device can also address up to 64
KB for external data memory.
The device has four sections of internal data memory:
1. The lower 128 bytes of RAM (00H to 7FH) are directly and indirectly addressable.
2. The higher 128 bytes of RAM (80H to FFH) are indirectly addressable.
3. The special function registers (80H to FFH) are directly addressable only.
4. The expanded RAM of 768 bytes (00H to 2FFH) is indirectly addressable by the move
external instruction (MOVX).

Dual data pointers:

The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1
Determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is selected; when
DPS = 1, DPTR1 is selected. Quickly switching between the two data pointers can be
accomplished by a single INC instruction on AUXR1 as shown below in figure 5.4.

Figure 5.4 Data pointer

TIMERS/COUNTERS 0 AND 1:

The two 16-bit Timer/Counter registers: Timer 0 and Timer 1 can be configured to
operate either as timers or event counters in the Timer function, the register is incremented
every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine
cycle consists of six oscillator periods, the count rate is 1/6 of the oscillator frequency. In the
Counter function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled once
every machine cycle.
The Timer or Counter function is selected by control bits C/T in the Special Function
Register TMOD. These two Timer/Counters have four operating modes, which are selected by
bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3
is different. The four operating modes are described in the following text.

TMOD Register:

Table 5.1

TCON Register:

Table 5.2

Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a fixed divide-by-32 prescaler. Figure 5.5 shows Mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the Timer
when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE =1 allows the Timer to be
controlled by external input INTn, to facilitate pulse width measurements). TRn is a control bit in
the Special Function Register TCON. The GATE bit is in the TMOD register.

Figure 5.5 Timer modes 0

The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of
TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the
registers. Mode 0 operations are the same for Timer 0 and Timer 1 as shown in figure 4.7.

Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn)
are used. See figure 5.6.

Figure 5.6 Timer modes 1

Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reloads,
as shown in figure 5.7. Overflow from TLn not only sets TFn, but also reloads TLn with the
contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2
operation is the same for Timer 0 and Timer 1.

Figure 5.7 Timer modes 2

Mode 3

When timer 1 is in Mode 3 it is stopped (holds its count). The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic
for Mode 3 and Timer 0 is shown in figure 5.8. TL0 uses the Timer 0 control bits: T0C/T,
T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles)
and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1
interrupt. Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in
Mode 3, the P89V51RD2 can look like it has an additional Timer.

Figure 5.8 Timer modes 3

Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out
of its own Mode 3. It can still be used by the serial port as a baud rate generator, or in any
application not requiring an interrupt.

RESET:
A system reset initializes the MCU and begins program execution at program memory
location 0000H. The reset input for the device is the RST pin. In order to reset the device, a logic
level high must be applied to the RST pin for at least two machine cycles (24 clocks), after the
oscillator becomes stable. ALE, PSEN are weakly pulled high during reset. During reset, ALE
and PSEN output a high level in order to perform a proper reset. This level must not be affected
by external element. A system reset will not affect the 1 Kbytes of on-chip RAM while the
device is running; however, the contents of the on-chip RAM during power up are indeterminate.

Power-on Reset:

At initial power up, the port pins will be in a random state until the oscillator has started
and the internal reset algorithm has weakly pulled all pins HIGH. Powering up the device
without a valid reset could cause the MCU to start executing instructions from an indeterminate
location. Such undefined states may inadvertently corrupt the code in the flash.
When power is applied to the device, the RST pin must be held HIGH long enough for
the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to
two machine cycles for a valid power-on reset. An example of a method to extend the RST signal
is to implement a RC circuit by connecting the RST pin VDD through a 10 mF capacitor and to
VSS through an 8.2 kW resistor as shown in figure 5.9
.

Figure 5.9 Power on reset

Note that if an RC circuit is being used, provisions should be made to ensure the VDD
rise time does not exceed 1 millisecond and the oscillator start-up time does not exceed 10
milliseconds.

Software reset
The software reset is executed by changing FCF[1] (SWR) from 0 to 1. A software

reset will reset the program counter to address 0000H. All SFR registers will be set to their reset
values, except FCF[1] (SWR), WDTC[2] (WDTS), and RAM data will not be altered.

 SECURITY BIT:
The Security Bit protects against software piracy and prevents the contents of the flash
from being read by unauthorized parties in Parallel Programmer Mode. It also protects against
code corruption resulting from accidental erasing and programming to the internal flash memory.
5.2.2 Bluetooth Module:

SPP Bluetooth Modules

These small size Bluetooth TTL transceiver modules are designed for serial communication (SPP
- serial port profile). It allows your target device to both send or receive TTL data via Bluetooth
technology without connecting a serial cable to your computer.
The modules with the HC-03 and HC-05 firmware are the Master and Slave integrated
Bluetooth serial modules with firmware which allows you to modify master and slave mode at
any time. HC-03 are industrial grade products, HC-05 are commercial grade products.
The modules with the HC-04 and HC-06 firmware are the modules which are factory set to be
Master or Slave modules. Master and slave mode cannot be switched from the factory setting.
HC-04 is an industrial grade product, HC-06 is a commercial grade product.
The hardware

HC-05, HC-06 Hardware

The hardware for all firmware versions of the HC-05 and HC-06 modules is the same and the
firmware may be freely changed with the right tools. All the modules look like this:

Hardware details:

Built-in CSR company Bluetooth chip BC417143

Bluetooth Technology v2.0 + EDR

TTL data transparent transfer between a host Bluetooth device

Compatible with all Bluetooth adapters that support SPP

Coverage up to 30 ft / 10 m

Built in antenna

Power input: +3.3VDC (bluetooth module)

Can set the module control parameters and control commands via AT commands

The maximum serial baud rate: 1382400 bps, support for hardware flow control transfer

Provide seven input and output ports

Connection/non-connection status indicators

HC-07 Hardware
HC-07 modules are replacements for the HC-06 using different hardware chips. The HC-07 uses
a CSR 41C6 chip with internal 8 Mbit flash. There is no external 8Mbit flash chip.

HC-08 Hardware
The HC-08 module firmware working voltage is 2V-3.6V. The range of this module is 8 to 10m.
The module is an ultra low power Bluetooth protocol v4.0 module which cane operate as either
a master or a slave device.
HC-08 Current Consumption
When module is

paired with an adapter

paired with the adapter connecting and
sending data
not paired with the adapter

Master current

Slave current

consumption

consumption

8.9mA

8.9mA

9.3mA

9.3mA

20.2mA

8.9mA

Note: absolute maximum voltage is 3V6 DC.

HC-09 Hardware
The HC-09 modules are replacements for the HC-06 and HC-07 modules.
HC-09 Current Consumption
When module is

Current consumption

paired with an adapter

25mA

paired with the adapter connecting and sending data

27mA

not paired with the adapter

15mA

Note: absolute maximum voltage is 3V6 DC.

Important Hardware Notes

The voltage to be applied to these modules is from a minimum of 3.1VDC to a maximum of

4.2VDC for HC-05/HC-06 and a maximum of 3.6VDC for HC-09. Do not connect 5VDC or
more unless you are using the module mounted on a board which includes some sort of voltage
regulation.

The serial output is at TTL voltage levels (3.3V to 5V) and not the higher RS232 voltage levels
(12V+). Do not connect the module directly to your computer serial port unless the module is
mounted on a board that is doing TTL to RS232 conversion. You can also use a TTL to RS232
adapter to connect the module to your computer serial port. You do not need to use any
conversion if you are connecting the module to your microcontroller serial port which has 5VDC
tolerant pins.

Module Pin Outs

HC-05 module pin out

The Firmware

The hardware for all firmware versions is the same and the firmware may be freely changed with
the right tools.

HC-05 firmware versions

HC-05 firmware has default settings for the serial port of 38400, N, 8,1; password: 1234.
Supports the AT command to modify the baud rate, device name, password, and set master or
slave mode.
HC-05 Pin definition

Pin 1 (UART TX - weak internal pull-up) UART data output

Pin 2 (UART RX - weak internal pull-down) UART data input

Pin 12 (VCC) 3.3V

Pin 13, 21, 22 (VSS) Ground

Pin 31 (PIO8) connects LED cathode via a 470 ohm series resistor to ground. It is used to indicate
the module state. After power on, flashing intervals differ in different states.

Pin 32 (PIO9) is used to control LED indicating pairing. It will be steady on when pairing is
successful.

Pin 34 (PIO11), module state switching pin. HIGH -> responds to AT commands via the wired
TTL serial connection; LOW or floating -> regular work status.

Built-in reset circuit, reset is completed automatically after power on.

Steps to set HC-05 to MASTER

Set PIO11 HIGH with a 10K resistor in between.

Power on, module comes into AT Command Response Status.

Open Hyperterminal or other communications tool, set the baud rate to 38400, 8 data bits, 1 stop
bit, no parity bit, no flow control (or 9600; firmware dependent).

Via TTL serial port, send characters "AT + ROLE = 1 r n",if successful, return "OK r n", where r
n is carriage return.

Set PIO11 LOW, re-power, then in Master state, automatically search for slave module and
connect.

HC-05 AT commands

AT responds OK.

AT+RESET responds OK.

AT+VERSION? responds with the firmware version.

AT+ORGL responds OK and restores default state.

AT+ADDR? responds with module address.

AT+NAME? responds with module name.

AT+NAMEname where name 20 or fewer characters. Responds OKname. Retained across power
offs.

AT+RNAME? responds with remote paired module's name.

AT+ROLE? responds with 0=slave, 1=master, 2=slave-loop (loopback: receives master device
data and sends back to master).

AT+CLASS? responds with device type (32 bit indicating device type and what is supported).

AT+PSWD? responds with password.

AT+PSWD=password sets module pairing password to password.

AT+UART=x, y, z where x is 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800,
921600, 1382400 for baud rate, where y is 0=1 bit, 1=2 bits stop bit, where z is 0=none, 1=odd,
2=even parity). Deafult is 9600,0,0.

AT+UART? responds with +UART:baud,stop bits,parity.

AT+STATUS? responds with the module status (+STATE:initialised, ready, pairable, paired,
inquiring, connecting, connected, disconnected).

AT+PAIR=x,y sets the remote Bluetooth device address with which to pair where x is the address
(eg 12:34:56:ab:cd:ef) and y is the limited time of the connection in seconds.

HC-06/Linvor v1.4/v1.5 firmware versions

HC-06 firmware has default settings for the serial port of 9600, N, 8,1; password: 1234. HC-06
firmware is almost always hardcoded to be a slave device, but it is also possible to be hardcoded
as a master device.

5.2.3

Motor driver:

L293D is a dual H-bridge motor driver integrated circuit (IC). Motor drivers act as current
amplifiers since they take a low-current control signal and provide a higher-current signal. This
higher

current

signal

is

used

to

drive

the

motors.

L293D contains two inbuilt H-bridge driver circuits. In its common mode of operation, two DC
motors can be driven simultaneously, both in forward and reverse direction. The motor
operations of two motors can be controlled by input logic at pins 2 & 7 and 10 & 15. Input logic
00 or 11 will stop the corresponding motor. Logic 01 and 10 will rotate it in clockwise and
anticlockwise

directions,

respectively.

Enable pins 1 and 9 (corresponding to the two motors) must be high for motors to start operating.
When an enable input is high, the associated driver gets enabled. As a result, the outputs become
active and work in phase with their inputs. Similarly, when the enable input is low, that driver is
disabled, and their outputs are off and in the high-impedance state

Pin Description:
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Function
Enable pin for Motor 1; active high
Input 1 for Motor 1
Output 1 for Motor 1
Ground (0V)
Ground (0V)
Output 2 for Motor 1
Input 2 for Motor 1
Supply voltage for Motors; 9-12V (up to 36V)
Enable pin for Motor 2; active high
Input 1 for Motor 1
Output 1 for Motor 1
Ground (0V)
Ground (0V)
Output 2 for Motor 1
Input2 for Motor 1
Supply voltage; 5V (up to 36V)

Name
Enable 1,2
Input 1
Output 1
Ground
Ground
Output 2
Input 2
Vcc 2
Enable 3,4
Input 3
Output 3
Ground
Ground
Output 4
Input 4
Vcc 1