8/27/2015

Every Design Uses Memory

Fast on-chip
memory

On-chip block RAM and ROM

Frequently used for
Finite State Machines
FIFO

Spartan-6

Large/local data storage

External memory for larger data storage

Dedicated Memory Controller Block (MCB)

External
memory

Supports evolving controller standards

Spartan-6 Memory Resources

Basic FPGA Architecture

All memory solutions

Must be fast and flexible
Bitstream can pre-loaded with fixed data for a
ROM or RAM

Xilinx Training

After completing this module you will be able to

Memory Options

Distributed
RAM/SRL32

Fully utilize the Spartan-6 distributed and block memory

resources
LOGIC

On-chip Block RAM

RAM / SRL 32

Objectives

Very granular, localized memory

Minimal impact on logic routing
Great for small FIFOs

Granularity

DRAM
SDRAM
DDR
DDR3
FCRAM
SRAM RLDRAM
SRAM
Sync SRAM
FLASH DDR SRAM
ZBT
QDR
EEPROM FLASH
EEPROM
DRAM

BRAM

Understand the features and limitations of the Spartan-6

dedicated memory controller block (MCB)
Use the Memory Interface Generator (MIG) to build your
custom memory controller and design an appropriate interface
to your off-chip memory component

Fast Memory
Interfaces

Efficient, on-chip blocks

Ideal for mid-sized buffering

Spartan-6

Cost-effective bulk storage

Various memory controller cores
For large memory requirements
Memory Controller Block

Capacity

8/27/2015

Interfacing to External Memories

Distributed RAM Features

MCB supports many standards

Distributed LUT memory

1.5 V to 2.5 V

Can be loaded by configuration

Single or double data rate

Synchronous (clocked) write operation

Different protocols

But asynchronous (combinatorial) read

Spartan-6

Can make synchronous read when you

use the neighboring flip-flop

High performance

Slice3
Logic

Slice3

Slice3
Logic RAM
Shift Register

Slice3

Slice3
Logic

Slice3

Logic

Logic

Slice3
Logic

Logic RAM
Shift Register

Slice3
Logic RAM
Shift Register

Logic

Slice3
Logic

Slice3

R
A
M

Logic RAM
Shift Register

R
A
M

Slice3
Logic RAM
Shift Register

Slice3
Logic RAM
Shift Register

R
A
M

Easiest to build with the Core Generator

With advanced ChipSync technology

Automatically builds the necessary input

This is the Select I/O functionality that

enables the FPGA to be directly connected
to memory specific I/O standards

decode and output multiplexer logic

Memories can be initialized

Text I/O code in VHDL
Coefficient file
Or an initialization file placed in HDL code if inferring the memory

Distributed RAM

Block RAM Features

Multiple configuration options

Distributed LUT memory

True dual-port, simple dual-port, single-port

64-bit blocks throughout the FPGA

available in 25% of the slices

Slice3
Logic

Logic RAM
Shift Register

Single-port, dual-port, multi-port

Slice3

Slice3

Can be used as 32-bit shift register

Very fast (sub-nanosecond)

Ideal for small and fast memories

Coefficient storage
Small data buffers
Small state machines
Small FIFOs
Shift registers

Slice3

Logic

Logic RAM
Shift Register

Slice3

Slice3

Logic

Logic RAM
Shift Register

Slice3
Logic

Slice3

Slice3

R
A
M

Slice3

Logic

Logic RAM
Shift Register

Slice3

Slice3

Logic

R
A
M

Logic RAM
Shift Register

Logic RAM
Shift Register

R
A
M

18Kb Memory

Two independent ports address common data

Individual address, clock, write enable, clock enable
Independent widths for each port

300-MHz operation when using data pipeline option

Dual-Port
BRAM

All operations are synchronous; all outputs are latched

Data output has an optional internal pipeline register
Faster clock rate, but increased latency

Byte-write enable
Enhances processor memory interfacing

Load block RAM during configuration

Reset during operation clears the registers, not the data content

Do not violate address setup time while enabled

Disable memory when address timing might be unpredictable
This also saves power

8/27/2015

Spartan-6 FPGA Block RAM Block

Simple Dual-Port Block RAM

Addr A

One read port and one write port

Each block RAM block can be used as

Port A

36

Natural structure for FIFOs

Wdata A

Allows widest implementation

18 Kb
Block
RAM

18 Kb
Memory
Array

72-bit data width on 18K block RAM

9 Kb
Block RAM

Up to a 72-bit read and write in one cycle

Addr B

36

36-bit data width for 9K block RAM

or

36

Rdata A

Wdata B

Port B

36

Rdata B

Doubles the memory bandwidth per block

9 Kb
Block RAM

Parity bits are not dedicated for parity

All byte-wide data has an extra ninth storage bit
Can be used for parity or for any other purpose

One 18 Kb Block RAM

Parity generation / checking would need LUT

logic

Two independent 9 Kb block RAMs

True Dual-Port Block RAM

Block RAM Configurations

True dual-port flexibility

Can perform read and write operations
simultaneously and independently on port A and
port B
Each port has its own clock, enable, and write enable
Every write also performs a read operation

Port A

36
Wdata A

18 K

True dual-port

8Kx1, 4Kx2, 2Kx4,

1Kx9, 512x18

16Kx1, 8Kx2,
4Kx4, 2Kx9,
1Kx18, 512x36

Two fully independent

read and write operations

Simple dual-port

8Kx1, 4Kx2, 2Kx4,

1Kx9, 512x18,
256x36

16Kx1, 8Kx2,
4Kx4, 2Kx9,
1Kx18, 512x36,
256x72

1 read & 1 write port

Read AND write in 1 cycle

Single-port

8Kx1, 4Kx2, 2Kx4,

1Kx9, 512x18,
256x36

16Kx1, 8Kx2,
4Kx4, 2Kx9,
1Kx18, 512x36,
256x72

1 read & 1 write port

Read OR write in 1 cycle

36

Rdata A

18 Kb
Memory
Array

Read before write, write before read, or no output

change

Simultaneous read + write or write + write

to the same location can cause data corruption

Each 9 K
Addr A

Addr B

36
Wdata B

Port B
Rdata B

36

Make sure that the address and control signals are stable
during operation

Block RAM configurations

One block RAM: 16Kx1, 8Kx2, 4Kx4, 2Kx9, 1Kx18, 512x36
Or two independent 9K block RAMs: 8Kx1, 4Kx2, 2Kx4, 1Kx9, 512x18
Each port can have its own depth x width within that range

8/27/2015

Byte-Wide Write Enable

Memory Controller Block (MCB)

Spartan-6 has a New dedicated memory

controller block

Controls which byte is being written

One write enable for each byte of data and its parity bit
Useful when interfacing with processors

clk
address
data

memory @a0

Bytes not being written will show

an undefined value on the
output
The output truly reflects the new
memory content
Writing always implies a read

ABCD

we[3:0]

1001

AFFD

FFFF

output

Be careful of reading when

writing

AFFD

DDR
DDR2
DDR3
LP DDR

Why a hard block?

Byte-write operation
during write-first mode

a0

MCB
Blk

Up to four controllers per device

Saves between 500 and 2000 LUTs and
registers versus a soft implementation

Spartan-6 FPGA Memory Capacity

Very common design component

Benefits of a hard block
Higher performance: 800 Mbps
Lower cost: smaller than soft logic
Lower power: compared to soft logic

Easy to design
Abstracts away complexity of memory interfacing
CORE Generator tool / MIG wizard and EDK
support

Interface

Spartan-6
FPGA

DDR3 SDRAM

800 Mbps*

DDR2 SDRAM

800 Mbps*

DDR SDRAM

400 Mbps*

LP DDR

400 Mbps*

*For all speed grades, except -1L

MCB Features
Memory support

XC6SLX4

Distr. RAM (Kb)

Block RAM (Kb)

18-Kb Block RAM Blocks

32

144

XC6SLX9

90

576

32

XC6SLX16

136

576

32

XC6SLX25

229

936

52

XC6SLX45

401

2,088

116

XC6SLX100

930

4,824

268

XC6SLX150

1,355

4,824

268

XC6SLX25T

229

936

52

XC6SLX45T

401

2,088

116

XC6SLX100T

930

4,824

268

XC6SLX150T

1,355

4,824

268

DDR, DDR2, DDR3, LP DDR

standards

Simple, multi-port user interface

Six 32-bit wide user ports
Can be concatenated up to 128 bits
Each port has 64-deep data FIFO and
4-deep command FIFO

Simple but also programmable

Controller options
Set user interface, calibration,
addressing, and arbitration schemes

Memory device options

Control features and timing
parameters

Automatic calibration
DQS centering
DQ per-bit de-skew
FPGA on-chip input termination

Memory Controller Block

CMD FIFO
CMD FIFO
CMD FIFO
CMD FIFO
CMD FIFO
CMD FIFO

0
1
2
3
4
5

Arbiter Controller

32-bit
Bi-directional

32-bit
Bi-directional

32-bit
Uni-directional

Data Path

Dedicated Routing

Spartan-6 Device

PHY

32-bit
Uni-directional

32-bit
Uni-directional

32-bit
Uni-directional

8/27/2015

MCB Options

Block Diagram

Number of memory controllers

Spartan-6 FPGA

User Interface

I/O interface to a single external DRAM device: 4, 8, or 16 bits wide

Internal user interface bus width is programmable: 32 to 128 bits
wide
bus LP DDR
DRAM size DRAM
width
x16
x8
128Mb
x4
x16
x8
256Mb
x4
x16
512Mb
x8
x4
x16
x8
1Gb
x4
x16
2Gb
x8
x4
4Gb
x16

DDR

DDR2

DDR3

M
C
B
3

M
C
B
3

M
C
LX16 B
1

M
C
B
4
M
C
B
3

p0_cmd_clk
p0_cmd_en
p0_cmd_bl
p0_cmd_instr
p0_cmd_addr

M
C
B
5
LX100/T

M
C
B
1

CMD FIFO 0
CMD FIFO 1
CMD FIFO 2
CMD FIFO 3
CMD FIFO 4
CMD FIFO 5

Off-Chip Memory
Arbiter

Controller

p0_rd_clk
p0_rd_en

M
C
B
1

LX25/T

Spartan-6 FPGA Memory Controller Block

p0_cmd_full
p0_cmd_empty

M
M
C
C
B LX9 B
3
1

LX4

Calibration Module (RTL)

IP Wrapper

I/O Clock Network

2 for medium-sized devices, 4 for the two largest devices

M
C
B
3

M
C
B
1

LX45/T

M
C
B
4
M
C
B
3

Bi -directional

32-bit
Bi -directional

32-bit
Uni -directional

p0_wr_clk
p0_wr_en
p0_wr_data
p0_wr_mask

M
C
B
5
LX150/T

32-bit

p0_rd_data
p0_rd_empty
p0_rd_full
p0_rd_overflow
p0_rd_count
p0_rd_error

P
H
Y

I
O
B

mcbx_dram_clk
mcbx_dram_clk_n
mcbx_dram_cke
mcbx_dram_ras_n
mcbx_dram_cas_n
mcbx_dram_we_n
mcbx_dram_odt
mcbx_dram_ddr3_rst
mcbx_dram_ba
mcbx_dram_addr
mcbx_dram_dq
mcbx_dram_dqs
mcbx_dram_dqs_n
mcbx_dram_udm
mcbx_dram_ldm

Uni -directional

32-bit

p0_wr_empty
p0_wr_full
p0_wr_underrun
p0_wr_count
p0_wr_error

M
C
B
1

Data Path

32-bit

Dedicated Routing

Uni- directional

32-bit
Uni -directional

Simple user interface abstracts away complexity

MIG / EDK wrapper delivers complete interface solution
Internal block assembly and signal connectivity is transparent to the user

MCB Performance

Design Considerations
PLL creates two phases of MCB
system clock

DDR
DDR2
DDR3
LPDDR

Max Theoretical Bandwidth

per Memory Controller Interface

Data Rate
Min
TBD *
TBD *
TBD *
TBD *

Max
400 Mbps
(200 MHz)

800 Mbps
(400 MHz)

800 Mbps
(400 MHz)

400 Mbps
(200 MHz)

4-bit

8-bit

16-bit

1.6 Gbps

3.2 Gbps

6.4 Gbps

3.2 Gbps

6.4 Gbps

12.8 Gbps

SYSCLK_2X & SYSCLK_2X_180

Operate at 2X memory clock frequency
Used for DDR I/O
Divide by 2 in MCB creates memory
clock frequency for other logic (1X
clocks)
Place MCBs on same side of device must
share system clocks = same data rate

MCB Block
User
Interface
User
Clks

Controller
Arbiter
Data Path

IOB

Memory
Type

PHY Layer

Memory
Interface

1X Clks

2 :2

PLL
3.2 Gbps

6.4 Gbps

12.8 Gbps

CLK

CLK
IN

CLKB

1.6 Gbps

3.2 Gbps

6.4 Gbps

Higher data rates than with soft-core implementations

Data rates up to 800 Mbps (DDR2, DDR3)
Maximum theoretical bandwidth up to 12.8 Gbps
Max values are for all speed grades in standard voltage devices

IBUFDS

FB

CLK
SYSCLK_2X
OUT0

2X Clks

CLK
SYSCLK_2X_180
OUT1
BUFPLL_MCB

User interface clocks

Port clocks for command, write, and read path
Asynchronous to system clocks
FIFOs handle clock domain transfer

Clock Example:
DDR2 800 Mbps
2X clk = 800 MHz
1X clk = 400 MHz

IO Clock Network

2nd MCB Block

On the same side of device
(Only in larger parts)

8/27/2015

Design Considerations

I/O pins for MCBs are predefined

But are general-purpose I/O when a particular MCB is not used

Two MCB Design Flows

For ISE tool design flow

Memory Interface Generator (MIG) wizard within the CORE Generator tool
Best for non-embedded applications

Package selection determines access to MCBs

Higher pin count packages have more MCB blocks bonded out

Migration across devices within same package

Simple GUI-driven tool for configuring MCB block

Supports all MCB memory standards (DDR3, DDR2, DDR, LPDDR)

For EDK design flow

Up or down one device density in most cases

Multi Port Memory Controller (MPMC)

Applies only within a device family (LX or LXT, for example)

Best for Embedded applications

MCB block is underlying hardware implementation of the MPMC peripheral

The left and lower left MCB has the best migration path
MCB pins shared less with other functions compared to right side

Design Considerations

MCB blocks can be connected in parallel to create wider

interfaces
This will require extra CLB logic

MCB blocks interface to a SINGLE memory device (x4, x8,

or x16)
There is No support for two x8 MC interfacing to a x16 memory

Simple GUI-driven tool within EDK / XPS

Supports all MCB memory standards (DDR3, DDR2, DDR, LPDDR)

Memory Interface Generator (MIG)

Easy to customize your memory controller and interface design

Memory architecture, data rate, bus width
CAS latency, burst length
I/O bank assignments
Generates RTL source code and UCF from hardware-verified IP
Delivered as part of the ISE software (CORE Generator utility)
MCB supports DDR, DDR2, DDR3, and LPDDR

Even for LPDDR, use an external VREF supply in the bank

Supports soft calibration module input termination tuning

Use a PLL nearest the center of the device to drive the

BUFPLL_MCB

Soft Memory Controller supports other additional memory

interfaces

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MIG Design Flow

MIG Output Files

Open CORE Generator

Run MIG, choose your memory

parameters and generate rtl and ucf files

Integrate MIG .ucf constraints to

overall design constraints file
Import RTL and build options into
ISE project

UCF file folder

Pinout and clocking constraints
Batch file (ise_flow.bat) with
recommended build options

RTL file folder

Customize MIG design
Integrate/customize MIG memory RTL
testbench

Perform functional simulation

Synthesize design
Place and route design
Timing simulation
Verify in hardware

Functional modules (physical layer, user

interface, controller, testbench)
Unencrypted for ease of customization

Simulation file folder

HDL simulation files including memory
device models Synthesis files folder

Optional RTL customization

MIG

Summary
Enables you to customize your
memory controller
Some options are specific to the
memory controller standard
(such as DDR2 and DDR3)

Options for the physical layer and

the FPGA controller
Debug signals
IOB options for power or speed

MIG bank selection options

Displays pins required
Restricted I/O columns are
disabled

Distributed LUT
RAM

Distributed LUT RAM

Fast, localized memories
Great for small FIFOs

Block RAM
Bigger on-chip memories

High-Performance
Block RAM

Great for mid-sized buffering

FPGA

Dedicated Memory Controller (MCB)

Fast connection to popular standard RAMs
Memory controller cores
Ideal for large memory requirements

Memories can be built with the Core

Generator or Memory Interface Generator
(MIG)

External Memory
Interfacing

8/27/2015

Where Can I Learn More?

User Guides
Spartan-6 FPGA User Guide
Describes the complete FPGA architecture, including distributed memory,
block memory and the MCB

Sparfan-6 FPGA Memory Controller User Guide

Detailed description of all MCB functionality

Xilinx Education Services courses

www.xilinx.com/training
Xilinx tools and architecture courses
Hardware description language courses
Basic FPGA architecture, Basic HDL Coding Techniques, and other Free
videos!