Please click on paper title to view Visual Supplement.

ISSCC 2009 / SESSION 6 / CELLULAR AND TUNER / 6.2

6.2

A SAW-Less Multiband WEDGE Receiver

Olivier Gaborieau1, Sven Mattisson2, Nikolaus Klemmer3, Bassem Fahs1,

Fabio T. Braz1, Richard Gudmundsson2, Thomas Mattsson2,
Carine Lascaux1, Christophe Trichereau1, Wen Suter3,
Eric Westesson2, Andreas Nydahl2
ST-NXP Wireless, Caen, France, 2Ericsson Mobile Platforms, Lund, Sweden
Ericsson Mobile Platforms, Raleigh, NC

1
3

With an ever-increasing number of frequency bands supported by cellular

transceivers (TRX), front-end (FE) complexity increases due to a large number of external SAW filters. The challenge of removing inter-stage filters from
multiband 3G receivers (RX) resides in the additional noise contribution due
to limited transmitter (TX) leakage rejection at the RX input, intermodulation
(IM) products and cross-compression due to TX leakage and strong out-ofband blockers. Increased downconverter dynamic range is thus required for a
SAW-less RX path. In addition, avoiding SNR degradation from reciprocal
mixing imposes additional constraints on LO phase noise.
The presented transceiver (Fig. 6.2.1) integrates all RX and TX functions
required to support a tri-band WCDMA/HSPA (bands I-VI, VIII, IX) and quadband GSM/GPRS/EDGE application in a single chip.
The transmit section uses two separate paths: one for EGPRS (polar modulation) and another one for WCDMA (direct conversion). Compared to previously published work [1-3], this TRX provides a higher integration level, yielding
a superior flexibility in the application and a lower bill-of-materials (BOM).
The circuit employs a 2-metal passive integration technology (PICS) allowing
the integration of high-Q LNA degeneration inductors, TX matching networks,
PLL filters and high-density supply-decoupling capacitors. The active
(10mm) and passive (40mm) die are double-flip-chip mounted into a 56-pin
package. In order to improve the isolation between RX and TX paths (operating simultaneously in 3G mode), octagonal-shaped VCO inductors are used
with mutually-orthogonal orientations to achieve better than 95dB isolation
between RX and TX VCOs. RX input and TX output paths are routed orthogonally to further minimize the RF coupling.
Figure 6.2.2 shows the FE architecture, comprising seven single-ended gainswitchable LNAs (three in 3G and four in 2G). A double-cascode structure provides high isolation between inputs and minimum group-delay change when
switching between high and low gain (-16dB) modes. The LNA degeneration
inductors are implemented in Al-metal on the passive substrate (PICS), with
typical inductance/Q-factor values of 0.7nH/20 at 2GHz and 2.3nH/18 at 1GHz.
In 2G mode, each pair of high/low-band LNAs employs a shared degeneration
inductor to save area. The LNA output currents are combined in a 2nd-level cascode circuit and passed through to the RX balun primary coil. Large PMOS
devices are used to configure this inductance between low- and high-band
settings, with transfer ratios of 6:4/4:3 in high/low band, respectively. The
interstage frequency response is tuned per band using a capacitance DAC. The
LNA output-current signal is AC coupled to the downconverter core via the
balun secondary winding. This effectively prevents LNA even-order distortion
components from entering the downconverter stage. The balun output current
circulates through two identical current commutators, consisting of transistors Q1, Q2, and Q1, Q2 respectively. In high-band operation, the overall current-commutation sequence is generated by directing the CKp,n controlled,
VCO-rate current pulses through switches Q1a,b to the baseband outputs via
CK/2-rate switches Q2a-d. Sequencing signals LIp,n, LQp,n are generated by a
conventional divide-by-2 quadrature circuit. The switching transients of Q2a-d
are controlled such that the sequencing signals are stable for the duration of
the corresponding CK half-period. In this way, sequencer output jitter is
masked and low-power operation is possible without impact on reciprocal
mixing of out-of-band blockers.
As a result, Q1 RF input current is directed to the I+, Q+, I-, Q- outputs for subsequent quarters of the CK/2 signal period. Conversion gain is 2x2/ for
each of the differential baseband outputs. Due to signal current re-use in the
second commutator, overall conversion gain is 2x4/, 3dB higher than for a
traditional Gilbert I/Q-mixer having the same current consumption. I/Q gain
and phase balance are achieved by maintaining accurate 50% duty cycle
throughout the VCO paths, and converter IP2 is maximized by maintaining a
high degree of active and passive component matching. Out-of-band blocking

114

2009 IEEE International Solid-State Circuits Conference

is maximized by protecting the baseband filter via a tuned RC roofing filter

pole.
The baseband channel filter (BCF) (Fig. 6.2.3) is designed as a reconfigurable
Legendre 5th-order (Gain~63 to 65dB, BW~2.15MHz) filter response in
WCDMA mode and a Butterworth 3rd-order (Gain~25 to 28dB, BW~230kHz)
response in GSM/EDGE mode. GSM/EDGE high-dynamic-range ADCs are cointegrated on chip [6]. RC auto-calibration and DC-offset cancellation in the
BCF help to overcome process and temperature drifts. A group-delay-variation
compensation minimizes WCDMA RX EVM.
Two VCOs are used to generate the RX LO signal at 2 and 4 RX frequencies
for low and high bands, respectively. Each VCO uses a 6b binary-weighted
NMOS varactor bank with 25% and 36% tuning range, respectively. Both
VCOs employ octagonal-shaped coils (Q~19 at 4GHz) to mitigate external
magnetic coupling. Measured phase-noise levels are below 155dBc/Hz at
45MHz offset at low- and high-band RX frequencies. VCO supply current is
4mA.
The VCOs are locked via the same 3rd-order fractional-N PLL. A temperature-adaptive loop-filter pre-charging system, active only during VCO band
self-calibration, preserves PLL locking in 3G mode over a wide temperature
range (-30 to +90C), whatever the initial locking temperature is. The 3rd-order
PLL natural frequency is set to 160kHz, with loop-filter resistors implemented
on the active die, while the capacitors are located on the passive die. An RCcalibrator adjusts the filter capacitors to compensate for process and temperature variations. Close-in phase noise is -96dBc/Hz @10kHz offset from a
2GHz carrier.
Figure 6.2.5 shows measured RX Noise Figure (NF) results for two scenarios
in band II (1990MHz):
1) in the presence of a WCDMA modulated blocking signal generated by the
on-chip TX at the band-specific duplex offset frequency (80MHz)
2) in the presence of a -45dBm CW blocking signal at half and double duplex
offset frequencies (corresponding to a -15dBm blocker at the antenna and
30dB duplexer attenuation).
Cross-compression, IM2 and IM3 performances are shown with CW, WCDMA
TX, and WCDMA TX & CW blockers respectively. Under worst-case duplexer
TX-RX isolation, a -26dBm out-of-band blocker at the LNA input results in
2.7dB/3dB NF, under CW and WCDMA modulation respectively.
Desensitization due to -26dBm CW blockers in addition to TX leakage is:
0.5/1.7dB at -380/-95MHz offset, respectively (band I)
0.6/1.8dB at -160/-40MHz offset, respectively (band II)
1/2dB at -90/-22.5MHz offset, respectively (band V)
Figure 6.2.4 shows measured RX EVM for 3GPP test-model 5 HSDPA with 16QAM modulation. A low EVM of less than 6% is maintained over a wide input
power range. Figure 6.2.6 shows a comparison with published RX work [2, 3].
A significant contribution to overall WEDGE radio cost is due to phone production calibration. In this TRX, all filters, VCOs and PLL bandwidths are internally self-calibrated.
The active die is implemented in a 0.25m BiCMOS process. The carrier substrate is realized in PICS and integrates all TRX components, including supply
decoupling into a single package. A crystal resonator is the only external component required. This TRX is in volume production.
References:
[1] H. Darabi et al., A Fully Integrated Quad-Band GPRS/EDGE Radio in 0.13m CMOS,
ISSCC Dig. Tech. Papers, pp. 206-207, Feb. 2008.
[2] B. Tenbroek et al., Single-Chip Tri-Band WCDMA/HSDPA Transceiver Without
External SAW Filters and with Integrated TX Power Control, ISSCC Dig. Tech. Papers,
pp. 202-203, Feb. 2008.
[3] J. Rogin et al., A 1.5V 45mW Direct-Conversion WCDMA Receiver IC in 0.13m
CMOS, IEEE J. Solid State Circuits, pp. 2339-2348, Dec. 2003.
[4] C. Takahasi et al, A 1.9GHz Si Direct-Conversion Receiver IC for QPSK Modulation
Systems, ISSCC Dig. Tech. Papers, pp. 138-139, Feb. 1995.
[5] Behzad Razavi, A 1.5V 900MHz Downconversion Mixer, ISSCC Dig. Tech. Papers,
pp. 48-49, Feb. 1996.
[6] Y. Le Guillou et al., Highly Integrated Direct-Conversion Receiver for
GSM/GPRS/EDGE with On-Chip 84dB Dynamic Range Continuous-Time Continuous
Time ADC, IEEE J. Solid State Circuits, vol. 40, no2, pp. 403-411, Feb. 2005.

978-1-4244-3457-2/09/$25.00 2009 IEEE

Please click on paper title to view Visual Supplement.

Please click on paper title to view Visual Supplement.

6L3

:('*(75$16&(,9(5

(*60
6$:

:&'0$

& / 5/
/LS

:&'0$%%
5[,4

/1$

$'&
$'&

'&
'&

(*60
)(
02'8/(

6

63,LQWHUIDFH

6HULDO
FRQWURO

9&2

3$

YFF
&

;2

YFF

5/

4D

&.S

*60('*(
75[GLJLWDO
GDWDLQWHUIDFH



2XW,
2XW,

YFF

YFF
&/

4E

2XW4
2XW4

ISSCC 2009 / February 9, 2009 / 2:00 PM

/LQ /TS

4D

4G

4F

4E

/TQ /LS

&.Q

4D 4E

&.S

YFF

/LQ /TS

YFF

4F 4G

4D

&/

5/

5/

4E

&/

/TQ

&.Q

YFF

6

6Q

YFF

%DOXQ

&Q

&

/% +%

3//

QGFDVFRGH
'$&

'$&

'$&

4D

9&$6&

4E

'$&

9&2

'$&

,2

637

%DQG6HOHFW

'$&
'$&

0DVWHU
FORFN

3//

:&'0$%%
7[,4

3$

(**/%



:&'0$
)(02'8/(

:/%

(**+%

(**/%

'$&

(**+%
:+%

VWFDVFRGH
/RZ
*DLQ

YFF

9LQ &S
9LQ &S

:+%

+LJK
*DLQ

/3,&6

4

/3,&6

/3,&6

9%4

/3,&6

1[4

9%

/3,&6

Figure 6.2.2: WEDGE RX front-end schematic.

Figure 6.2.1: Multi-band WEDGE transceiver block diagram.



:&'0$



/RZ%DQG
+LJK%DQG






&RPSRVLWH5;(90>@
&RPSRVLWH(90>@






























2XWRI%DQG,,3>G%P@







:&'0$
%DQG,,
%$1',,









,QSXW3RZHUG%P
,QSXW3RZHU>G%P@

Figure 6.2.4: Out-of-band IIP2 and RX EVM (3GPP test-model 5+8 HS-PDSCH) versus
input power.

















%DQG9 9,

%DQG,,, ,;

%DQG,,

%DQG, ,9




















$YHUDJH1RLVH)LJXUHLQ0+]>G%@
$YHUDJH1)LQ0+]>G%@

%DQG9,,,



















5[*DLQ>G%@
:&'0$5[*DLQ>G%@

:&'0$1RLVH)LJXUH>G%@
1RLVH)LJXUH>G%@

Figure 6.2.3: WEDGE RX baseband filter and AGC schematic.


0RGH
*



)UHTXHQF\>0+]@
0RGH
*













3DUDPHWHU
1RLVH)LJXUH
9ROWDJH*DLQ
*DLQUDQJH
2XWRI%DQG,,3
2XWRI%DQG,,3
(90
5[3RZHU&RQVXPSWLRQ
3RZHUVXSSO\
7HFKQRORJ\
3DFNDJH

:&'0$7[DQG
0+]G%P&:
:&'0$7[

:&'0$
%DQG,,
%$1',,

3DUDPHWHU
>@/%+%
1RLVH)LJXUH
G%
9ROWDJH*DLQ
1$
*DLQUDQJH
aG%
,,3
G%P
,,3
!G%P
0+]%ORFNHU1)
G%
5[3RZHU&RQVXPSWLRQ
P:
3RZHUVXSSO\
9 9
7HFKQRORJ\
PGLJLWDO&026
3DFNDJH
1$
  LQFOXGLQJWKH$'&
  $'&G\QDPLFUDQJH

:&'0$7[DQG
0+]G%P&:
&:7[

>@
G%
G%
G%
G%P
!G%P

P:
9 9
PGLJLWDO&026
1$

5HIHUHQFH
7KLVZRUN/%+%
 G% 
G%
G% 
G%P
G%P
G%
P:
9 9
0.25m BiCMOS
HVQFN56 7x7

5HIHUHQFH
>@
G%
1$
G%
G%P
G%P
1$
P:
9
0.13m digital CMOS
1$

7KLVZRUN/%+%
G%
G%
G%
G%P
G%PW\S

P:
9 9
0.25m BiCMOS
HVQFN56 7x7

*335HTXLUHPHQW
G%
1$
1$
G%P
G%P
G%
1$
1$
1$
1$

*335HTXLUHPHQW
G%
1$
1$
G%P
G%P

1$
1$
1$
1$










0+]7[3RZHUDW/1$>G%P@
0+]7[3RZHUDW/1$>G%P@







Figure 6.2.5: WCDMA Band II NF versus frequency and versus TX Power at LNA.

Figure 6.2.6: Receiver performance summary.

DIGEST OF TECHNICAL PAPERS

Please click on paper title to view Visual Supplement.

115

Please click on paper title to view Visual Supplement.

ISSCC 2009 PAPER CONTINUATIONS

Figure 6.2.7: Transceiver micrograph highlighting the receiver path.

2009 IEEE International Solid-State Circuits Conference

978-1-4244-3457-2/09/$25.00 2009 IEEE

Please click on paper title to view Visual Supplement.