Assembler: Is A Program That Accepts An Assembly Language Program As Input and Converts It

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)
Date: 07.10.2005
Topic: Assembler Directives
Faculty: Anita Kanavalli MSRIT
Lecture Notes
Assembler: is a program that accepts an assembly language program as input and converts it
into an object module and prepares for loading the program into memory for execution.
Loader (linker) further converts the object module prepared by the assembler into executable
form, by linking it with other object modules and library modules.
The final executable map of the assembly language program is prepared by the loader at the time
of loading into the primary memory for actual execution.
The assembler prepares the relocation and linkages information (subroutine, ISR) for loader.
The operating system that actually has the control of the memory, which is to be allotted to the
program for execution, passes the memory address at which the program is to be loaded for
execution and the map of the available memory to the loader.
Based on this information and the information generated by the assembler, the loader generates
an executable map of the program and further physically loads it into the memory and transfers
control to for execution.
Thus the basic task of an assembler is to generate the object module and prepare the loading and
linking information.
Procedure for assembling a program
Assembling a program proceeds statement by statement sequentially.
The first phase of assembling is to analyze the program to be converted. This phase is called
Pass1 defines and records the symbols, pseudo operands and directives. It also analyses the
segments used by the program types and labels and their memory requirements.
The second phase looks for the addresses and data assigned to the labels. It also finds out codes
of the instructions from the instruction machine, code database and the program data.
It processes the pseudo operands and directives.
It is the task of the assembler designer to select the suitable strings for using them as directives,
pseudo operands or reserved words and decides syntax.
Directives
Also called as pseudo operations that control the assembly process.
They indicate how an operand or section of a program to be processed by the assembler.
They generate and store information in the memory.
Assembler Memory models
Each model defines the way that a program is stored in the memory system.
Tiny: data fits into one segment written in .COM format
Small: has two segments data and memory.
There are several other models too.
Directive for string data in a memory segment
DB
define byte

Date: 07.10.2005
Lecture Notes
DW define word
DD
define double word
DQ
define 10 bytes
Example
Data1 DB
10H,11H,12H
Data2 DW 1234H
SEGMENT: statement to indicate the start of the program and its symbolic name.
Example
Name SEGMENT
Variable_name
DB
.
Variable_name
DW .
Name ENDS
Data SEGMENT
Data1
DB
Data2
DW
Data ENDS
.
.
Code SEGMENT
START: MOV AX,BX
Code ENDS
Similarly the stack segment is also declared.
For small models
.DATA
ENDS
The ENDS directive indicates the end of the segment.
Memory is reserved for use in the future by using a ? as an operand for DB DW or DD
directive. The assembler sets aside a location and does not initialize it to any specific value
(usually stores a zero). The DUP (duplicate) directive creates an array and stores a zero.
Example
Data1 DB
5 DUP(?)
This reserves 5 bytes of memory for a array data1 and initializes each location with 05H
ALIGN: memory array is stored in word boundaries.
Example
ALIGN 2 means storing from an even address

Date: 07.10.2005
Lecture Notes
Address 0
Address 1
Address 2
XX
YY
XX
The data XX is aligned to the even address.

ASSUME, EQU, ORG
ASSUME tells the assembler what names have been chosen for Code, Data Extra and Stack
segments. Informs the assembler that the register CS is to be initialized with the address allotted
by the loader to the label CODE and DS is similarly initialized with the address of label DATA.
Example
ASSUME CS: Name of code segment
ASSUME DS: Name of the data segment
ASSUME CS: Code1, DS: Data1
EQU: Equates a numeric, ASCII(American Standard Code for Information Interchange) or label
to another label.
Example
Data SEGMENT
Num1 EQU 50H
Num2 EQU 66H
Data ENDS
Numeric value 50H and 66H are assigned to Num1 and Num2
ORG: Changes the starting offset address of the data in the data segment
Example
ORG 100H
100
data1 DB
10H
it can be used for code too.
PROC & ENDP: indicate the start and end of the procedure. They require a label to indicate the
name of the procedure.
NEAR: the procedure resides in the same code segment. (Local)
FAR: resides at any location in the memory.
Example
Add PROC NEAR
ADD AX,BX
MOV CX,AX
RET
Add ENDP
PROC directive stores the contents of the register in the stack.
EXTRN, PUBLIC informs the assembler that the names of procedures and labels declared after
this directive have been already defined in some other assembly language modules.

Date: 07.10.2005
Lecture Notes
Example
If you want to call a Factorial procedure of Module1 from Module2 it must be declared as
PUBLIC in Module1.
Example
A sample for full segment definition
Data
Num1
Num2
Num3
Data
SEGMENT
DB
10H
DB
20H
EQU 30H
ENDS
ASSUME CS:Code,DS:Data
Code SEGMENT
START: MOV
AX,Data
MOV DS,AX
MOV AX,Num1
MOV CX,Num2
ADD AX,CX
Code ENDS
END START
Example
A sample for small model
. MODEL SMALL
.Data
Num1 DB
10H
Num2 DB
20H
Num3 EQU 30H
.Code
HERE: MOV AX,@Data
MOV DS,AX
MOV AX,Num1
MOV CX,Num2
ADD AX,CX

Date: 07.10.2005
Lecture Notes
QUESTIONS
1: What is a directive?
2: Describe the purpose of DB DW and DQ directive?
3: What is the purpose of .386 directive?
4: What does START indicate?

Date: 07.10.2005
Lecture Notes
BCD Arithmetic:
The microprocessor allows manipulation of BCD and ASCII data
BCD used in Cash registers and ASCII used by many programs
There are two instructions
DAA decimal adjust after addition
DAS decimal adjust after subtraction
Both instructions correct the result. The BCD number is stored as packed form 2 digits/byte and
if unpacked form means 1 digit/byte it functions with AL only.
DAA decimal adjust after addition
The result is in AL
The Logic of this instruction
If lower nibble>9 or AF=1 add 06
After adding 06 if upper nibble>9 or CF=1 add 60
DAA instruction follows ADD or ADC
Example1
ADD AL,CL
DAA
Let AL=53 and CL=29
AL=53+29
AL=7C
AL=7C+06 (as C>9)
AL=82
Example 2
Let AL=73 CL=29
AL=9C
AL=9C+06 (as C>9)
AL=A2
AL=A2+60=02 and CF=1
The instruction affects AF,CF,PF and ZF
Example3
MOV DX,1234H
MOV BX,3099H
MOV AL,BL
ADD AL,DL
DAA
MOV AL,BH
ADC AL,DH
DAA

Date: 07.10.2005
Lecture Notes
MOV CH,AL
BL=99H DL=34H
99+34=CD
AL=CD+6(D>9)
AL=D3
AL=D3+60(D>9)
AL=33 and CF=1
BH=30 DH=12
AL=30+12+CF
AL=43
DAA does not do anything
The result is placed in CX=4333
DAS instruction follows subtraction
The result is in AL
Logic of this instruction
If lower nibble>9 or AF=1 subtract 06
After subtracting 06 if upper nibble>9 or CF=1 add 60
The instruction affects AF,CF,PF and ZF
Example1
SUB AL,BH
DAS
Let AL=75 BH=46
AL=75-46=2F AF=1
AL=2F-6(F>9)
AL=29
Example 2
SUB AL,CH
DAS
AL=38 CH=61
AL=38-61=D7 CF=1(borrow)
AL=D7-60(D>9)
AL=77 CF=1(borrow)
Example 3
MOV DX,1234H
MOV BX,3099H

Date: 07.10.2005
Lecture Notes
MOV AL,BL
SUB AL,DL
DAS
MOV CL,AL
MOV AL,BH
SBB AL,DH
DAS
MOV CH,AL
AL=99-34=65
DAS will not have affect
AL=30-12=1E
AL=1E-06(E>9)
AL=18
The result is 1865 placed in CX
ASCII Arithmetic
Functions with ASCII coded numbers
The numbers range from 30-39H for 0-9
AAA
AAD
AAM
AAS use AX as source and destination
AAA
Example
add 31H and 39H the result is 6AH it should have been 10 decimal which is 31H and 30H
AAA is used to correct the answer
Converts resulting contents of AL to unpacked decimal digits
AAA instruction examines the lower 4 bits of AL for valid BCD numbers and checks AF=0 sets
the 4 high order bits to 0
AH cleared before addition
If lower digit of AL is between 0-9 and AF=1 06 is added
The upper 4 digits are cleared and incremented by 1
If the lower value of the lower nibble is greater than 9 then increment AL by 06 AH by 1
AF and CF set
The higher 4 bits of AL are cleared to 0
AH modified
To get the exact sum add 3030H to AX
AAS
Correct result in AL after subtracting two unpacked ASCII operands
The result is in unpacked decimal format
If the lower 4 bits of AL are>9 or if AF=1 then AL=AL-6 and AH=AH-1 CF and AF set
otherwise CF and AF set to 0 no correction

Date: 07.10.2005
Lecture Notes
result the upper nibble of AL is 00 and the lower nibble may be any number from 0-9
AAM
Follows multiplication instruction after multiplying two unpacked BCD numbers
Converts the product available in AL into unpacked BCD
Lower byte of result is in AL and upper in AH
Example
let the product is 5D in AL
D>9 so add 6 =13H
LSD of 13H is lower unpacked byte
Increment AH, AH=5+1=6 upper unpacked byte
After execution AH=06 and AL=03
MOV AL,5
MOV CL,5
MUL CL
AAM
Accomplishes conversion by dividing AX by 10
Benefit of AAM converts from binary to unpacked BCD
use of AAM for conversion
XOR DX,DX
MOV CX,100
DIV CX
AAM
ADD AX,3030H
XCHG AX,DX
AAM
ADD AX,3030H
AAD
Appears before division
requires AX to contain two digit unpacked BCD number(not ASCII) before executing
After adjusting AX with AAD it is divided by an unpacked BCD number to generate a single
digit result in AL with remainder in AH
Example
.MODEL
.CODE
.STARTUP
MOV AL,48H
MOV AH,0
AAM
ADD AX,3030H
MOV DL,AH
MOV AH,2

Date: 07.10.2005
Lecture Notes
PUSH AX
INT 21H
POP AX
MOV DL,AL
INT 21H
.EXIT
END
Logic instructions
AND
OR
Exclusive OR
NOT
TEST
The above instructions perform bitwise operation and the src and destination could be register or
memory location. Their function is same as logic opeartions
Shift instructions
They manipulate binary numbers
Used to control I/O Devices. Shift operation moves the number either to left or right within
memory location or a register. There are four instructions.There are two types of shift (1)
arithmetic and (2) logical. The shift left operation is equivalent to multiply operation and shift
right is divide operation. The data is shifted to left or right only by one position.
Shift left operation
Logical left: The contents of the register or memory location are shifted left by one position the
MSB bit moves to Carry flag bit and a zero is added to the LSB position
Example
SHL AX,1
AX=0000 1111 0000 1111 and Carry=1
After the execution of the instruction
AX=0001 1110 0001 1110 and Carry =0
Example
MOV CL,3
SHL DX,CL
The contents of the DX register are shifted left by three postions
Arithmetical Left: It is same as logical left shift.

Date: 07.10.2005
Lecture Notes
Logical right: The contents of the register or memory location are shifted right by one position
the LSB bit moves to Carry flag bit and a zero is added to the MSB position
Example
SHR AX,1
AX=0000 1111 0000 1111 and Carry=0
Result
AX=0000 0111 1000 0111 and carry=1
Arithmetic right: The contents of the register or memory location are shifted right by one
position the LSB bit moves to Carry flag bit and the sign bit is copied through the MSB position
Example
SAL AX,1
AX=1000 0000 0000 1111 and carry=0
Result
AX=1100 0000 0000 0111 and carry=1
Example
SAR SI,3
SI= 1010 1100 1010 0101 C=0
After first shift SI= 1101 0110 0101 0010 C=1
second shift SI=1110 1011 0010 1001 C=0
third shift SI= 1111 0101 1001 0100 C=1
All condition flags are affected
Rotation instructions
There are four rotate instructions.
Rotate left: The contents of the memory location or the register are rotated left by the no of
positions indicated in the instruction through the carry or without the carry.
ROL BL,4
Let BL=0001 0110 C=0
After first rotate
After second rotate
After third rotate
After fourth rotate
C= 0
C=0
C=0
C=1
BL= 0010 1100

BL= 0101 1000
BL= 1011 0000
BL= 0110 0000

Date: 07.10.2005
Lecture Notes
Rotate right
The contents of the memory location or the register are rotated right by the no of positions
indicated in the instruction through the carry or without the carry.
String instructions
REP it is a prefix used with instruction
REPE/REPZ
REPNE/REPNZ
These are used with CMPS and SCAS instructions
These instructions are used in the program as prefix.
CMPS
Compare string byte or string word
Only Flags affected
Zero flag set if strings match otherwise reset
DS:SI and ES:DI are used to point to the two strings
SCAS
Scans the string of bytes or words for an operand byte or word specified in register AL or AX
When match found the ZF=1 otherwise it is reset
LODS
Load string byte or string word
Loads the AL/AX register by the contents of a string pointed by DS:SI No flag affected
STOS
Stores contents of AL/AX register to a location in a string pointed by ES:DI
No flag affected
A bus is used to communicate between components in a computer system. They are typically
specialized, with (for instance) a memory bus having different characteristics from an IO bus.
Communications used in networks are different again.
An important distinction to be drawn early is that between a bus and a point-to-point network. A
bus has a single wire, or connection of wires with multiple sources and destinations. A point-topoint network has some sort of interconnection scheme between sources and destinations in
which the nodes are endpoints. In general a bus is cheaper and slower than other network
topologies; there is a shift in progress in some areas from busses to point-to-point networks; this
is most noticeable in high-speed ethernet and in AMD's multiprocessor system ``busses.''

Date: 07.10.2005
Lecture Notes
Bus operations should be thought of in terms of transactions. A bus transaction is an operation

on the bus; for instance, a memory read, or an interrupt service, or an IO write. A bus transaction
is initiated by a bus master who requests that some operation take place; a slave will respond to
the transaction appropriately. Different busses support different sets of transactions
Bus Components
Busses typically have several components in common. In general, dedicated groups of wires are
used for the different components (but see multiplexing, below).
1. Data: this is the whole purpose of the bus - to transmit data. Ordinarily, when you talk
about the ``width'' of a bus (8-bit bus, 32-bit bus, etc), you're talking about how many
wires are used for data.
2. Address: this is how the components on the bus recognize that data on the bus is
intended for them. Ordinarily, whenever a bus transaction takes place, an address is put
on the bus... recipient can tell who it's for. Memory and IO busses don't normally put a
source address on; that's either implicit in the transaction or irrelevant. Networks, on the
other hand, usually do.
3. Control: these wires contain a variety of information about the transaction, for instance
what type of transaction it is (read, write, interrupt request, etc). Most parallel busses may
also have a global clock, which would be a control line as well. A serial bus can't very
well do that, so the clock has to be carried with the data somehow.
4. Power and Ground: the bus has to have a ground wire, so the different components have
a common voltage reference (they'll normally have lots of ground wires, for electrical
immunity!). Also, all the cards in the bus need to get power from somewhere, so the bus
itself is a convenient place to distribute it.
PCI Bus
The Peripheral Component Interconnect (PCI) bus is the standard I/O bus on recent computers in
general, and PCs in particular.
It was developed by Intel in 1993 to replace the various busses which had been in use on both PCs and Macintoshes.
It is a 32-bit, 33MHz bus with multiplexed address and data, and very nice capabilities for
autoconfiguration ("Plug and Play"). It also supports both old, 5 volt devices and newer, 3.3 volt
devices.
Just as a brief note, it was developed by Intel in 1993 to replace the various busses which had
been in use on both PCs and Macintoshes. To Intel's credit, it is a remarkably architecture-neutral
bus. A very brief description would be that it is a 32-bit, 33MHz bus with multiplexed address
and data, and very nice capabilities for autoconfiguration ("Plug and Play"). It also supports both
old, 5 volt devices and newer, 3.3 volt devices.
There are many extensions to PCI. Best known is that it has simply been extended to 64 bits and
66 MHz. In addition, there is a variant called PC-104+, which is a 32-bit PCI bus in a highly

Date: 07.10.2005
Lecture Notes
shock and vibration resistant packaging. PCI-X is a backward-compatible extension to PCI, with
PCI-X itself running at 266MHz and PCI-X 2.0 at 533 MHz. This latter also defines a 16 bit
interface for space-constrained applications, and a new bus mastering protocol (PCI SIG likes to
call this peer-to-peer) that looks a lot like messaging.
All transfers on the PCI bus are "burst" transfers. What this means is that once a device obtains
the bus to perform a transfer, it is able to hang on to the bus indefinitely, and keep sending more
data every bus cycle (there's actually a time in the bus controller which will take control back
after some configurable time period, to keep transfers from being too long. The longer the
tranfers are the better the throughput, but this can cause unacceptable delays for other devices).
Configuration Space
One of the nicest features of PCI is its support for autoconfiguration. In addition to every device
having an address on the PCI bus, every card has its own address determined by which slot it is
plugged into. This is referred to as the card's configuration space, and can be queried (and parts
of it can be written) by the CPU. This normally occurs at boot time; it may be performed by the
BIOS prior to starting the boot loader, or it may be performed by the OS as it boots.
Here's a picture of the configuration space for a PCI device
Header(64 bytes)
00H
Identification
Status/Command
3FH
Cla
BIST
ss
Available
(192 bytes)
FFH
Special
The most important parts of the configuration space are:

Vendor and Device ID
The Vendor ID is a 16 bit number, assigned by the PCI SIG. You can look this number
up in a database to find out who built the card. The device ID is another 16 bit number,
assigned by the vendor. You can look this up in a database to find out the device model

Date: 07.10.2005
Lecture Notes
number. Put them together and you can know what kind of device you're going to be
talking to, so you can run the right device driver.
Class Code
This is a 24 bit number, assigned by I-don't-know-who, which identifies what kind of
device is on the card. The difference between this and the vendor/device id fields is that
this will specify something like "serial port" You can run the device based on its class
code, but to take advantage of any extra features (like the fact it might be an 8-port card
instead of a single-port card) requires the vendor and device IDs.
Base Registers
Up to six base registers can be specified, for the devices located on the card. If you have
fewer than six logical devices you will actually use fewer than these; if you have more,
you will have to get into some ugly hacks (for instance, on an eight port serial card I
have, six of the ports' base addresses are specified in the base addresses, while two are at
fixed offsets from the first two of the six). Unlike the vendor and device ID fields, and
the class codes, the base register addresses are read/write.
PCI Commands
There are a total of 16 possible commands on a PCI cycle. They're in the following table:
Command
Command Type
0000
Interrupt Acknowledge
0001
Special Cycle
0010
I/O Read
0011
I/O Write
0100
reserved
0101
reserved
0110
Memory Read
0111
Memory Write
1000
reserved
1001
reserved
1010
Configuration Read
1011
Configuration Write
1100
Multiple Memory Read
1101
Dual Address Cycle
1110
Memory-Read Line
1111
Memory Write and Invalidate
Here are some notes on the different transfer types
Interrupt Acknowledge (0000)

Date: 07.10.2005
Lecture Notes
The interrupt controller automatically recognizes and reacts to the INTA (interrupt
acknowledge) command. In the data phase, it transfers the interrupt vector to the AD
lines.
Special Cycle (0001)
AD15-AD0
0x0000
Processor Shutdown
0x0001
Processor Halt
0x0002
x86 Specific Code
0x0003 to 0xFFFF Reserved
I/O Read (0010) and I/O Write (0011)
Input/Output device read or write operation. The AD lines contain a byte address (AD0
and AD1 must be decoded). PCI I/O ports may be 8 or 16 bits. PCI allows 32 bits of
address space. On IBM compatible machines, the Intel CPU is limited to 16 bits of I/O
space, which is further limited by some ISA cards that may also be installed in the
machine (many ISA cards only decode the lower 10 bits of address space, and thus mirror
themselves throughout the 16 bit I/O space). This limit assumes that the machine supports
ISA or EISA slots in addition to PCI slots. The PCI configuration space may also be
accessed through I/O ports 0x0CF8 (Address) and 0x0CFC (Data). The address port must
be written first.
Memory Read (0110) and Memory Write (0111)
A read or write to the system memory space. The AD lines contain a doubleword address.
AD0 and AD1 do not need to be decoded. The Byte Enable lines (C/BE) indicate which
bytes are valid.
Configuration Read (1010) and Configuration Write (1011)
A read or write to the PCI device configuration space, which is 256 bytes in length. It is
accessed in doubleword units. AD0 and AD1 contain 0, AD2-7 contain the doubleword
address, AD8-10 are used for selecting the addressed unit a the malfunction unit, and the
remaining AD lines are not used.
Multiple Memory Read (1100)
This is an extension of the memory read bus cycle. It is used to read large blocks of
memory without caching, which is beneficial for long sequential memory accesses.
Dual Address Cycle (1101)
Two address cycles are necessary when a 64 bit address is used, but only a 32 bit physical
address exists. The least significant portion of the address is placed on the AD lines first,
followed by the most significant 32 bits. The second address cycle also contains the
command for the type of transfer (I/O, Memory, etc). The PCI bus supports a 64 bit I/O
address space, although this is not available on Intel based PCs due to limitations of the
CPU.
Memory-Read Line (1110)
This cycle is used to read in more than two 32 bit data blocks, typically up to the end of a
cache line. It is more effecient than normal memory read bursts for a long series of
sequential memory accesses.
Memory Write and Invalidate (1111)

Date: 07.10.2005
Lecture Notes
This indicates that a minimum of one cache line is to be transferred. This allows main
memory to be updated, saving a cache write-back cycle.
Interrupt Handling
PCI uses four pins, called INTA-INTD, for interrupt requests.
When an interrupt is required, the proper pin is asserted.
A card which only has a single interrupt will normally use INTA
In the modern systems BIOS exists which support PCI bus
-----------------------------------------------------------------------------------------------------------------Port details
The parallel port LPT1 is normally at I/O port addresses 378H, 379H and 37AH
The secondary port(if present) is located at 278H, 279H and 27AH
The parallel printer interface is located on the rear of the PC
LPT stands for Line printer
The printer interface gives access to eight lines that can be programmed to receive or send data
The Centronics interface implemented by the parallel port uses two connecters
One is 25 pin D type on the back of the PC
The other one is 36 pin on the back of the Printer
The parallel port can work as both transmitter and as well as receiver
Other than printers CD ROMs can also be interfaced through parallel port.
Universal Serial Bus (USB) allows the addition of a new device to a PC by plugging it into the
back of the machine or daisy-chaining it from another device on the bus. The device is
immediately available for use (no rebooting required) and often does not need a device driver to
be installed (depending on the operating system being used.
USB 1.1 allows communication speeds of 12 Megabits per second (or 1.5 Megabytes per
second). The enhanced USB 2.0 will use the same cables, connectors, and software interfaces
and will be backward compatible with older devices. USB 2.0 carries data at 360 to 480 Mbps
(60 MBps). All cables use four wires; the distance between two devices can be up to five meters.
A big advantage of USB devices, apart from their much greater speed, is that USB devices
configure themselves automatically: gone are the days when you had to fiddle with IRQ settings,
DMA channels, and I/O addresses to make a gadget work. Another benefit is that because USB
devices do not require IRQ settings, DMA channels, or I/O settings, COM and LPT ports
currently occupying an IRQ can be freed up, making more IRQ interrupts available for other
uses.
Another advantage of USB is that it is a standard port and can support just about any type of
device, including keyboards, mice, serial peripherals (e.g. modems), printers, audio input/output,
joysticks, digital cameras, scanners, external hard disks and CD burners. Soon, the collection of
space-consuming and costly dedicated ports for keyboards, printers, mice, modems etc will

Date: 07.10.2005
Lecture Notes
disappear and replaced by USB. USB can be built into most chipsets for about $1. The other
advantage is that you can mix and match devices as much as you like. In the old days, if you had
a parallel port scanner and a printer, they had to share the single printer port (and neither of them
would work properly for long.)
If you have several USB devices, it is best to use a USB hub. This is a little box that splits a
single USB port into 4 or more ports
USB uses a four-wire cable interface. Two of the wires are used in a differential mode for both
transmitting and receiving data, and the remaining two wires are power and ground. The source
of the power to a USB device can come from the host, a hub, or the device can be "self
powered." There are two different connector types on each end of a USB cable. One of these
connectors is for upstream communications, and the other for downstream. Each cable length is
limited
to
about
5
meters.
USB has four types of communication transfer modes:
control,
interrupt,
bulk, and
isochronous.
Control mode is initiated by the host. In this mode, every data transfer must send data in both
directions, but only in one direction at a time. The control mode is used mainly for initialization
of devices, but it can also be used to transfer small amounts of data.
In interrupt mode, interrupts do not occur in the usual sense. As in control mode, the host has to
initiate the transfer of data. Interrupt mode works by the host querying devices to see if they need
To be serviced
Bulk mode and isochronous mode complement each other in a sense. Bulk mode is used when
data accuracy is of prime importance, but the rate of data transfer is not guaranteed. An example
of this would be disk drive storage. Isochronous mode sacrifices data accuracy in favor of
guaranteed timing of data delivery. An example of this would be USB audio speakers.
These four modes will be discussed in more detail below.

Date: 07.10.2005
Lecture Notes
Above is an example of USB ports found on PCs and on some USB peripherals including
keyboards and
monitors.
The PC host typically has connections for two external USB ports. Each of these two connectors
on the PC is actually a connection to a separate root hub inside the PC. If either of the two root
hubs needs to have more than one device connected to it, a downstream USB hub is required to
expand connections. Hubs are used to add to the number of devices that can be connected to one
USB port. They can be considered to be a repeater of sorts and also a controller. When a device
is connected downstream of a hub, the hub does the connect detection of the new device and
notifies the host.
Hubs can be inside the device itself -- for example, in a keyboard that may have an additional
two downstream USB connectors for additional devices. A hub can have a combination of high
and low speed devices connected to it, up to a maximum of four additional hubs downstream
from itself. A hub's upstream port to the PC must be high speed. The hub acts as a traffic cop,
handling communication to downstream devices as either high or low speed. A hub can ignore a
downstream device that is not behaving properly. Hubs can be either self-powered or receive
power from the USB bus. USB 1.x hubs support both low and high-speed data transfers.
There are several hardware requirements for devices that are placed on the USB bus. Five volts
is the nominal supply voltage on the bus. A device that requires 100mA or less can be powered
from the host or any hub, provided that the total available power hasn't already been exhausted
by other devices. A device on the bus can draw up to 500mA from it. However, not all USB
hosts (especially a battery powered PC) or bus-powered hubs will allow a device to draw more
than 100mA from the bus. For this reason, a USB device that draws more than 100mA should, in
most cases, be self-powered .
A device tells the host how much current is required for its operation. Self-powered devices
usually get their power from a separate power supply or batteries. A battery-powered device
plugged into the bus can get its power from the bus if it meets the tests above, and it can then
switch back over to battery power when it is disconnected from the bus or when the host is shut
down. When a device is in suspend mode, it cannot draw any more than 500uA from the bus if it
is bus-powered. Also, if a device has not seen any activity on its bus in 3 mS, it needs to go into
suspend mode. A host can initiate a resume command to a device that is in suspend mode. A
device can also issue a remote wakeup to an inactive host to make it active.
All devices have endpoints, which are memory buffers. An endpoint can be as simple as an
addressable single register, or it can be a block of memory that is used to store incoming and/or
outgoing data. There may be multiple endpoints inside a device. Each device has at least one
endpoint -- "endpoint 0"-- which is used as a control endpoint. It must be able to both send and
receive data, but can only communicate in one direction at a time. Typically, when a device

Date: 07.10.2005
Lecture Notes
receives data such as an Out or Setup command from the host, this data is stored in the endpoint
and the device's microprocessor is interrupted and works on this data. When a device receives an
In command that is addressed to it from the host, data for the host that is stored in the endpoint is
sent to the host.
The host is considered to be the master in most all cases. One exception is when a device issues a
remote wakeup to the host as discussed above. There are time limits for both the host and device
to respond to each other. For example, if the host requests data from a device using an In
command, the device must send the data back to the host within 500mS, in some cases.
Depending on the transaction type, the host and/or the device may respond to data received with
an acknowledgement. Data transfer involves quite a bit of error-checking and handshaking. The
different types of data packets sent and received use different ways to verify correct data transfer.
A logical connection link needs to be set up between the host and a device before a transaction
can occur. This connection is referred to as a Pipe. It is set up as soon as possible after a host has
recognized a device as being connected. When the host responds to a connect signal from the
device, one of the parameters that is sent to the host is the device's required data transfer type and
speed. The host can refuse to establish a Pipe if the host does not have enough bandwidth to
support the device's request or if its power requirements cannot be met. The device at its
discretion can lower its requested data rate and try again until the host accepts it and initiates a
Pipe.
When a device is connected, it also sends to the host descriptor information on the types of
endpoints in the device, the type of data transfer it uses, size of data packets, endpoint addresses
within the device, and if used, the time required between data transfers.
The following describes a typical data flow for a device when it is initially plugged into a host's
bus while the host is active. Remember here that the host has an internal USB hub, and
additional hubs may be connected downstream from the host's hub.
1. The host recognizes that a device has been attached to one of its USB hubs. It realizes
this by a simple resistive divider that is connected to the differential data pair of wires in
the USB bus. These resistors are inside the USB hubs and devices.
2. The host sends a Get_Port_Status request to the hub to find out more about what has been
plugged in. It could be another hub, a device connected directly to the host hub, or a
device that has been plugged into one of the downstream hubs.
3. After receiving a response from the hub, the host issues a Set_Port_Feature command in
which the hub issues a reset over the data pair but only to the newly connected device on
the USB bus.
4. The host then checks to see if the device has come out of the reset state by issuing a
Get_Port_Status command to the hub. After reset, the device is in the Default state and
can only draw a maximum of 100mA. In Default state, the device can communicate with
the host through Endpoint 0.
5. The hub now detects the device's speed by using the resistive dividers that are attached to
the USB bus. The hub sends the speed of this device back to the host.

Date: 07.10.2005
Lecture Notes
6. The host then sends a Get_Descriptor command to the hub in which the hub gets the
packet size needed from this particular device and sends the result back to the host.
7. The host now issues a Set_Address command to the hub which sends this information to
the device. The device in turn acknowledges the command back through the hub to the
host and sets up this address internally.
8. To learn more about this device, the host sends a Get_Descriptor command to the address
that the device has been given. The information that is returned to the host consists of
various details of the device that the host needs to know for its operation. These queries
by the host continue two more times to retrieve all the information needed.
9. Based on the information received from the device, the host determines the best device
driver to use for communications with it.
10. The device driver in the host now takes over by requesting a Set_Configuration
command. There can be several configurations for one device, and the device driver
determines which to use based on information received from the device in response to the
Get_Descriptor command.
11. The device is now ready for use.
As you can see, the USB protocol is a fairly complex arrangement. This strict pattern of query
and response, however, is important in alleviating potential conflicts on the bus.
--------------------------------------------------------------------------------------------------------------------
Addition:
There are two instructions ADD and ADC
Register Addition:
ADD AL,BL AL=AL+BL
ADD CX,DI CX=CX+DI
ADD CL,10H CL=CL+10
ADD [BX],AL the contents of AL are added with the contents of a memory location
addressed by BX and the result is stored in the same memory location
Example
ADD AL,BL AL=10H
BL=30H the result AL=40H

Date: 07.10.2005
Lecture Notes
ADD AX,[SI+2] the word content of the data segment memory location addressed by sum of
SI+2 is added with AX and the result is stored in AX
Example
AX=1234H SI=2000 SI+2=2002 and let the word stored in memory location 2002 be
1122H The result AX=2356H
ADD BYTE PTR [DI],3 3 is added to the byte contents of the data segment memory
location addressed by DI
Example
DI=2000 and the contents of that memory location is 11H
The contents of address 2000 will be 14H after the execution of this instruction
The contents of the flag register change after the addition operation. The flags affected are
SIGN,CARRY,ZERO, AUX CARRY,PARITY,OVERFLOW
The INTR,TRAP and other flags not affected.
Immediate Addition
An 8 bit immediate data is added.
Example
MOV AL,10H
ADD AL,30H
The result AL=40H
Memory to Register addition
Example
MOV AX,0
ADD AX,DI
ADD AX,DI+1
Let DI=2000 the contents of this memory location is 22H
After first add AX will have 22+0=22H
Then DI+1=2001 let the contents be 11H
The result will be 33H
Array addition The offset address of the array is moved to the SI or DI register
Example
MOV AL,0
MOV SI,OFFSET of Array

Date: 07.10.2005
Lecture Notes
ADD AL,[SI]
ADD AL,[SI+2]
ADD AL,[SI+4]
Array
Offset
addr
2000
10H
2001
2002
2003
2004
11H
22H
33H
44H
After first add the contents AL will be 0+10=10H

After the second add instruction AL will be 10+22=32H
After the third add instruction AL will be 32+44=76H
Increment addition
INC adds a 1 to a register or a memory location used for memory increments
Example
INC AX
This instruction adds one to the contents ox AX let Ax=1234H the result will be AX=1235H
INC BYTE PTR [DI]
This instruction adds one to the byte contents of the data segment location addressed by DI
Addition with carry
ADC adds the bit in carry flag to the operand data.
Example
ADC AL,BH
AL=AL+BH+CARRY
ADC CX,AX
CX=CX+AX+CARRY
ADC BX,[BP+2] the word contents of the stack segment memory location addressed by
BP+2 is added to BX with carry and the result is stored in BX.
Subtraction
Many forms of subtraction appears to use with any addressing mode 8 16 and 32 bit data
SUB
SBB subtract with borrow
Register Subtraction:
SUB AL,BL
AL=AL-BL
SUB CL,10H CL=CL-10
The carry flag holds the borrow.

Date: 07.10.2005
Lecture Notes
Decrement
A 1 is subtracted from the register or the memory location.
Example
DEC AX
DEC BYTE PTR [DI]
DEC CL
DEC BL
Subtracts 1 to from a register or a memory location
CMP
This changes only the flag the destination operand never changes
This instruction is usually followed by conditional jump instructions
and tests the condition against the flags
Multiplication
The multiplication is performed on bytes words or double words and can be a signed integer or
unsigned integer
MUL: unsigned
IMUL: signed
Flags CARRY,OVERFLOW
8 Bit multiplication
Example
MOV BL,05H
MOV AL,10H
MUL BL
The multiplicand is in AL
The multiplier is in BL (even a memory location can be used)
8 Bit multiplication
Example
IMUL BYTE PTR [BX]
AL is multiplied by the byte contents of the data segment memory location addressed by BX the
signed product is placed in AX
For signed multiplication the product is in true binary form if positive and in twos complement
form if negative
Example
AL
00000010
BL 10000100

Date: 07.10.2005
Lecture Notes
AL contains +2 and BL contains -4

IMUL BL
The product is -8
The product is in twos complement form stored in AX
AX 11111000
Division
DIV,IDIV
The dividend is always a double width dividend that is divided by the operand
An 8 bit division devides a 16 bit number by a 8 bit number
Errors: Divide by zero,devide overflow
AX register stores the dividend that is divided by contents of any 8 bit register or memory
location.
the Quotient(result) moves to AL and AH has the remainder.
For signed division the remainder always assumes sign of dividend and is an integer
AX=0010H equivalent to +16
BL=FDH equivalent to -3
DIV BL
AL=05H and AH=-1 11111111H
AX=1111111100000101H
AX=0010H equivalent to +16
BL=FDH equivalent to -3
DIV BL
AL=-5 11111011 and AH=1
AX=0000000111111011H

Assembler: Is A Program That Accepts An Assembly Language Program As Input and Converts It

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Assembler: Is A Program That Accepts An Assembly Language Program As Input and Converts It

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EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

The data XX is aligned to the even address.

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

BL= 0010 1100

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

Bus operations should be thought of in terms of transactions. A bus transaction is an operation

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

The most important parts of the configuration space are:

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

BL=30H the result AL=40H

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

After first add the contents AL will be 0+10=10H

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

EDUSAT SESSION FOR ADVANCED MICROPROCESSOR (EC54)

AL contains +2 and BL contains -4

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