Philips UOCIII-V1.8 Manual Entrenamiento

INTEGRATED CIRCUITS
DEVICE
DATASPECIFICATION
SHEET
UOCIII series
Versatile signal processor for lowand mid-range TV applications
Preliminary specification
File
under18Integrated Circuits, <Handbook>
Version:
2003 Nov 11
Previous date: 2003 Oct 09
CONFIDENTIAL
Philips Semiconductors
Versatile signal processor for low- and

mid-range TV applications
UOCIII series
GENERAL DESCRIPTION
The UOCIII series combines the functions of a Video
Signal Processor (VSP) together with a FLASH embedded
TEXT/Control/Graphics -Controller (TCG -Controller)
and US Closed Caption decoder. In addition the following
functions can be added:
Adaptive digital (4H/2H) PAL/NTSC combfilter
Teletext decoder with 10 page text memory
Multi-standard stereo decoder
FEATURES
BTSC stereo decoder
Analogue Video Processing (all versions)
Digital sound processing circuit
Multi-standard vision IF circuit with alignment-free PLL

demodulator
Digital video processing circuit
Internal (switchable) time-constant for the IF-AGC circuit
The UOCIII series consists of the following 3 basic

concepts:
Switchable group delay correction and sound trap (with

switchable centre frequency) for the demodulated CVBS
signal
Stereo versions. These versions contain the TV

processor with a stereo audio selector, the TCG
-Controller, the multi-standard stereo or BTSC
decoder, the digital sound processing circuit and the
digital video processing circuit. Options are the adaptive
digital PAL/NTSC comb filter and a teletext decoder with
10 page text memory.
DVB/VSB IF circuit for preprocessing of digital TV

signals.
Video switch with 3 external CVBS inputs and a CVBS
output. All CVBS inputs can be used as Y-input for Y/C
signals. However, only 2 Y/C sources can be selected
because the circuit has 2 chroma inputs. It is possible to
add an additional CVBS(Y)/C input (CVBS/YX and CX)
when the YUV interface and the RGB/YPRPB input are
not needed.
AV stereo versions. These versions contain the TV

processor with stereo audio selector and the TCG
-Controller. Options are the digital sound processing
circuit, the digital video processing circuit, the adaptive
digital PAL/NTSC comb filter and a teletext decoder with
a 10 page text memory.
Automatic Y/C signal detector

Adaptive digital (4H/2H) PAL/NTSC comb filter for
optimum separation of the luminance and the
chrominance signal.
Mono sound versions. These versions contain the TV

processor with a selector for mono audio signals and the
TCG -Controller. Options are the adaptive digital
PAL/NTSC combfilter and a teletext decoder with 10
page text memory.
Integrated luminance delay line with adjustable delay

time
Picture improvement features with peaking (with
switchable centre frequency, depeaking, variable
positive/negative peak ratio, variable pre-/overshoot
ratio and video dependent coring), dynamic skin tone
control, gamma control and blue- and black stretching.
All features are available for CVBS, Y/C and
RGB/YPBPR signals.
The most important features of the complete IC series are

given in the following feature lists. The exact feature
content of the various ICs is given in Table 1 on page 7.
The ICs are mounted in a QFP-128 envelope(1) and can be
used in economy television receivers with 90 and 110
picture tubes. They have supply voltages of 5V, 3.3V. Also
an 1.8V supply is needed, but this can be simply derived
by adding an emitter follower at a reference voltage from
the device.
Switchable DC transfer ratio for the luminance signal

Only one reference (24.576 MHz) crystal required for
the TCG -Controller, digital sound processor, Teletextand the colour decoder
UOCIII is supported by a comprehensive Global TV

Software Development kit to enable easy programming
and fast time-to-market (see also Chapter LICENSE
INFORMATION on page 6.
Multi-standard colour decoder with automatic search

system and various forced mode possibilities
Internal base-band delay line
(1) Both standard and face down versions of the QFP128

0.8mm pitch package are available.
2003 Nov 11
CONFIDENTIAL

Indication of the Signal-to-Noise ratio of the incoming
CVBS signal
UOCIII series
Sound Demodulation (all versions)
Separate SIF (Sound IF) input for single reference QSS
(Quasi Split Sound) demodulation.
Linear RGB/YPBPR input with fast insertion.

YUV interface. When this feature is not required some
pins can be used as additional RGB/YPBPR input. It is
also possible to use these pins for additional CVBS (or
Y/C) input (CVBS/YX and CX).
AM demodulator without extra reference circuit

The mono intercarrier sound circuit has a selective
FM-PLL demodulator which can be switched to the
different FM sound frequencies (4.5/5.5/6.0/6.5 MHz).
The quality of this system is such that the external
band-pass filters can be omitted. In the stereo versions
of UOCIII the use of this demodulator is optional for
special applications. Normally the FM demodulators of
the stereo demodulator/decoder part are used (see
below).
Tint control for external RGB/YPBPR signals

Scan Velocity Modulation output. The SVM circuit is
active for all the incoming CVBS, Y/C and RGB/YPBPR
signals. The SVM function can also be used during the
display of teletext pages.
RGB control circuit with Continuous Cathode
Calibration, white point and black level off-set
adjustment so that the colour temperature of the dark
and the light parts of the screen can be chosen
independently.
The FM-PLL demodulator can be set to centre

frequencies of 4.72/5.74 MHz so that a second sound
channel can be demodulated. In such an application it is
necessary that an external bandpass filter is inserted.
The vision IF and mono intercarrier sound circuit can be
used for the demodulation of FM radio signals. With an
external FM tuner also signals with an IF frequency of
10.7 MHz can be demodulated.
Contrast reduction possibility during mixed-mode of

OSD and Text signals
Adjustable wide blanking of the RGB outputs
Horizontal synchronization with two control loops and
alignment-free horizontal oscillator
Switch to select between 2nd SIF from QSS

demodulation or external FM (SSIF)
Vertical count-down circuit

Vertical driver optimized for DC-coupled vertical output
stages
Audio Interfaces and switching (stereo versions with

Audio DSP)
Horizontal and vertical geometry processing with

horizontal parallelogram and bow correction and
horizontal and vertical zoom
Audio switch circuit with 4 stereo inputs, a stereo output

for SCART/CINCH, 1 stereo output for HEADPHONE.
The headphone channel has an analogue volume
control circuit for the L and R channel. Finally 1 stereo
SPEAKER output with digital controls.
Low-power start-up of the horizontal drive circuit
AVL (Automatic Volume Levelling) circuit for the

headphone channel.
Analogue video processing (stereo versions)

The low-pass filtered mixed down I signal is available
via a single ended or balanced output stage.
Digital input crossbar switch for all digital signal sources

and destinations
Analogue video processing (mono versions)
Digital output crossbar for exchange of channel

processing functionality
The low-pass filtered mixed down I signal is available

via a single ended output stage
Digital audio input interface (stereo I2S input interface)

Digital audio output interface (stereo I2S output
interface)
Digital Video Processing (some versions)

Double Window mode applications. It is possible to
display a video and a text window or 2 text windows in
parallel.
Audio interfaces and switching (AV stereo versions

without Audio DSP)
Linear and non-linear horizontal scaling of the video

signal to be displayed.
Audio switch circuit with 4 stereo inputs, a stereo output

for SCART/CINCH and a stereo SPEAKER output with
analogue volume control.
Analogue mono AVL circuit at left audio channel
2003 Nov 11
CONFIDENTIAL

UOCIII series
Volume and tone control for loudspeakers (stereo
versions with Audio DSP)
Audio interfaces and switching (mono versions)

Audio switch circuit with 4 external audio (mono) inputs
and a volume controlled output
Automatic Volume Level (AVL) control

Smooth volume control
AVL circuit
Master volume control
Stereo Demodulator and Decoder (full stereo

versions)
Soft-mute
Loudness
Demodulator and Decoder Easy Programming (DDEP)
Bass, Treble
Auto standard detection (ASD)
Dynamic Bass Boost (DBB) (2)
Static Standard Selection (SSS)
Dynamic Virtual Bass (DVB) (3)
DQPSK demodulation for different standards,

simultaneously with 1-channel FM demodulation
BBE Sound processing (4)
NICAM decoding (B/G, I, D/K and L standard)
Graphic equaliser
Two-carrier multistandard FM demodulation (B/G, D/K

and M standard)
Programmable beeper
Processed or non processed subwoofer
Decoding for three analog multi-channel systems (A2,

A2+ and A2*) and satellite sound
Reflection and delay for loudspeaker channels

(stereo versions with Audio DSP)
Adaptive de-emphasis for satellite FM
Dolby Pro Logic Delay (1)
Optional AM demodulation for system L, simultaneously

with NICAM
Pseudo hall/matrix function
Identification A2 systems (B/G, D/K and M standard)

with different identification time constants
Psycho acoustic spatial algorithms, downmix and

split in loudspeaker channels (stereo versions with
Audio DSP)
FM pilot carrier present detector

Monitor selection for FM/AM DC values and signals,
with peak and quasi peak detection option
Extended Pseudo Stereo (EPS) (5)

Extended Spatial Stereo (ESS) (6)
BTSC MPX decoder
Virtual Dolby Surround (VDS 422,423) (1)
SAP decoder
SRS 3D and SRS TruSurround (4)
dbx noise reduction (4)

Japan (EIAJ) decoder
RDS/RBDS
FM radio decoder
Demodulation of the European Radio Data system

(RDS) or the USA Radio Broadcast Data System
(RBDS) signal
Soft-mute for DEMDEC outputs DEC, MONO and SAP

FM overmodulation adaptation option to avoid clipping
and distortion
RDS and RBDS block detection

Error detection and correction
Audio Multi Channel Decoder (stereo versions with

Audio DSP)
Fast block synchronisation

Synchronisation control (flywheel)
Dolby Pro Logic (DPL) (1)
Mode control for RDS/RBDS processing
Five channel processing for Main Left and Right,

Subwoofer, Centre and Surround. To exploit this feature
an external DAC is required.
Different RDS/RBDS block information output modes

(2) Also referred to as Dynamic UltraBass
(3) Also referred to as Dynamic Bass Enhancement
(4) For the use of these products a licence is required. More
details are given in the chapter LICENSE INFORMATION on
page 6
(5) Also referred to as I-Mono or Incredible Mono
(6) Also referred to as I-Stereo or Incredible Stereo
(1) Dolby is a trademark of Dolby Laboratories
2003 Nov 11
CONFIDENTIAL

UOCIII series
-Controller
Display
80C51 -controller core standard instruction set and

timing
Teletext and Enhanced OSD modes
0.4883 s machine cycle
50Hz/60Hz display timing modes
Features of level 1.5 WST and US Close Caption
maximum of 256k x 8-bit flash programmable ROM
Two page operation for 16:9 screens
maximum of 8k x 8-bit Auxiliary RAM
Serial and Parallel Display Attributes
12-level Interrupt controller for individual enable/disable

with two level priority
Single/Double/Quadruple Width and Height for

characters
Two 16-bit Timer/Counter registers

One 24-bit Timer (16-bit timer with 8-bit Pre-scaler)
Smoothing capability of both Double Size, Double Width

& Double Height characters
WatchDog timer
Scrolling of display region
Auxiliary RAM page pointer
Variable flash rate controlled by software
16-bit Data pointer
Soft colours using CLUT with 4096 colour palette
Stand-by, Idle and Power Down modes
Globally selectable scan lines per row (9/10/13/16/) and

character matrix [12x9, 12x13, 12x16, 16x18, (VxH)]
24 general-purpose I/O pins
Fringing (Shadow) selectable from N-S-E-W direction
14 bits PWM for Voltage Synthesis Tuning
Fringe colour selectable
8-bit A/D converter with 4 multiplexed inputs
Contrast reduction of defined area
5 PWM (6-bits) outputs for analogue control functions
Cursor
Remote Control Pre-processor (RCP)

Universal Asynchronous Receiver Transmitter (UART)
Special Graphics Characters with two planes, allowing

four colours per character
Data Capture
64 software redefinable On-Screen display characters
Text memory up to 10 pages
4 WST Character sets (G0/G2) in single device (e.g.

Latin, Cyrillic, Greek, Arabic)
Inventory of transmitted Teletext pages stored in the

Transmitted Page Table (TPT) and Subtitle Page Table
(SPT)
G1 Mosaic graphics, Limited G3 Line drawing

characters
WST Character sets and Closed Caption Character set
in single device
Data Capture for US Closed Caption

Data Capture for 525/625 line WST, VPS (PDC system
A) and 625 line Wide Screen Signalling (WSS) bit
decoding
SVM for Text
Automatic selection between 525 WST/625 WST

Automatic selection between 625 WST/VPS on line 16
of VBI
Real-time capture and decoding for WST Teletext in
Hardware, to enable optimized -processor throughput
Automatic detection of FASTEXT transmission
Real-time packet 26 engine in Hardware for processing
accented, G2 and G3 characters
Signal quality detector for video and WST/VPS data
types
Comprehensive teletext language coverage
Vertical Blanking Interval (VBI) data capture of WST
data
2003 Nov 11
CONFIDENTIAL

UOCIII series
LICENSE INFORMATION
dbx
dbx is a registered trademark of Carillon Electronics Corp. A license is required for the use of this product. For further
information, please contact THAT Corporation, 45 Summer street, Milford, Massachusetts 01757-1656, USA.
Tel: 1-508-478-9200, FAX: 1-508-478-0990
Dolby
Dolby, Pro Logic and the double-D symbol are trademarks of Dolby Laboratories, San Francisco, USA, products are
available to licensees of Dolby Laboratories Licensing Corporation, 100 Potrero Avenue, San Francisco, CA, 94103,
USA,
Tel: 1-415-558-0200, Fax: 1-415-863-1373
Supply of this Implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any
other Industrial or Intellectual Property Right of Dolby Laboratories, to use this Implementation in any finished end-user
or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories.
BBE
BBE is a registered trademark of BBE Sound, Inc., 5381 Production Drive, Huntington Beach, California 92649, USA.
The use of BBE needs licensing from BBE Sound, Inc.
Tel: 1-714-897-6766, Fax: 1-714-895-6728
The SRS TruSurround technology rights incorporated in the TDA120xxH are owned by SRS Labs, a U.S. Corporation
and licensed to Philips Semiconductors B.V. Purchaser of TDA120xxH must sign a license for use of the chip and display
of the SRS Labs trademarks. Any products incorporating the TDA120xxH must be sent to SRS Labs for review. SRS
and TruSurround are protected under US and foreign patents issued and/or pending. TruSurround, SRS and (O) symbol
are trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the chip
TDA120xxH, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized
recordings made with any SRS technology. SRS Labs requires all set makers to comply with all rules and regulations as
outlined in the SRS Trademark Usage Manual separately provided.
Philips
Dynamic Ultra BassTM, Dynamic Bass Enhancement, I-Mono and I-Stereo are denominators for Philips patented
technologies. The use of the IC does not imply any copyrights nor the right to use the same denominators but instead
generic ones such as listed below.
Generic name/ Philips name
Dynamic Virtual Bass (DVB)/Dynamic UltraBass
Dynamic Bass Boost (DBB)/Dynamic Bass Enhancement
Extended Pseudo Stereo (EPS)/I-Mono
Extended Spatial Stereo (ESSI)/I-Stereo
GTV
Delivery and use of the GTV Software Development Kit requires a separate License sold by Philips Semiconductors B.V.
Please contact your nearest Philips Semiconductors sales office for further details.
2003 Nov 11
CONFIDENTIAL
NTSC
128
1.25 2.25
NTSC
128
1.25 2.25
MULTI
128
1.25 2.25
MULTI
128
1.25 2.25
MULTI
128
TDA12001H/H1(2) BTSC(3)
TDA12006H/H1
BTSC(3)
TDA12007H/H1
BTSC(3)
TDA12008H/H1
BTSC(3)
TDA12009H/H1
BTSC(3)
TDA12010H/H1(2)
MULTI
TDA12011H/H1(2)
MULTI
TDA12016H/H1
MULTI
TDA12017H/H1
MULTI
TDA12018H/H1
MULTI
TDA12019H/H1
MULTI
TDA12020H/H1(2)
MULTI
TDA12021H/H1(2)
MULTI
TDA12026H/H1
MULTI
TDA12027H/H1
MULTI
TDA12028H/H1
MULTI
TDA12029H/H1
MULTI
MULTI
2.25
10
2.25
128
NTSC
128/256
1.25 2.25
NTSC
128/256
1.25 2.25
NTSC
128/256
1.25 2.25
NTSC
128/256
1.25 2.25
NTSC
128/256
1.25 2.25
NTSC
128/256
1.25 2.25
MULTI
128/256
1.25 2.25
MULTI
128/256
1.25 2.25
MULTI
128/256
1.25 2.25
MULTI
128/256
1.25 2.25
MULTI
128/256
1.25 2.25
MULTI
128/256
1.25 2.25
MULTI
128/256
10
2.25
MULTI
128/256
10
2.25
MULTI
128/256
10
2.25
MULTI
128/256
10
2.25
MULTI
128/256
10
2.25
MULTI
128/256
10
2.25
10
UOCIII series
TDA12000H/H1(2) BTSC(3)
DRCS RAM (k)
DISPLAY RAM (k)
TDA11020H/H1
AUX RAM SIZE (k)
ROM SIZE (k)
TDA11021H/H1
CONFIDENTIAL
TDA11010H/H1
TDA11011H/H1
DW / PANORAMA
BBETM
SRS TruSurround
TDA11001H/H1
SRS 3D Stereo
Virtual Dolby (VDS)
Dolby ProLogic
TDA11000H/H1
10
dbx
RDS/RBDS
STEREO
AUDIO
DECOMONO
DSP
DER
MONO FM RADIO
TYPE NUMBER(1)
STEREO FM RADIO
NUMBER OF
TELETEXT
PAGES
COLOUR DECODER
SOUND SYSTEM
Overview of types

Table 1
COMB FILTER
2003 Nov 11
OVERVIEW OF THE VARIOUS VERSIONS
TDA12071H/H1
TDA12072H/H1(2)
TDA12073H/H1(2)
TDA12076H/H1
TDA12077H/H1
TDA12078H/H1
TDA12079H/H1
128/256
1.25 2.25
MULTI
128/256
1.25 2.25
MULTI
128/256
1.25 2.25
MULTI
128/256
1.25 2.25
MULTI
128/256
1.25 2.25
MULTI
128/256
1.25 2.25
MULTI
128/256
1.25 2.25
MULTI
128/256
1.25 2.25
MULTI
128/256
10
2.25
MULTI
128/256
10
2.25
MULTI
128/256
10
2.25
MULTI
128/256
10
2.25
MULTI
128/256
10
2.25
MULTI
128/256
10
2.25
MULTI
128/256
10
2.25
MULTI
128/256
10
2.25
TDA12069H/H1
MULTI

TDA12068H/H1
DRCS RAM (k)
DISPLAY RAM (k)
AUX RAM SIZE (k)
TDA12067H/H1
ROM SIZE (k)
DW / PANORAMA
TDA12070H/H1
8
CONFIDENTIAL
TDA12066H/H1
BBETM
TDA12063H/H1(2)
SRS TruSurround
SRS 3D Stereo
TDA12062H/H1(2)
Virtual Dolby (VDS)
TDA12061H/H1
Dolby ProLogic
dbx
TDA12060H/H1
10
RDS/RBDS
MONO FM RADIO
STEREO
AUDIO
DECOMONO
DSP
DER
STEREO FM RADIO
TYPE NUMBER(1)
COLOUR DECODER
NUMBER OF
TELETEXT
PAGES
COMB FILTER
2003 Nov 11
SOUND SYSTEM
Note
1. The standard version is indicated with H and the facedown version with H1
2. For these versions the feature content can be found from the type number. More details are given in the next Section.
3. When the BTSC demodulation is active the EIAJ demodulation is also activated.
UOCIII series

UOCIII series
Type Number Definition and Feature Indication

The complete type number of these versions is given below.
TDA12000H1/N1VXY0AA
The explanation of the various parts of the type number is given below:
The first 8 characters indicate the type number, the last 2 characters vary depending on the version.
The next 1 or 2 characters indicate the envelope. The normal QFP128 version is indicated with H and the face-down
version with H1.
The first 3 characters after the slash (/) indicate the IC version.
The characters X and Y give an indication of the Feature Content. More information is given in the Tables 2 and 3.
The last 3 characters give an indication of the ROM code.
Dolby ProLogic
Virtual Dolby (VDS)
SECOND INDICATION (Y)
SRS 3D Stereo
SRS TruSurround
BBETM
DW / PANORAMA
Feature Indication, second character (Y)
dbx
Table 3
ROM size / 0 = 128K
Feature Indication, first character (X)
FIRST INDICATION (X)
Table 2
2003 Nov 11
CONFIDENTIAL

UOCIII series
QUICK REFERENCE DATA

SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Supply
VP
analogue supply voltage TV processor
4.7
5.0
5.3
IP
supply current (5.0 V)
190
mA
VDDA
digital supply TV processor / analogue supply periphery
3.0
3.3
3.6
IDDA
36
mA
VDDC/P
digital supply to core/periphery
1.65
1.8
1.95
IDDC/P
440
mA
VPAudio (1)
audio supply voltage
4.7
8.0
8.4
supply current (5.0/8.0 V)
0.5
mA
total power dissipation
1.87
ViVIFrms)
video IF amplifier sensitivity (RMS value)
75
150
ViSIF(rms)
QSS sound IF amplifier sensitivity (RMS value)
45
tbf
dBV
ViSSIF(rms)
sound IF amplifier sensitivity (RMS value)
1.0
mV
ViAUDIO(rms)
external audio input (RMS value)
1.0
1.3
ViCVBS(p-p)
external CVBS/Y input (peak-to-peak value)
1.0
1.4
ViCHROMA(p-p)
external chroma input voltage (burst amplitude)

(peak-to-peak value)
0.3
1.0
ViRGB(p-p)
RGB inputs (peak-to-peak value)
0.7
0.8
IPAudio
(1)
Ptot
Input voltages
ViY(p-p)
luminance input signal (peak-to-peak value)
1.4 / 1.0
ViU(p-p) /
ViPB(p-p)
U / PB input signal (peak-to-peak value); note 2
1.33 /
+0.7
ViV(p-p) /
ViPR(p-p)
V / PR input signal (peak-to-peak value); note 2
1.05 /
+0.7
Vo(IFVO)(p-p)
demodulated CVBS output (peak-to-peak value)
2.0
Vo(QSSO)(rms)
sound IF intercarrier output (RMS value)
100
mV
Vo(AMOUT)(rms)
demodulated AM sound output (RMS value)
250
mV
non-controlled audio output signals (RMS value)
1.0
Output signals
Vo(AUDIO)(rms)
(1)
Vo(CVBSO)(p-p)
selected CVBS output (peak-to-peak value)
2.0
Io(AGCOUT)
tuner AGC output current range
mA
VoRGB(p-p)
RGB output signal amplitudes (peak-to-peak value)
1.2
IoHOUT
horizontal output current
10
mA
IoVERT
vertical output current (peak-to-peak value)
mA
IoEWD
EW drive output current
1.2
mA
Note
1. The supply voltage for the analogue audio part of the IC can be 5V or 8V. For a supply voltage of 5V the maximum
signal amplitudes at in and outputs are 1Vrms. For a supply voltage of 8V the maximum output signal amplitude is
2 Vrms.
2. The YUV/YPBPR input signal amplitudes are based on a colour bar signal with 75/100% saturation.
2003 Nov 11
10
CONFIDENTIAL
2003 Nov 11
CVBS3/Y3
C2/C3
CVBS4/Y4
C4
CVBSO/
PIP
IFVO/SVO/
CVBSI
YSYNC
CVBS2/Y2
VIFIN
AGCOUT
DVBO/IFVO/
FMRO
DVBO/FMRO
SIFIN/DVBIN
11
CONFIDENTIAL
H/V SYNC SEP.

H-OSC. + PLL
2nd LOOP
H-SHIFT
H-DRIVE
VIDEO FILTERS
VIDEO SWITCH
VIDEO IDENT.
H/V
SOUND PLL
SWO1 BL
R/PR B/PB
G/Y
B/PB
Ui Vi
SATURATION
U/V TINT
SKIN TONE
YUV
U/V DELAY
MODULATION
PEAKING
SCAN VELOCITY
SAT
BRI
CON.
SCAVEM
ON TEXT
GAMMA CONTROL
RGB MATRIX
BLUE STRETCH
BLACK STRETCH
RGB CONTROL
OSD/TEXT INSERT
CONTR/BRIGHTN
CCC
WHITE-P. ADJ.
BL R
CR
HP-OUT
DIGITAL SIGNAL PROCESSING FEATURES
R/PR
G/Y
(CVBSx/Yx) (Cx)
Yi
AUDIO CONTROL
VOLUME
TREBBLE/BASS
FEATURES
DACs
LS-OUT
RDS
I2S
-PROCESSOR AND TELETEXT DECODER
ADC/DAC
AUDIO SELECT
SCART/CINCH IN/OUT
Fig.1 Block diagram of the Stereo TV processor
EWD
EHTO BL
Vo Uo Yo
YUV INTERFACE
RGB/YPRPB INSERT
AM
YUV IN/OUT
V-DRIVE
GEOMETRY
& EAST-WEST
VERTICAL
Y DELAY ADJ.
DIGITAL
2H/4H
COMB FILTER
DELAY LINE
DECODER
REF
BASE-BAND
A/D CONVERTER
ALL-STANDARD
STEREO
DECODER
PAL/SECAM/NTSC
DEEMPHASIS
SSIF
SVM
BCLIN
BLKIN
BO
RO
GO
I/Os

HOUT
VISION IF/AGC/AFC
PLL DEMOD.
SOUND TRAP
GROUP DELAY
VIDEO AMP.
SWITCH
QSS SOUND IF
AGC
QSS MIXER
AM DEMODULATOR
REFO
QSSO/AMOUT
UOCIII series
BLOCK DIAGRAMS
2003 Nov 11
12
CONFIDENTIAL
CVBSO/
PIP
CVBS3/Y3
C2/C3
CVBS4/Y4
C4
IFVO/SVO/
CVBSI
YSYNC
CVBS2/Y2
VIFIN
AGCOUT
DVBO/IFVO/
FMRO
DVBO/FMRO
SIFIN/DVBIN
H/V SYNC SEP.

H-OSC. + PLL
2nd LOOP
H-SHIFT
H-DRIVE
VIDEO FILTERS
VIDEO SWITCH
VIDEO IDENT.
H/V
G/Y
SWO1 BL
R/PR B/PB
HP-OUT
RDS
SATURATION
SKIN TONE
U/V TINT
SCAN VELOCITY
MODULATION
U/V DELAY
PEAKING
SAT
BRI
CON.
SCAVEM
ON TEXT
GAMMA CONTROL
RGB MATRIX
BLUE STRETCH
BLACK STRETCH
RGB CONTROL
OSD/TEXT INSERT
CONTR/BRIGHTN
CCC
WHITE-P. ADJ.
BL R
R/PR
G/Y
(CVBSx/Yx) (Cx)
B/PB
AUDIO CONTROL
VOLUME
TREBBLE/BASS
FEATURES
DACs
LS-OUT
Fig.2 Block diagram of the AV-stereo TV processor with audio DSP
EWD
EHTO BL
Vo Uo Yo Yi Vi Ui
YUV INTERFACE
RGB/YPRPB INSERT
I2S
YUV IN/OUT
V-DRIVE
GEOMETRY
& EAST-WEST
VERTICAL
Y DELAY ADJ.
DIGITAL
2H/4H
COMB FILTER
DELAY LINE
ADC/DAC
DECODER
REF
AM
AUDIO SELECT
BASE-BAND
DEEMPHASIS
SOUND PLL
SCART/CINCH IN/OUT
PAL/SECAM/NTSC
SSIF
CR
SVM
BCLIN
BLKIN
BO
RO
GO
I/Os

HOUT
VISION IF/AGC/AFC
PLL DEMOD.
SOUND TRAP
GROUP DELAY
VIDEO AMP.
SWITCH
QSS SOUND IF
AGC
QSS MIXER
AM DEMODULATOR
REFO
QSSO/AMOUT
UOCIII series
2003 Nov 11
13
CONFIDENTIAL
CVBSO/
PIP
CVBS3/Y3
C2/C3
CVBS4/Y4
C4
IFVO/SVO/
CVBSI
YSYNC
CVBS2/Y2
VIFIN
AGCOUT
DVBO/IFVO/
FMRO
DVBO/FMRO
SIFIN/DVBIN
H/V SYNC SEP.

H-OSC. + PLL
2nd LOOP
H-SHIFT
H-DRIVE
VIDEO FILTERS
VIDEO SWITCH
VIDEO IDENT.
H/V
SWO1 BL
R/PR B/PB
RDS
SATURATION
SKIN TONE
U/V TINT
SCAN VELOCITY
MODULATION
U/V DELAY
PEAKING
SAT
BRI
CON.
SCAVEM
ON TEXT
GAMMA CONTROL
RGB MATRIX
BLUE STRETCH
BLACK STRETCH
RGB CONTROL
OSD/TEXT INSERT
CONTR/BRIGHTN
CCC
WHITE-P. ADJ.
BL R
R/PR
G/Y
(CVBSx/Yx) (Cx)
B/PB
VOLUME CONTROL
LS-OUT
Fig.3 Block diagram of the AV-stereo TV processor without audio DSP
EWD
EHTO BL
Vo Uo Yo Yi Vi Ui
YUV INTERFACE
RGB/YPRPB INSERT
YUV IN/OUT
V-DRIVE
GEOMETRY
& EAST-WEST
VERTICAL
2H/4H
COMB FILTER
Y DELAY ADJ.
DIGITAL
DELAY LINE
G/Y
AUDIO SELECT
DECODER
REF
AM
BASE-BAND
DEEMPHASIS
SOUND PLL
SCART/CINCH IN/OUT
PAL/SECAM/NTSC
SSIF
CR
SVM
BCLIN
BLKIN
BO
RO
GO
I/Os

HOUT
VISION IF/AGC/AFC
PLL DEMOD.
SOUND TRAP
GROUP DELAY
VIDEO AMP.
SWITCH
QSS SOUND IF
AGC
QSS MIXER
AM DEMODULATOR
REFO
QSSO/AMOUT
UOCIII series
2003 Nov 11
14
CONFIDENTIAL
CVBSO/PIP
YSYNC
C4
CVBS3/Y3
C2/C3
CVBS4/Y4
CVBS2/Y2
IFVO/SVO/
CVBSI
HOUT
G/Y
SWO1 BL
R/PR B/PB
BL
G/Y
YI
VI
(Cx)
B/PB R/PR
UI
(CVBS/Yx)
VO UO YO
YUV INTERFACE
RGB/YUV/YPRPB INSERT
PEAKING
SCAN VELOCITY
MODULATION
U/V DELAY
Fig. 4 Block diagram of the Mono TV processor
V-DRIVE (EWD) EHTO
AND DRIVE
U/V
DELAY LINE
BASE-BAND
YUV
BL
GAMMA CONTROL
SKIN TONE
U/V TINT
SATURATION
BLACK STRETCH
CONTR/BRIGHTN
OSD/TEXT INSERT
BLUE STRETCH
CCC
WHITE-P. ADJ.
COR
SCAVEM
ON TEXT
BLKIN
BCLIN
BO
GO
RO
SVM

(REFO)
GEOMETRY
VERTICAL + EW
COMB FILTER
Y DELAY ADJ.
4H/2H
DIGITAL
REF
RDS
YUV IN/OUT
H-DRIVE
H/V SYNC SEP.

H-OSC. + PLL
2nd LOOP
H-SHIFT
VIDEO FILTERS
VIDEO IDENT.
VIDEO SWITCH
DECODER
PAL/SECAM/NTSC
AUDOUT/AMOUT
VIFIN
VISION IF/AGC/AFC
REF
PLL DEMOD.
DVB MIXER
GROUP DELAY
SOUND TRAP
(SSIF)
AGCOUT
QSSO/AMOUT
AUDEEM
DVBO/IFVO
FMRO
SIFIN/DVBIN
(AVL)
SOUND PLL
DEEMPHASIS
AUDIO SWITCH
AVL
VOLUME CONTROL
AUDIO3
AUDIO2
SWITCH
AUDIO5
AUDIO4
QSS SOUND IF
AGC
QSS MIXER
AM DEMODULATOR
I/Os
UOCIII series
STEREO +
AV STEREO
AV STEREO
NO AUDIO DSP
MONO
128
128
128
ground
VSSC4
127
127
127
ground
VDDC4
126
126
126
digital supply to SDACs (1.8V)
VDDA3(3.3V)
125
125
125
supply (3.3 V)
VREF_POS_LSL
124
positive reference voltage SDAC (3.3 V)
VREF_NEG_LSL+HPL
123
negative reference voltage SDAC (0 V)
VREF_POS_LSR+HPR
122
VREF_NEG_HPL+HPR
121
negative reference voltage SDAC (0 V)
VREF_POS_HPR
120
XTALIN
10
10
10
119
119
119
crystal oscillator input
XTALOUT
11
11
11
118
118
118
crystal oscillator output
VSSA1
12
12
12
117
117
117
ground
VGUARD/SWIO
13
13
13
116
116
116
V-guard input / I/O switch (e.g. 4 mA current sinking capability for

direct drive of LEDs)
DECDIG
14
14
14
115
115
115
decoupling digital supply
VP1
15
15
15
114
114
114
1st supply voltage TV-processor (+5 V)
PH2LF
16
16
16
113
113
113
phase-2 filter
PH1LF
17
17
17
112
112
112
phase-1 filter
GND1
18
18
18
111
111
111
ground 1 for TV-processor
SECPLL
19
19
19
110
110
110
SECAM PLL decoupling
DECBG
20
20
20
109
109
109
bandgap decoupling
EWD/AVL (1)
21
21
21
108
108
108
East-West drive output or AVL capacitor
15
CONFIDENTIAL
MONO
DESCRIPTION
UOCIII series
AV STEREO
NO AUDIO DSP
VSSP2
SYMBOL
FACE DOWN
VERSION

STANDARD
VERSION
STEREO +
AV STEREO
2003 Nov 11
PINNING OF THE VARIOUS VERSIONS
MONO
STEREO +
AV STEREO
AV STEREO
NO AUDIO DSP
MONO
22
22
107
107
107
vertical drive B output
VDRA
23
23
23
106
106
106
vertical drive A output
VIFIN1
24
24
24
105
105
105
IF input 1
VIFIN2
25
25
25
104
104
104
IF input 2
VSC
26
26
26
103
103
103
vertical sawtooth capacitor
IREF
27
27
27
102
102
102
reference current input
GNDIF
28
28
28
101
101
101
ground connection for IF amplifier
SIFIN1/DVBIN1 (2)
29
29
29
100
100
100
SIF input 1 / DVB input 1
SIFIN2/DVBIN2 (2)
30
30
30
99
99
99
SIF input 2 / DVB input 2
AGCOUT
31
31
31
98
98
98
tuner AGC output
EHTO
32
32
32
97
97
97
EHT/overvoltage protection input
AVL/SWO/SSIF/
REFO/REFIN (2)(3)
33
33
33
96
96
96
Automatic Volume Levelling / switch output / sound IF input /

subcarrier reference output / external reference signal input for I
signal mixer for DVB operation
AUDIOIN5
34
95
audio 5 input
AUDIOIN5L
34
34
95
95
audio-5 input (left signal)
AUDIOIN5R
35
35
94
94
audio-5 input (right signal)
AUDOUTSL
36
36
93
93
audio output for SCART/CINCH (left signal)
AUDOUTSR
37
37
92
92
audio output for SCART/CINCH (right signal)
38
38
38
91
91
91
decoupling sound demodulator
39
39
39
90
90
90
QSS intercarrier output / AM output / deemphasis (front-end audio

out)
40
40
40
89
89
89
ground 2 for TV processor
DECSDEM
QSSO/AMOUT/AUDEEM
GND2
(2)
AV STEREO
NO AUDIO DSP
22
DESCRIPTION
UOCIII series
STEREO +
AV STEREO
16
CONFIDENTIAL
VDRB
SYMBOL
FACE DOWN
VERSION

2003 Nov 11
STANDARD
VERSION
MONO
STEREO +
AV STEREO
AV STEREO
NO AUDIO DSP
MONO
41
88
88
88
IF-PLL loop filter
42
42
42
87
87
87
AGC sound IF / internal-external AGC for DVB applications
43
43
43
86
86
86
Digital Video Broadcast output / IF video output / FM radio output
44
44
85
85
Digital Video Broadcast output / FM radio output
VCC8V
45
45
45
84
84
84
8 Volt supply for audio switches
AGC2SIF
46
83
AGC capacitor second sound IF
VP2
47
47
47
82
82
82
2nd supply voltage TV processor (+5 V)
IFVO/SVO/CVBSI (2)
48
48
48
81
81
81
IF video output / selected CVBS output / CVBS input
AUDIOIN4
49
80
audio 4 input
AUDIOIN4L
49
49
80
80
audio-4 input (left signal)
AUDIOIN4R
50
50
79
79
audio-4 input (right signal)
CVBS4/Y4
51
51
51
78
78
78
CVBS4/Y4 input
C4
52
52
52
77
77
77
chroma-4 input
53
76
audio 2 input
53
53
76
76
audio 2 input (left signal) / sound IF input
AUDIOIN2R
54
54
75
75
audio 2 input (right signal)
CVBS2/Y2
55
55
55
74
74
74
CVBS2/Y2 input
AUDIOIN3
56
73
audio 3 input
AUDIOIN3L
56
56
73
73
audio 3 input (left signal)
AUDIOIN3R
57
57
72
72
audio 3 input (right signal)
CVBS3/Y3
58
58
58
71
71
71
CVBS3/Y3 input
C2/C3
59
59
59
70
70
70
chroma-2/3 input
SIFAGC/DVBAGC (2)
DVBO/IFVO/FMRO
17
CONFIDENTIAL
DVBO/FMRO
(2)
(2)
AUDIOIN2
AUDIOIN2L/SSIF
(3)
AV STEREO
NO AUDIO DSP
41
PLLIF
DESCRIPTION
UOCIII series
STEREO +
AV STEREO
41
SYMBOL
FACE DOWN
VERSION

2003 Nov 11
STANDARD
VERSION
MONO
STEREO +
AV STEREO
AV STEREO
NO AUDIO DSP
MONO
62
69
67
audio output for audio power amplifier (left signal)
AUDOUTLSR
61
63
68
66
audio output for audio power amplifier (right signal)
AUDOUT/AMOUT/FMOUT
62
67
audio output / AM output / FM output, volume controlled
AUDOUTHPL
62
67
audio output for headphone channel (left signal)
AUDOUTHPR
63
66
audio output for headphone channel (right signal)
CVBSO/PIP
64
64
64
65
65
65
CVBS / PIP output
SVM
65
65
65
64
64
64
scan velocity modulation output
FBISO/CSY
66
66
66
63
63
63
flyback input/sandcastle output or composite H/V timing output
HOUT
67
67
67
62
62
62
horizontal output
VSScomb
68
68
68
61
61
61
ground connection for comb filter
VDDcomb
69
69
69
60
60
60
supply voltage for comb filter (5 V)
VIN (R/PRIN2/CX)
70
70
70
59
59
59
V-input for YUV interface (2nd R input / PR input or CX input)
UIN (B/PBIN2)
71
71
71
58
58
58
U-input for YUV interface (2nd B input / PB input)
YIN (G/YIN2/CVBS-YX)
72
72
72
57
57
57
Y-input for YUV interface (2nd G input / Y input or CVBS/YX input))
YSYNC
73
73
73
56
56
56
Y-input for sync separator
YOUT
74
74
74
55
55
55
Y-output (for YUV interface)
UOUT (INSSW2)
75
75
75
54
54
54
U-output for YUV interface (2nd RGB / YPBPR insertion input)
VOUT (SWO1)
76
76
76
53
53
53
V-output for YUV interface (general purpose switch output)
INSSW3
77
77
77
52
52
52
3rd RGB / YPBPR insertion input
R/PRIN3
78
78
78
51
51
51
3rd R input / PR input
G/YIN3
79
79
79
50
50
50
3rd G input / Y input
B/PBIN3
80
80
80
49
49
49
3rd B input / PB input
AV STEREO
NO AUDIO DSP
60
DESCRIPTION
UOCIII series
STEREO +
AV STEREO
18
CONFIDENTIAL
AUDOUTLSL
SYMBOL
FACE DOWN
VERSION

2003 Nov 11
STANDARD
VERSION
MONO
STEREO +
AV STEREO
AV STEREO
NO AUDIO DSP
MONO
81
48
48
48
ground 3 for TV-processor
VP3
82
82
82
47
47
47
3rd supply for TV processor
BCLIN
83
83
83
46
46
46
beam current limiter input
BLKIN
84
84
84
45
45
45
black current input
RO
85
85
85
44
44
44
Red output
GO
86
86
86
43
43
43
Green output
BO
87
87
87
42
42
42
Blue output
VDDA1
88
88
88
41
41
41
analog supply for TCG -Controller and digital supply for

TV-processor (+3.3 V)
VREFAD_NEG
89
89
89
40
40
40
negative reference voltage (0 V)
VREFAD_POS
90
90
90
39
39
39
positive reference voltage (3.3 V)
VREFAD
91
38
reference voltage for audio ADCs (3.3/2 V)
GNDA
92
92
92
37
37
37
ground
VDDA(1.8V)
93
93
93
36
36
36
analogue supply for audio ADCs (1.8 V)
VDDA2(3.3)
94
94
94
35
35
35
supply voltage SDAC (3.3 V)
VSSadc
95
95
95
34
34
34
ground for video ADC and PLL
VDDadc(1.8)
96
96
96
33
33
33
supply voltage video ADC and PLL
INT0/P0.5
97
97
97
32
32
32
external interrupt 0 or port 0.5 (4 mA current sinking capability for

direct drive of LEDs)
P1.0/INT1
98
98
98
31
31
31
port 1.0 or external interrupt 1
P1.1/T0
99
99
99
30
30
30
port 1.1 or Counter/Timer 0 input
VDDC2
100
100
100
29
29
29
digital supply to core (1.8 V)
VSSC2
101
101
101
28
28
28
ground
AV STEREO
NO AUDIO DSP
81
DESCRIPTION
UOCIII series
STEREO +
AV STEREO
81
19
CONFIDENTIAL
GND3
SYMBOL
FACE DOWN
VERSION

2003 Nov 11
STANDARD
VERSION
MONO
STEREO +
AV STEREO
AV STEREO
NO AUDIO DSP
MONO
27
port 0.4 or I2S word select
102
102
27
27
port 0.4
103
26
port 0.3 or I2S clock
103
103
26
26
port 0.3
104
25
port 0.2 or I2S digital output 2
104
104
25
25
port 0.2
105
24
port 0.1 or I2S digital output 1
105
105
24
24
port 0.1
106
23
port 0.0 or I2S digital input 1 or I2S digital output
106
106
23
23
port 0.0
P1.3/T1
107
107
107
22
22
22
port 1.3 or Counter/Timer 1 input
P1.6/SCL
108
108
108
21
21
21
port 1.6 or I2C-bus clock line
P1.7/SDA
109
109
109
20
20
20
port 1.7 or I2C-bus data line
VDDP(3.3V)
110
110
110
19
19
19
supply to periphery and on-chip voltage regulator (3.3 V)
P2.0/TPWM
111
111
111
18
18
18
port 2.0 or Tuning PWM output
P2.1/PWM0
112
112
112
17
17
17
port 2.1 or PWM0 output
P2.2/PWM1
113
113
113
16
16
16
P2.3/PWM2
114
114
114
15
15
15
P3.0/ADC0
115
115
115
14
14
14
port 3.0 or ADC0 input
P3.1/ADC1
116
116
116
13
13
13
VDDC1
117
117
117
12
12
12
digital supply to core (+1.8 V)
DECV1V8
118
118
118
11
11
11
decoupling 1.8 V supply
P0.4
P0.3/I2SCLK
P0.2/I2SDO2
P0.2
P0.1/I2SDO1
P0.1
20
CONFIDENTIAL
P0.3
P0.0/I2SDI1/O
P0.0
AV STEREO
NO AUDIO DSP
P0.4/I2SWS
DESCRIPTION
UOCIII series
STEREO +
AV STEREO
102
SYMBOL
FACE DOWN
VERSION

2003 Nov 11
STANDARD
VERSION
STEREO +
AV STEREO
AV STEREO
NO AUDIO DSP
MONO
STEREO +
AV STEREO
AV STEREO
NO AUDIO DSP
MONO
21
CONFIDENTIAL
P3.2/ADC2
119
119
119
10
10
10
P3.3/ADC3
120
120
120
VSSC/P
121
121
121
digital ground for -Controller core and periphery
P2.4/PWM3
122
122
122
P2.5/PWM4
123
123
123
VDDC3
124
124
124
digital supply to core (1.8V)
VSSC3
125
125
125
ground
P1.2/INT2
126
126
126
port 1.2 or external interrupt 2
P1.4/RX
127
127
127
port 1.4 or UART bus
P1.5/TX
128
128
128
port 1.5 or UART bus
SYMBOL
DESCRIPTION
FACE DOWN
VERSION

2003 Nov 11
STANDARD
VERSION
Note
1. The function of this pin can be chosen by means of the AVLE bit.
2. The functional content of these pins is dependent on the mode of operation and on some I2C-bus control bits. More details are given in table 4.
3. With the ESSIF bit the SSIF input can be selected either on pin 33 or pin 53. For the face down versions these pin numbers are 96 and 76
respectively.
UOCIII series
ANALOGUE TV MODE
IC MODE
DVB MODE
FM-PLL MODE
(QSS = 0)
FM
DEMODULATION
FUNCTION
IFA/IFB/IFC bits
000/001/010/011/100/110
FMI bit
AVLE bit
CMB2/CMB1/CMB0 bits
010/011
100
101/111
000/001/010/011/101/110
22
CONFIDENTIAL
AM bit
FM RADIO MODE
QSS-FM
DEMODULATION
QSS/AM DEMODULATION
101/111
FMR bit
Standard
QSS MODE (QSS = 1)
Face-down
pin 21
pin 108
pin 29
pin 100
DVBIN1
SIFIN1
SIFIN1
pin 30
pin 99
DVBIN2
SIFIN2
SIFIN2
pin 33
(1)
pin 96
(1)
AVL
EWD
SWO
REFIN
AVL
EWD
SWO/
SSIF/
REFO
AVL/
SWO/
SSIF/
REFO
AVL
EWD
SWO/SSIF/REFO
AVL/SWO/SSIF/
REFO
QSSO
QSSO
AVL
SWO/
SSIF/
REFO
EWD
AVL/
SWO/
SSIF/
REFO
AVL
SWO/
SSIF/
REFO
EWD
AVL/
SWO/
SSIF/
REFO
pin 39
pin 90
AUDEEM
pin 42
pin 87
DVBAGC
SIFAGC
SIFAGC
DVBO
IFVO
IFVO
FMRO
pin 43
(2)
pin 44
(2)
pin 86
(2)
pin 85
(2)
AMOUT
AMOUT
AUDEEM
AUDEEM
DVBO
FMRO
pin 48 (3)
pin 81 (3)
SVO/CVBSI
IFVO/SVO/CVBSI
IFVO/SVO/CVBSI
IFVO/SVO/CVBSI
pin 62 (4)
pin 67 (4)
AUDOUT
AUDOUT
AUDOUT AMOUT AUDOUT AMOUT
AUDOUT
Pin functions for various modes of operation

2003 Nov 11
Table 4
AUDOUT
2. The functions of the pins 43/44 (standard pinning) or 85/86 (face-down pinning) are controlled by the IFO2-IFO0 bits in subaddress 31H.
3. The function of this pin is determined by the SVO1/SVO0 bits in subaddress 39H.
4. This functionality is only valid for the mono versions. In the stereo and AV-stereo versions this pin has the function of audio output for the
headphone channel (left signal).
UOCIII series
1. The function of this pin is controlled by the bits CMB2-CMB0 in subaddress 4AH.
Note
97 INT0/P0.5
101 VSSC2
100 VDDC2
99 P1.1/T0
98 P1.O/INT1
P1.7/SDA
P1.6/SCL
P1.3/T1
107
106 P0.0/I2SDI1
P0.1/I2SDO1
105
104 P0.2/I2SDO2
103 P0.3/I2SCLK
102 P0.4/I2SWS
P2.2/PWM1
P2.1/PWM0
P2.0/PMW
VDDP(3.3V)
UOCIII series
113
112
111
110
109
108
118 DECV1V8
117 VDDC1(1.8)
116 P3.1/ADC1
P3.0/ADC0
115
114 P2.3/PWM2
127 P1.4/RX
126 P1.2/INT2
125 VSSC3
124 VDDC3
123 P2.5/PWM4
122 P2.4/PWM3
121 VSSC1/P
120 P3.3/ADC3
119 P3.2/ADC2
128 P1.5/TX

VDDadc(1.8)
95 VSSadc
94 VDDA2(3.3V)
93 VDDA(1.8V)
92 GNDA
96
VSSP2 1
VSSC4 2
VDDC4 3
VDDA3(3.3V) 4
VREF_POS_LSL 5
VREF_NEG_LSL+LSR 6
VREF_POS_LSR+HPL 7
VREF_NEG_HPL+HPR 8
VREF_POS_HPR 9
91 VREFAD
90 VREFAD_POS
89 VREFAD_NEG
88 VDDA1(3.3V.)
87 BO
86 GO
XTALIN 10
XTALOUT 11
VSSA1 12
VGUARD/SWIO 13
DECDIG 14
VP1 15
PH2LF 16
PH1LF 17
GND1 18
SECPLL 19
DECBG 20
77
76
75
74
73
72
71
70
69
68
67
66
65
60
61
62
63
CVBSO/PIP 64
59
C2/C3
AUDOUTLSL
AUDOUTLSR
AUDOUTHPL
AUDOUTHPR
52
AUDIOIN2L 53
AUDIOIN2R/SSIF 54
CVBS2/Y2 55
AUDIOIN3L 56
AUDIOIN3R 57
CVBS3/Y3 58
51
49
50
AUDIOIN4L
AUDIOIN4R
CVBS4/Y4
C4
47
48
43
44
45
46
AGC2SIF
VP2
SVO/IFOUT/CVBSI
PLLIF
SIFAGC/DVBAGC
DVBO//IFVO/FMRO
DVBO/FMRO
VCC8V
GND2
AVL/SWO/SSIF/
REFIN/REFOUT
AUDIOIN5L
AUDIOIN5R
AUDOUTSL
AUDOUTSR
DECSDEM
AMOUT/QSSO/AUDEEM
41
42
QFP-128 0.8mm pitch standard version

33
34
AGCOUT
EHTO
39
40
GNDIF
DVBIN1/SIFIN1
DVBIN2/SIFIN2
21
22
23
24
25
26
27
28
29
30
31
32
82 VP3
81 GND3
80 B/PB-3
79 G/Y-3
78 R/PR-3
35
36
37
38
AVL/EWD
VDRB
VDRA
VIFIN1
VIFIN2
VSC
IREF
RO
BLKIN
84
83 BCLIN
85
Fig.5 Pin configuration stereo and AV-stereo versions with Audio DSP
2003 Nov 11
23
CONFIDENTIAL
INSSW3
VOUT(SWO1)
UOUT(INSW-2)
YOUT
YSYNC
YIN(G/Y-2/CVBS/Y-X)
UIN (B/PB-2)
VIN(R/PR-2/C-X)
VDDcomb
VSScomb
HOUT
FBISO/CSY
SVM
85 RO
84 BLKIN
83 BCLIN
82 VP3
81 GND3
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
CVBS3/Y3
C2/C3 59
- 60
- 61
AUDOUTLSL 62
AUDOUTLSR 63
CVBSO/PIP 64
AUDIOIN3L
AUDIOIN3R
AUDIOIN2R
CVBS2/Y2
52
53
54
55
56
57
58
AUDIOIN2L/SSIF
51
49
50
AUDIOIN4L
AUDIOIN4R
CVBS4/Y4
C4
AVL/SWO/SSIF/
REFIN/REFOUT
AUDIOIN5L
AUDIOIN5R
AUDOUTSL
AUDOUTSR
DECSDEM
AMOUT/QSSO/AUDEEM
47
48

33
34
11
12
13
14
VP1 15
PH2LF 16
PH1LF 17
GND1 18
SECPLL 19
DECBG 20
AVL/EWD 21
VDRB 22
VDRA 23
VIFIN1 24
VIFIN2 25
VSC 26
IREF 27
GNDIF 28
DVBIN1/SIFIN1 29
DVBIN2/SIFIN2 30
AGCOUT 31
EHTO 32
Fig.6 Pin configuration of AV stereo versions without Audio DSP
2003 Nov 11
97 INT0/P0.5
P0.3
P0.4
VSSC2
VDDC2
99 P1.1/T0
98 P1.O/INT1
P0.2
104
103
102
101
100
107 P1.3/T1
106 P0.0
105 P0.1
P1.7/SDA
P1.6/SCL
P2.2/PWM1
P2.1/PWM0
P2.0/PMW
VDDP(3.3V)
113
112
111
110
109
108
VSSC1/P
P3.3/ADC3
119 P3.2/ADC2
118 DECV1V8
117 VDDC1(1.8)
116 P3.1/ADC1
P3.0/ADC0
115
114 P2.3/PWM2
VDDC3
P2.5/PWM4
P2.4/PWM3
123
122
121
120
124
9
10
VP2
SVO/IFOUT/CVBSI
XTALIN
XTALOUT
VSSA1
VGUARD/SWIO
DECDIG
41
SIFAGC/DVBAGC 42
DVBO//IFVO/FMRO 43
- 44
VCC8V 45
- 46
91 90 VREFAD_POS
89 VREFAD_NEG
88 VDDA1(3.3V.)
87 BO
86 GO
PLLIF
3
4
5
6
7
8
39
40
VDDadc(1.8)
95 VSSadc
94 VDDA2(3.3V)
93 VDDA(1.8V)
92 GNDA
96
GND2
VDDA3(3.3V)
-
UOCIII series
1
2
35
36
37
38
VSSP2
VSSC4
VDDC4
127 P1.4/RX
126 P1.2/INT2
125 VSSC3
128 P1.5/TX

24
CONFIDENTIAL
B/PB-3
G/Y-3
R/PR-3
INSSW3
VOUT(SWO1)
UOUT(INSW-2)
YOUT
YSYNC
YIN(G/Y-2/CVBS/Y-X)
UIN (B/PB-2)
VIN(R/PR-2/C-X)
VDDcomb
VSScomb
HOUT
FBISO/CSY
SVM
VSSP2
VSSC4
VDDC4
VDDA3(3.3V)
-
97 INT0/P0.5
P0.3
P0.4
VSSC2
VDDC2
99 P1.1/T0
98 P1.O/INT1
P0.2
104
103
102
101
100
107 P1.3/T1
106 P0.0
105 P0.1
P1.7/SDA
P1.6/SCL
P2.2/PWM1
P2.1/PWM0
P2.0/PMW
VDDP(3.3V)
UOCIII series
113
112
111
110
109
108
118 DECV1V8
117 VDDC1(1.8)
116 P3.1/ADC1
P3.0/ADC0
115
P2.3/PWM2
114
127 P1.4/RX
126 P1.2/INT2
125 VSSC3
124 VDDC3
123 P2.5/PWM4
122 P2.4/PWM3
121 VSSC1/P
120 P3.3/ADC3
119 P3.2/ADC2
128 P1.5/TX

VDDadc(1.8)
95 VSSadc
94 VDDA2(3.3V)
93 VDDA(1.8V)
92 GNDA
91 90 VREFAD_POS
89 VREFAD_NEG
96
1
2
3
4
5
6
7
8
88 VDDA1(3.3V.)
87 BO
86 GO
9
XTALIN 10
XTALOUT 11
VSSA1 12
VGUARD/SWIO 13
DECDIG 14
VP1 15
PH2LF 16
PH1LF 17
GND1 18
SECPLL 19
DECBG 20
25
CONFIDENTIAL
60
61
AUDOUT/AMOUT 62
- 63
CVBSO/PIP 64
-
52
AUDIOIN2 53
- 54
CVBS2/Y2 55
AUDIOIN3 56
- 57
CVBS3/Y3 58
C2/C3 59
51
AUDIOIN4
CVBS4/Y4
C4
47
48
VP2
SVO/IFOUT/CVBSI
49
50
43
44
45
46
PLLIF
41
42
SIFAGC/DVBAGC
DVBO//IFVO/FMRO
VCC8V
-
39
40
GND2
AVL/SWO/SSIF/
REFIN/REFOUT
AUDIOIN5
-
Fig.7 Pin configuration mono versions
2003 Nov 11
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

33
34
AGCOUT
EHTO
DECSDEM
AMOUT/QSSO/AUDEEM
GNDIF
DVBIN1/SIFIN1
DVBIN2/SIFIN2
21
22
23
24
25
26
27
28
29
30
31
32
80
35
36
37
38
AVL/EWD
VDRB
VDRA
VIFIN1
VIFIN2
VSC
IREF
85 RO
84 BLKIN
83 BCLIN
82 VP3
81 GND3
B/PB-3
G/Y-3
R/PR-3
INSSW3
VOUT(SWO1)
UOUT(INSW-2)
YOUT
YSYNC
YIN(G/Y-2/CVBS/Y-X)
UIN (B/PB-2)
VIN(R/PR-2/C-X)
VDDcomb
VSScomb
HOUT
FBISO/CSY
SVM
97 EHTO
99 DVBIN2/SIFIN2
98 AGCOUT
IREF
GNDIF
DVBIN1/SIFIN1
VIFIN1
VIFIN2
VSC
105
104
103
102
101
100
107 VDRB
106 VDRA
DECBG
AVL/EWD
PH1LF
GND1
SECPLL
DECDIG
VP1
PH2LF
UOCIII series
115
114
113
112
111
110
109
108
119 XTALIN
118 XTALOUT
117 VSSA1
116 VGUARD/SWIO
122 VREF_POS_LSR+HPL
121 VREF_NEG_HPL+HPR
120 VREF_POS_HPR
127 VSSC4
126 VDDC4
125 VDDA3(3.3V)
124 VREF_POS_LSL
123 VREF_NEG_LSL+LSR
128 VSSP2

AVL/SWO/SSIF/
96 REFIN/REFOUT
P1.5/TX 1
P1.4/RX 2
P1.2/INT2 3
VSSC3 4
VDDC3 5
P2.5/PWM4 6
P2.4/PWM3 7
VSSC1/P 8
95 AUDIOIN5L
94 AUDIOIN5R
93 AUDOUTSL
92 AUDOUTSR
91 DECSDEM
90 AMOUT/QSSO/AUDEEM
89 GND2
P3.3/ADC3
88 PLLIF
9
P3.2/ADC2 10
DECV1V8 11
VDDC1(1.8) 12
P3.1/ADC1 13
P3.0/ADC0 14
P2.3/PWM2 15
P2.2/PWM1 16
P2.1/PWM0 17
P2.0/PMW 18
VDDP(3.3V) 19
P1.7/SDA 20
QFP-128 0.8 mm pitch face down version

VDDadc(1.8) 33
VSSadc 34
VDDA2(3.3V) 35
VDDA(1.8V) 36
INT0/P0.5
74
73
72
71
70
69
68
67
66
65
CVBS2/Y2
AUDIOIN3L
AUDIOIN3R
CVBS3/Y3
C2/C3
AUDOUTLSL
AUDOUTLSR
AUDOUTHPL
AUDOUTHPR
CVBSO/PIP
VIN(R/PR-2/C-X) 59
VDDcomb 60
VSScomb 61
HOUT 62
FBISO/CSY 63
SVM 64
VSSC2
VDDC2
P1.1/T0
P1.O/INT1
INSSW3 52
VOUT(SWO1) 53
UOUT(INSW-2) 54
YOUT 55
YSYNC 56
YIN(G/Y-2/CVBS/Y-X) 57
UIN (B/PB-2) 58
P0.4/I2SWS
VP3 47
GND3 48
B/PB-3 49
G/Y-3 50
R/PR-3 51
P0.3/I2SCLK
VDDA1(3.3V.) 41
BO 42
GO 43
RO 44
BLKIN 45
BCLIN 46
P0.2/I2SDO2
21
22
23
24
25
26
27
28
29
30
31
32
84 VCC8V
83 AGC2SIF
82 VP2
81 SVO/IFOUT/CVBSI
80 AUDIOIN4L
79 AUDIOIN4R
78 CVBS4/Y4
77 C4
76 AUDIOIN2L/SSIF
75 AUDIOIN2R
GNDA 37
VREFAD 38
VREFAD_POS 39
VREFAD_NEG 40
P1.6/SCL
P1.3/T1
P0.0/I2SDI1
P0.1/I2SDO1
87 SIFAGC/DVBAGC
86 DVBO//IFVO/FMRO
85 DVBO/FMRO
Fig.8 Pin configuration stereo and AV-stereo versions with Audio DSP
2003 Nov 11
26
CONFIDENTIAL
97 EHTO
99 DVBIN2/SIFIN2
98 AGCOUT
IREF
GNDIF
DVBIN1/SIFIN1
VIFIN1
VIFIN2
VSC
105
104
103
102
101
100
107 VDRB
106 VDRA
DECBG
AVL/EWD
PH1LF
GND1
SECPLL
DECDIG
VP1
PH2LF
UOCIII series
115
114
113
112
111
110
109
108
XTALIN
118 XTALOUT
117 VSSA1
116 VGUARD/SWIO
120 -
119
VSSC4
126 VDDC4
125 VDDA3(3.3V)
124 123 122 121 127
128
VSSP2

AVL/SWO/SSIF/
96 REFIN/REFOUT
P1.5/TX 1
P1.4/RX 2
P1.2/INT2 3
VSSC3 4
VDDC3 5
P2.5/PWM4 6
P2.4/PWM3 7
VSSC1/P 8
95 AUDIOIN5L
94 AUDIOIN5R
93 AUDOUTSL
92 AUDOUTSR
91 DECSDEM
89 GND2
P3.3/ADC3
88 PLLIF
87 SIFAGC/DVBAGC
86 DVBO//IFVO/FMRO
85 84 VCC8V
83 82 VP2
81 SVO/IFOUT/CVBSI
80 AUDIOIN4L
79 AUDIOIN4R
78 CVBS4/Y4
77 C4
76 AUDIOIN2L/SSIF
75 AUDIOIN2R
74
73
72
71
70
69
68
67
66
65
VIN(R/PR-2/C-X) 59
VDDcomb 60
VSScomb 61
HOUT 62
FBISO/CSY 63
SVM 64
INSSW3 52
VOUT(SWO1) 53
UOUT(INSW-2) 54
YOUT 55
YSYNC 56
UIN (B/PB-2) 58
VP3 47
GND3 48
B/PB-3 49
G/Y-3 50
R/PR-3 51
VREFAD_POS 39
VREFAD_NEG 40
VDDA1(3.3V.) 41
BO 42
GO 43
RO 44
BLKIN 45
BCLIN 46
VDDA2(3.3V) 35
VDDA(1.8V) 36
GNDA 37
- 38
QFP-128 0.8mm pitch face down version

VDDadc(1.8) 33
VSSadc 34
9
P3.2/ADC2 10
DECV1V8 11
VDDC1(1.8) 12
P3.1/ADC1 13
P3.0/ADC0 14
P2.3/PWM2 15
P2.2/PWM1 16
P2.1/PWM0 17
P2.0/PMW 18
VDDP(3.3V) 19
P1.7/SDA 20
P1.6/SCL 21
P1.3/T1 22
P0.0 23
P0.1 24
P0.2 25
P0.3 26
P0.4 27
VSSC2 28
VDDC2 29
P1.1/T0 30
P1.O/INT1 31
INT0/P0.5 32
Fig.9 Pin configuration of AV stereo versions without Audio DSP
2003 Nov 11
27
CVBS2/Y2
AUDIOIN3L
AUDIOIN3R
CVBS3/Y3
C2/C3
AUDOUTLSL
AUDOUTLSR
CVBSO/PIP
97 EHTO
99 DVBIN2/SIFIN2
98 AGCOUT
IREF
GNDIF
DVBIN1/SIFIN1
VIFIN1
VIFIN2
VSC
105
104
103
102
101
100
107 VDRB
106 VDRA
DECBG
AVL/EWD
PH1LF
GND1
SECPLL
DECDIG
VP1
PH2LF
UOCIII series
115
114
113
112
111
110
109
108
XTALIN
118 XTALOUT
117 VSSA1
116 VGUARD/SWIO
120 -
119
127 VSSC4
126 VDDC4
125 VDDA3(3.3V)
124 123 122 121 -
128 VSSP2

AVL/SWO/SSIF/
96 REFIN/REFOUT
P1.5/TX 1
P1.4/RX 2
P1.2/INT2 3
VSSC3 4
VDDC3 5
P2.5/PWM4 6
P2.4/PWM3 7
VSSC1/P 8
95 AUDIOIN5
94 93 92 91 DECSDEM
89 GND2
P3.3/ADC3
88 PLLIF
87 SIFAGC/DVBAGC
86 DVBO//IFVO/FMRO
85 84 VCC8V
83 82 VP2
81 SVO/IFOUT/CVBSI
80 AUDIOIN4
79 78 CVBS4/Y4
77 C4
76 AUDIOIN2
75 -
28
CONFIDENTIAL
HOUT 62
FBISO/CSY 63
SVM 64
INSSW3 52
VOUT(SWO1) 53
UOUT(INSW-2) 54
YOUT 55
YSYNC 56
UIN (B/PB-2) 58
VIN(R/PR-2/C-X) 59
VDDcomb 60
VSScomb 61
VP3 47
GND3 48
B/PB-3 49
G/Y-3 50
R/PR-3 51
VDDA1(3.3V.) 41
BO 42
GO 43
RO 44
BLKIN 45
BCLIN 46
39
40
37
38
GNDA
VREFAD_POS
VREFAD_NEG
Fig.10 Pin configuration mono versions
2003 Nov 11
74
73
72
71
70
69
68
67
66
65
QFP-128 0.8mm pitch face down version

VDDadc(1.8) 33
VSSadc 34
VDDA2(3.3V) 35
VDDA(1.8V) 36
9
P3.2/ADC2 10
DECV1V8 11
VDDC1(1.8) 12
P3.1/ADC1 13
P3.0/ADC0 14
P2.3/PWM2 15
P2.2/PWM1 16
P2.1/PWM0 17
P2.0/PMW 18
VDDP(3.3V) 19
P1.7/SDA 20
P1.6/SCL 21
P1.3/T1 22
P0.0 23
P0.1 24
P0.2 25
P0.3 26
P0.4 27
VSSC2 28
VDDC2 29
P1.1/T0 30
P1.O/INT1 31
INT0/P0.5 32
CVBS2/Y2
AUDIOIN3
CVBS3/Y3
C2/C3
AUDOUT/AMOUT
CVBSO/PIP

UOCIII series
FUNCTIONAL DESCRIPTION OF THE 80C51

The functionality of the micro-controller used on this
device is described here with reference to the industry
standard 80C51 micro-controller. A full description of its
functionality can be found in the 80C51 based 8-bit
micro-controllers - Philips Semiconductors (ref. IC20).
Features of the 80c51
80C51 micro-controller core standard instruction set and
timing
0.4883s machine cycle (Xtal frequency 24.576MHz)
Maximum 256Kx8bit Flash Program ROM
Maximum of 8Kx8bit Auxiliary RAM
12-Level Interrupt Controller for individual
enable/disable with two level priority
Fig.11 ROM Bank switching memory map
Two 16-bit Timer/Counter registers

Additional 24-bit Timer (16-bit timer with 8-bit pre-scaler)
WatchDog Timer
RAM Organisation
The Internal Data RAM is organised into two areas, Data
Memory and Special Function Registers (SFRs) as shown
in Fig.12.
Auxiliary RAM Page Pointer

16-bit Data pointer
Stand-by, IDLE and Power Down (PD) modes
24 General I/O via individual addressable controls
Five 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analogue signals
Internal RAM : I-Data

FF H
One 14-bit PWM for Voltage Synthesis tuning control
128B RAM
only Indirect
addressing
8-bit ADC with 4 multiplexed inputs

High-speed
I 2C
for ISP (up to 1.2 Mb/s)
RAM
80 H
30..7F H
20..2F H Bit-addressable
space
18..1F H Register-Bank3
Lower 128 Byte RAM

Direct & Indirect
addressing
Universal Asynchronous Receiver Transmitter (UART)
Special Function Registers

= extension method for 80c51
7F H
Remote Control Pre-processor (RCP)

00 H
10..17 H Register-Bank2
Register-Bank
select bits
in PSW
R-Bank
08..0F H Register-Bank1
R7
R6
R5
R4
R3
R2
R1
R0
00..07 H Register-Bank0
Different addressing method for upper 128 Bytes

accesses RAM or SFR
Memory Organisation
The device has the capability of a maximum of 256K Bytes
of PROGRAM ROM and 8K Bytes of AUX DATA RAM for
internally.
Fig.12 Internal Data Memory
ROM Organisation
The 256K is arranged in eight banks of 32K. One of the
32K banks is common and is always addressable. The
other banks (Bank0 to Bank6) can be accessed by
selecting the right bank via the SFR ROMBK bits 2/1/0.
2003 Nov 11
128B SFR
only Direct
addressing
DATA MEMORY
The Data memory is 256 x 8-bits and occupies the address
range 00 to FF Hex when using Indirect addressing and 00
to 7F Hex when using direct addressing. The SFRs occupy
the address range 80 Hex to FF Hex and are accessible
using Direct addressing only. The lower 128 Bytes of Data
memory are mapped as shown in Fig.12. The lowest 32
bytes are grouped into 4 banks of 8 registers, the next 16
bytes above the register banks form a block of bit
addressable memory space. The upper 128 bytes are not
allocated for any special area or functions.
29
CONFIDENTIAL

SFR MEMORY
The Special Function Register (SFR) space is used for
port latches, counters/timers, peripheral control, data
capture and display control, etc. These registers can only
be accessed by direct addressing.
ADD
R/W
Names
UOCIII series
Sixteen of the addresses in the SFR space are both bit and
byte addressable. The bit addressable SFRs are those
whose address ends in 0H or 8H. A summary of the SFR
map in address order is shown in Table 5.
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
80H
R/W
P0
Reserved
Reserved
P0<5>
P0<4>
P0<3>
P0<2>
P0<1>
P0<0>
81H
R/W
SP
SP<7>
SP<6>
SP<5>
SP<4>
SP<3>
SP<2>
SP<1>
SP<0>
82H
R/W
DPL
DPL<7>
DPL<6>
DPL<5>
DPL<4>
DPL<3>
DPL<2>
DPL<1>
DPL<0>
83H
R/W
DPH
DPH<7>
DPH<6>
DPH<5>
DPH<4>
DPH<3>
DPH<2>
DPH<1>
DPH<0>
84H
R/W
IEN1
EX2
ERDS
EUART
ET2PR
EBUSY
85H
R/W
IP1
PX2
PRDS
PUART
PT2PR
PBUSY
86H
R/W
RCP1
DAT<7>
DAT<6>
DAT<5>
DAT<4>
DAT<3>
DAT<2>
DAT<1>
DAT<0>
87H
R/W
PCON
SMOD
ARD
RFI
WLE
GF1
GF0
PD
IDL
88H
R/W
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
89H
R/W
TMOD
GATE
C/T
M1
M0
GATE
C/T
M1
M0
8AH
R/W
TL0
TL0<7>
TL0<6>
TL0<5>
TL0<4>
TL0<3>
TL0<2>
TL0<1>
TL0<0>
8BH
R/W
TL1
TL1<7>
TL1<6>
TL1<5>
TL1<4>
TL1<3>
TL1<2>
TL1<1>
TL1<0>
8CH
R/W
TH0
TH0<7>
TH0<6>
TH0<5>
TH0<4>
TH0<3>
TH0<2>
TH0<1>
TH0<0>
8DH
R/W
TH1
TH1<7>
TH1<6>
TH1<5>
TH1<4>
TH1<3>
TH1<2>
TH1<1>
TH1<0>
8EH
RCP3
RA<7>
RA<6>
RA<5>
RA<4>
RA<3>
RA<2>
RA<1>
RA<0>
8FH
RCP4
RB<11>
RB<10>
RB<9>
RB<8>
RA<11>
RA<10>
RA<9>
RA<8>
90H
R/W
P1
P1<7>
P1<6>
P1<5>
P1<4>
P1<3>
P1<2>
P1<1>
P1<0>
91H
R/W
TP2L
TP2L<7>
TP2L<6>
TP2L<5>
TP2L<4>
TP2L<3>
TP2L<2>
TP2L<1>
TP2L<0>
92H
R/W
TP2H
TP2H<7>
TP2H<6>
TP2H<5>
TP2H<4>
TP2H<3>
TP2H<2>
TP2H<1>
TP2H<0>
93H
R/W
TP2PR
TP2PR<7>
TP2PR<6>
TP2PR<5>
TP2PR<4>
TP2PR<3>
TP2PR<2>
TP2PR<1>
TP2PR<0>
94H
R/W
TP2CRL
TP2CRL<1>
TP2CRL<0>
95H
R/W
RCP2
DAT<11>
DAT<10>
DAT<9>
DAT<8>
96H
R/W
P0CFGA
Reserved
Reserved
P0CFGA<5>
P0CFGA<4>
P0CFGA<3>
P0CFGA<2>
P0CFGA<1>
P0CFGA<0>
97H
R/W
P0CFGB
Reserved
Reserved
P0CFGB<5>
P0CFGB<4>
P0CFGB<3>
P0CFGB<2>
P0CFGB<1>
P0CFGB<0>
98H
R/W
SADB
SSD_ON
DC_COMP
SAD<3>
SAD<2>
SAD<1>
SAD<0>
99H
R/W
S0CON
SM<0>
SM<1>
SM<2>
REN
TB8
RB8
TI
RI
9AH
R/W
S0BUF
S0BUF<7>
S0BUF<6>
S0BUF<5>
S0BUF<4>
S0BUF<3>
S0BUF<2>
S0BUF<1>
S0BUF<0>
9BH
RCP5
RB<7>
RB<6>
RB<5>
RB<4>
RB<3>
RB<2>
RB<1>
RB<0>
9CH
TP2CL
TP2CL<7>
TP2CL<6>
TP2CL<5>
TP2CL<4>
TP2CL<3>
TP2CL<2>
TP2CL<1>
TP2CL<0>
9DH
TP2CH
TP2CH<7>
TP2CH<6>
TP2CH<5>
TP2CH<4>
TP2CH<3>
TP2CH<2>
TP2CH<1>
TP2CH<0>
9EH
R/W
P1CFGA
P1CFGA<7>
P1CFGA<6>
P1CFGA<5>
P1CFGA<4>
P1CFGA<3>
P1CFGA<2>
P1CFGA<1>
P1CFGA<0>
9FH
R/W
P1CFGB
P1CFGB<7>
P1CFGB<6>
P1CFGB<5>
P1CFGB<4>
P1CFGB<3>
P1CFGB<2>
P1CFGB<1>
P1CFGB<0>
2003 Nov 11
30
CONFIDENTIAL

ADD
R/W
Names
UOCIII series
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
Reserved
Reserved
P2<5>
P2<4>
P2<3>
P2<2>
P2<1>
P2<0>
A0H
R/W
P2
A1H
R/W
TXT31
CC_TXT
B
ACTIVE PAGE
1V8GUARD
GPF<11>
GPF<10>
GPF<9>
GPF<8>
A2H
TXT32
GPF<11>
9FF<11>
9FF<10>
9FF<9>
9FF<8>
9FF<7>
9FF<6>
9FF<5>
A3H
TXT33
BFE<7>
BFE<6>
BFE<5>
BFE<4>
BFE<3>
BFE<2>
BFE<1>
BFE<0>
A4H
TXT34
BFE<15>
BFE<14>
BFE<13>
BFE<12>
BFE<11>
BFE<10>
BFE<9>
BFE<8>
A5H
R/W
Video_process
DW_PA<1>
DW_PA<0>
A6H
R/W
P2CFGA
Reserved
Reserved
P2CFGA<5>
P2CFGA<4>
P2CFGA<3>
P2CFGA<2>
P2CFGA<1>
P2CFGA<0>
A7H
R/W
P2CFGB
Reserved
Reserved
P2CFGB<5>
P2CFGB<4>
P2CFGB<3>
P2CFGB<2>
P2CFGB<1>
P2CFGB<0>
A8H
R/W
IE
EA
ES2
ECC
EDET
ET1
EX1
ET0
EX0
A9H
R/W
TXT23
NOT B <3>
NOT B <2>
NOT B <1>
NOT B <0>
East/West B
DRCS B
ENABLE
BS B<1>
BS B<0>
AAH
R/W
TXT24
BKGND OUT
B
BKGND IN B
CORB OUT B
CORB IN
B
TEXT OUT B
TEXT IN
B
PICTURE ON
OUT
B
PICTURE ON
IN
B
ABH
R/W
TXT25
BKGND OUT
B
BKGND IN B
CORB OUT B
CORB IN
B
TEXT OUT B
TEXT IN
B
PICTURE ON
OUT
B
PICTURE ON
IN
B
ACH
R/W
TXT26
EXTENDED
DRCS
TRANS B
SHADOW
ENABLE B
BOX ON
24 B
BOX ON
1-23 B
BOX ON
0B
ADH
R/W
TXT28
DISPLAY
BANK B<3>
DISPLAY
BANK B<2>
DISPLAY
BANK B<1>
DISPLAY
BANK B<0>
PAGE B<3>
PAGE B<2>
PAGE B<1>
PAGE B<0>
AEH
ADJUST_E0
ADJUST
E0<7>
ADJUST
E0<6>
ADJUST
E0<5>
ADJUST
E0<4>
ADJUST E0<3>
ADJUST
E0<2>
ADJUST
E0<1>
ADJUST
E0<0>
AFH
ADJUST_E1
ADJUST
E1<7>
ADJUST
E1<6>
ADJUST
E1<5>
ADJUST
E1<4>
ADJUST E1<3>
ADJUST
E1<2>
ADJUST
E1<1>
ADJUST
E1<0>
B0H
R/W
P3
Reserved
Reserved
Reserved
Reserved
P3<3>
P3<2>
P3<1>
P3<0>
B1H
R/W
TXT27
RDS ON
SCR B<2>
SCR B<1>
SCR B<0>
B2H
R/W
TXT18
NOT<3>
NOT<2>
NOT<1>
NOT<0>
BS<1>
BS<0>
B3H
R/W
TXT19
TEN
TC<2>
TC<1>
TC<0>
TS<1>
TS<0>
B4H
R/W
TXT20
DRCS
ENABLE
OSD PLANES
EXTENDED
SPECIAL
GRAPHICS
CHAR
SELECT
ENABLE
OSD LANG
ENABLE
OSD LAN<2>
OSD LAN<1>
OSD LAN<0>
B5H
R/W
TXT21
DISP LINE<1>
DISP
LINES<0>
CHAR
SIZE<1>
CHAR
SIZE<0>
Reserved (0)
CC ON
I2C PORT EN
CC/TXT
B6H
TXT22
GPF<7>
GPF<6>
GPF<5>
GPF<4>
GPF<3>
GPF<2>
GPF<1>
GPF<0>
B7H
R/W
CCLIN
CS<4>
CS<3>
CS<2>
CS<1>
CS<0>
B8H
R/W
IP
PES2
PCC
PDET
PT1
PX1
PT0
PX0
B9H
R/W
TXT17
FORCE
ACQ<1>
FORCE
ACQ<0>
FORCE
DISP<1>
FORCE
DISP<0>
SCREEN
COL<2>
SCREEN
COL<1>
SCREEN
COL<0>
BAH
WSS1
WSS<3:0>
ERROR
WSS<3>
WSS<2>
WSS<1>
WSS<0>
BBH
WSS2
WSS<7:4>
ERROR
WSS<7>
WSS<6>
WSS<5>
WSS<4>
2003 Nov 11
31
CONFIDENTIAL

ADD
R/W
Names
UOCIII series
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
WSS<13:11>
ERROR
WSS<13>
WSS<12>
WSS<11>
WSS<10:8>
ERROR
WSS<10>
WSS<9>
WSS<8>
BCH
WSS3
BDH
ADJUST_E2
ADJUST
E2<7>
ADJUST
E2<6>
ADJUST
E2<5>
ADJUST
E2<4>
ADJUST E2<3>
ADJUST
E2<2>
ADJUST
E2<1>
ADJUST
E2<0>
BEH
R/W
P3CFGA
Reserved
Reserved
Reserved
Reserved
P3CFGA<3>
P3CFGA<2>
P3CFGA<1>
P3CFGA<0>
BFH
R/W
P3CFGB
Reserved
Reserved
Reserved
Reserved
P3CFGB<3>
P3CFGB<2>
P3CFGB<1>
P3CFGB<0>
C0H
R/W
TXT0
X24 POSN
DISPLAY X24
AUTO FRAME
DISABLE
HEADER
ROLL
DISPLAY
STATUS ROW
ONLY
DISABLE
FRAME
VPS ON
INV ON
C1H
R/W
TXT1
EXT PKT OFF
8 BIT
ACQ OFF
X26 OFF
Reserved
FIELD
POLARITY
H POLARITY
V POLARITY
C2H
R/W
TXT2
ACQ
BANK<0>
REQ<3>
REQ<2>
REQ<1>
REQ<0>
SC<2>
SC<1>
SC<0>
C3H
R/W
TXT3
ACQ
BANK<3>
ACQ
BANK<2>
ACQ
BANK<1>
PRD<4>
PRD<3>
PRD<2>
PRD<1>
PRD<0>
C4H
R/W
TXT4
OSD BANK
ENABLE
QUAD
WIDTH
ENABLE
EAST/WEST
DISABLE
DOUBLE
HEIGHT
TRANS
ENABLE
SHADOW
ENABLE
C5H
R/W
TXT5
BKGND OUT
BKGND IN
CORB OUT
CORB IN
TEXT OUT
TEXT IN
PICTURE ON
OUT
PICTURE ON
IN
C6H
R/W
TXT6
BKGND OUT
BKGND IN
CORB OUT
CORB IN
TEXT OUT
TEXT IN
PICTURE ON
OUT
PICTURE ON
IN
C7H
R/W
TXT7
STATUS ROW
TOP
CURSOR ON
REVEAL
BOTTOM/TOP
DOUBLE
HEIGHT
BOX ON 24
BOX ON 1-23
BOX ON 0
C8H
R/W
TXT8
(Reserved)
0
FLICKER
STOP ON
HUNT
DISABLE
SPANISH
PKT 26
RECEIVED
WSS
RECEIVED
WSS ON
(Reserved)
0
C9H
R/W
TXT9
CURSOR
FREEZE
CLEAR
MEMORY
A0
R<4>
R<3>
R<2>
R<1>
R<0>
CAH
R/W
TXT10
CHAR
16/12
C<5>
C<4>
C<3>
C<2>
C<1>
C<0>
CBH
R/W
TXT11
D<7>
D<6>
D<5>
D<4>
D<3>
D<2>
D<1>
D<0>
CCH
TXT12
525/625 SYNC
ROM VER<4>
ROM VER<3>
ROM VER<2>
ROM VER<1>
ROM VER<0>
VIDEO
SIGNAL
QUALITY
CDH
R/W
TXT14
DISPLAY
BANK<3>
DISPLAY
BANK<2>
DISPLAY
BANK<1>
DISPLAY
BANK<0>
PAGE<3>
PAGE<2>
PAGE<1>
PAGE<0>
CEH
R/W
TXT15
MICRO
BANK<3>
MICRO
BANK<2>
MICRO
BANK<1>
MICRO
BANK<0>
BLOCK<3>
BLOCK<2>
BLOCK<1>
BLOCK<0>
CFH
ADJUST
E3<7>
ADJUST
E3<6>
ADJUST
E3<5>
ADJUST
E3<4>
ADJUST E3<3>
ADJUST
E3<2>
ADJUST E31>
ADJUST
E3<0>
D0H
R/W
AC
F0
RS1
RS0
OV
D1H
ADJUST
E4<7>
ADJUST
E4<6>
ADJUST
E4<5>
ADJUST
E4<4>
ADJUST E4<3>
ADJUST
E4<2>
ADJUST
E4<1>
ADJUST
E4<0>
D2H
R/W
TDACL
TD<7>
TD<6>
TD<5>
TD<4>
TD<3>
TD<2>
TD<1>
TD<0>
D3H
R/W
TDACH
TPWE
TD<13>
TD<12>
TD<11>
TD<10>
TD<9>
TD<8>
D4H
R/W
P3DCXOCTR
L
P3DCXOMUX
P3DCXOCAP
S<6>
P3DCXOCAP
S<5>
P3DCXOCAPS
<4>
P3DCXOCAPS
<3>
P3DCXOCAP
S<2>
P3DCXOCAPS
<1>
P3DCXOCAPS
<0>
D5H
R/W
PWM0
PW0E
Reserved (0)
PW0V<5>
PW0V<4>
PW0V<3>
PW0V<2>
PW0V<1>
PW0V<0>
D6H
R/W
PWM1
PW1E
PW1V<5>
PW1V<4>
PW1V<3>
PW1V<2>
PW1V<1>
PW1V<0>
2003 Nov 11
ADJUST_E3
PSW
ADJUST_E4
32
CONFIDENTIAL

ADD
R/W
Names
CCDAT1
UOCIII series
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
CCD1<7>
CCD1<6>
CCD1<5>
CCD1<4>
CCD1<3>
CCD1<2>
CCD1<1>
CCD1<0>
D7H
D8H
R/W
S1CON
EN_I2CINT
ENSI
STA
STO
SI
AA
D9H
S1STA
STAT<4>
STAT<3>
STAT<2>
STAT<1>
STAT<0>
DAH
R/W
S1DAT
DAT<7>
DAT<6>
DAT<5>
DAT<4>
DAT<3>
DAT<2>
DAT<1>
DAT<0>
DBH
R/W
S1ADR
ADR<6>
ADR<5>
ADR<4>
ADR<3>
ADR<2>
ADR<1>
ADR<0>
GC
DCH
R/W
PWM3
PW3E
PW3V<5>
PW3V<4>
PW3V<3>
PW3V<2>
PW3V<1>
PW3V<0>
DDH
R/W
PWM4
PW4E
PW4V<5>
PW4V<4>
PW4V<3>
PW4V<2>
PW4V<1>
PW4V<0>
DEH
R/W
HSBIR
HSB<4>
HSB<3>
HSB<2>
HSB<1>
HSB<0>
DFH
R/W
FSBIR
F/S
FSB<6>
FSB<5>
FSB<4>
FSB<3>
FSB<2>
FSB<1>
FSB<0>
E0H
R/W
ACC
ACC<7>
ACC<6>
ACC<5>
ACC<4>
ACC<3>
ACC<2>
ACC<1>
ACC<0>
E1H
R/W
TXT29
TEN B
TS B <1>
TS B <0>
OSD
PLANES B
OSD LANG
ENABLE B
OSD LAN B
<2>
OSD LAN B
<1>
OSD LAN B
<0>
E2H
R/W
TXT30
TC B <2>
TC B <1>
TC B <0>
BOTTOM/TOP
B
DOUBLE
HEIGHT
B
STATUS ROW
TOP B
DISPLAY X24
B
DISPLAY
STATUS ROW
ONLY B
E3H
R/W
RDS_F0_F1
F0<3>
F0<2>
F0<1>
F0<0>
F1<3>
F1<2>
F1<1>
F1<0>
E4H
R/W
PWM2
PW2E
PW2V<5>
PW2V<4>
PW2V<3>
PW2V<2>
PW2V<1>
PW2V<0>
COEF<14>
COEF<13>
COEF<12>
COEF<11>
COEF<10>
COEF<9>
COEF<8>
E5H
R/W
RDS_COEF_
H
COEF<15>
E6H
R/W
RDS_COEF_
L
COEF<7>
COEF<6>
COEF<5>
COEF<4>
COEF<3>
COEF<2>
COEF<1>
COEF<0>
E7H
CCDAT2
CCD2<7>
CCD2<6>
CCD2<5>
CCD2<4>
CCD2<3>
CCD2<2>
CCD2<1>
CCD2<0>
E8H
R/W
SAD
VHI
CH<1>
CH<0>
ST
SAD<7>
SAD<6>
SAD<5>
SAD<4>
SYNC
DOFL
RSTD
LBIN<2>
LBIN<1>
LBIN<0>
ELB<1>
ELB<0>
E9H
RDS_STAT
EAH
RDS_LDATH
LDAT<15>
LDAT<14>
LDAT<13>
LDAT<12>
LDAT<11>
LDAT<10>
LDAT<9>
LDAT<8>
EBH
RDS_LDATL
LDAT<7>
LDAT<6>
LDAT<5>
LDAT<4>
LDAT<3>
LDAT<2>
LDAT<1>
LDAT<0>
ECH
RDS_PDATH
PDAT<15>
PDAT<14>
PDAT<13>
PDAT<12>
PDAT<11>
PDAT<10>
PDAT<9>
PDAT<8>
EDH
RDS_PDATL
PDAT<7>
PDAT<6>
PDAT<5>
PDAT<4>
PDAT<3>
PDAT<2>
PDAT<1>
PDAT<0>
EFH
R/W
RCP6
RCP ON
NFP
NGP
RCPSET<2>
RCPSET<1>
RCPSET<0>
F0H
R/W
B<7>
B<6>
B<5>
B<4>
B<3>
B<2>
B<1>
B<0>
BBC<4>
BBC<3>
BBC<2>
BBC<1>
BBC<0>
EPB<1>
EPB<0>
F1H
RDS_CNT1
BBC<5>
F2H
RDS_CNT2
GBC<5>
GBC<4>
GBC<3>
GBC<2>
GBC<1>
PBIN<2>
PBIN<1>
PBIN<0>
F3H
R/W
RDS_CTRL1
RBDS
MBBL<5>
MBBL<4>
MBBL<3>
MBBL<2>
MBBL<1>
MBBL<0>
F4H
R/W
RDS_CTRL2
SYM<1>
SYM<0>
MGBL<5>
MGBL<4>
MGBL<3>
MGBL<2>
MGBL<1>
MGBL<0>
F5H
R/W
RDS_CTRL3
DAC<1>
DAC<0>
NWSY
MBBG<4>
MBBG<3>
MBBG<2>
MBBG<1>
MBBG<0>
F6H
R/W
I2S
I2S_CLK<1>
I2S_CLK<0>
EN_I2S_DI1
EN_I2SDO1
EN_I2SDO2
EN_I2SCLK
EN_I2SWS
rds_clkin
F7H
TXT35
9FF<15>
9FF<14>
9FF<13>
9FF<12>
GPF<15>
GPF<14>
GPF<13>
GPF<12>
F8H
R/W
TXT13
VPS
RECEIVED
PAGE
CLEARING
525 DISPLAY
525 TEXT
625 TEXT
PKT 8/30
FASTEXT
2003 Nov 11
33
CONFIDENTIAL

ADD
R/W
Names
UOCIII series
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SCAVEM_EN
PULSE_
WIDTH<1>
PULSE_
WIDTH<0>
EARLY<2>
EARLY<1>
EARLY<0>
F9H
R/W
SCAVTXT
FAH
R/W
XRAMP
XRAMP<7>
XRAMP<6>
XRAMP<5>
XRAMP<4>
XRAMP<3>
XRAMP<2>
XRAMP<1>
XRAMP<0>
FBH
R/W
ROMBK
STANDBY
SW_RST
TEMP_140
TEMP_130
ROMBK<2>
ROMBK<1>
ROMBK<0>
FCH
TXT36
BFF<4>
BFF<3>
BFF<2>
BFF<1>
BFF<0>
FDH
TEST
TEST<7>
TEST<6>
TEST<5>
TEST<4>
TEST<3>
TEST<2>
TEST<1>
TEST<0>
FEH
WDTKEY
WKEY<7>
WKEY<6>
WKEY<5>
WKEY<4>
WKEY<3>
WKEY<2>
WKEY<1>
WKEY<0>
FFH
R/W
WDV<7>
WDV<6>
WDV<5>
WDV<4>
WDV<3>
WDV<2>
WDV<1>
WDV<0>
Table 5
WDT
SFR Map
A description of each the SFR bits is shown in Table 6. The SFRs are in alphabetical order.
Table 6
SFR Bit description
Names
ACC
Add
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
E0H
ACC<7>
ACC<6>
ACC<5>
ACC<4>
ACC<3>
ACC<2>
ACC<1>
ACC<0>
00H
ADJUST
E0<6>
ADJUST
E0<5>
ADJUST
E0<4>
ADJUST
E0<3>
ADJUST
E0<2>
ADJUST
E0<1>
ADJUST
E0<0>
XXH
ADJUST
E1<5>
ADJUST
E1<4>
ADJUST
E1<3>
ADJUST
E1<2>
ADJUST
E1<1>
ADJUST
E1<0>
XXH
ADJUST
E2<5>
ADJUST
E2<4>
ADJUST
E2<3>
ADJUST
E2<2>
ADJUST
E2<1>
ADJUST
E2<0>
XXH
ADJUST
E3<5>
ADJUST
E3<4>
ADJUST
E3<3>
ADJUST
E3<2>
ADJUST
E3<1>
ADJUST
E3<0>
XXH
ADJUST
E4<5>
ADJUST
E4<4>
ADJUST
E4<3>
ADJUST
E4<2>
ADJUST
E4<1>
ADJUST
E4<0>
XXH
P3DCXOCAP
S<5>
P3DCXOCAP
S<4>
P3DCXOCAPS
<3>
P3DCXOCAP
S<2>
P3DCXOCAP
S<1>
P3DCXOCAP
S<0>
XXH
ACC<7:0>
ADJUST_E0
AEH
ADJUST E0<7:0>
ADJUST_E1
AFH
ADJUST E1<7:0>
ADJUST_E2
BDH
ADJUST E2<7:0>
ADJUST_E3
CFH
ADJUST E3<7:0>
ADJUST_E4
D1H
ADJUST E4<7:0>
P3DCXOCTRL
D4H
P3DCXOMUX
P3DCXOCAPS<6:0>
B
CCDAT1
2003 Nov 11
Accumulator value
ADJUST
E0<7>
For internal testing purpose.

ADJUST
E1<7>
ADJUST
E1<6>

ADJUST
E2<7>
ADJUST
E2<6>

ADJUST
E3<7>
ADJUST
E3<6>

ADJUST
E4<7>
ADJUST
E4<6>

P3DCXOMUX
P3DCXOCAP
S<6>
DCXO Cap. Bank Selection:0 - P3DCXOCAPS

1 - SSD Nicam
DCXO Cap. Bank tuning for NICAM.
F0H
B<7>
B<7:0>
B Register value
D7H
CCD1<7>
B<6>
B<5>
B<4>
B<3>
B<2>
B<1>
B<0>
00H
CCD1<6>
CCD1<5>
CCD1<4>
CCD1<3>
CCD1<2>
CCD1<1>
CCD1<0>
00H
34
CONFIDENTIAL

Names
Add
CCD1<7:0>
CCDAT2
E7H
CCD2<7:0>
CCLIN
B7H
CS<4:0>
DPH
83H
DPH<7:0>
DPL
82H
DPL<7:0>
FSBIR
DFH
F/S
FSB<6:0>
HSBIR
DEH
HSBIR<4:0>
I2S
F6H
I2S_CLK<1:0>
EN_I2SDI1
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
CCD2<5>
CCD2<4>
CCD2<3>
CCD2<2>
CCD2<1>
CCD2<0>
00H
CS<4>
CS<3>
CS<2>
CS<1>
CS<0>
15H
DPH<5>
DPH<4>
DPH<3>
DPH<2>
DPH<1>
DPH<0>
00H
DPL<3>
DPL<2>
DPL<1>
DPL<0>
00H
FSB<3>
FSB<2>
FSB<1>
FSB<0>
00H
Closed Caption first data byte

CCD2<7>
CCD2<6>
Closed Caption second data byte

0
Closed caption Slice line using 525 line number.

DPH<7>
DPH<6>
Data Pointer High byte, used with DPL to address auxiliary memory
DPL<7>
DPL<6>
DPL<5>
F/S
FSB<6>
FSB<5>
Determine the SCLH-out frequency in F/S-mode

0
HSB<4>
HSB<3>
HSB<2>
HSB<1>
HSB<0>
00H
EN_I2SDI1
EN_I2SDO1
EN_I2SDO2
EN_I2SCLK
EN_I2SWS
rds_clkin
00H
EDET
ET1
EX1
ET0
EX0
00H
Determine the SCLH-out frequency in Hs-mode

I2S_CLK<1>
I2S_CLK<0>
I2S Clock Output Selection:00 - 256fs

01 - 128fs
10 - 64fs
11 - invalid
fs = 32kHz
Enable I2S Data Input 1 alternative function to port pin:0 - GPIO function
1 - I2S Data Input 1
EN_I2SDO2
Enable I2S Data Output 2 alternative function to port pin:0 - GPIO function
1 - I2S Data Output 2
EN_I2SCLK
Enable I2S Clock Output alternative function to port pin:0 - GPIO function
1 - I2S Clock Output
EN_I2SWS
Enable I2S Word Select alternative function to port pin:0 - GPIO function
1 - I2S Word Select
A8H
EA
EA
ES2
ECC
Disable all interrupts (0), or use individual interrupt enable bits (1)
Enable I2C interrupt.
ECC
Enable Closed Caption interrupt
ET1
2003 Nov 11
For RDS debugging / evaluation only.
ES2
EDET
FSB<4>
0 - the duty cycle of SCLH-out is according the Standard mode requirement.

1 - the duty cycle of SCLH-out is according the Fast mode requirement.
Enable I2S Data Output 1 alternative function to port pin:0 - GPIO function
1 - I2S Data Output 1
IE
DPL<4>
Data pointer low byte, used with DPH to address auxiliary memory
EN_I2SDO1
rds_clkin
UOCIII series
Enable Supply Dip Monitor Interrupt.

Enable Timer 1 interrupt
35
CONFIDENTIAL

Names
Add
IEN1
BIT7
BIT6
EX1
Enable External interrupt 1
ET0
EX0
Enable External interrupt 0
84H
EX2
ERDS
EBUSY
Enable BUSY interrupt
PCC
PDET
IP1
P1
Priority Timer 0 interrupt
PX0
Priority External Interrupt 0
P3
PBUSY
Priority BUSY Interrupt
B0H
P3<3:0>
ERDS
EUART
ET2PR
EBUSY
00H
PCC
PDET
PT1
PX1
PT0
PX0
00H
PX2
PRDS
PUART
PT2PR
PBUSY
00H
P0<5>
P0<4>
P0<3>
P0<2>
P0<1>
P0<0>
00H
P1<5>
P1<4>
P1<3>
P1<2>
P1<1>
P1<0>
C3H
P2<5>
P2<4>
P2<3>
P2<2>
P2<1>
P2<0>
00H
Reserved
Reserved
P3<3>
P3<2>
P3<1>
P3<0>
C0H
Priority RDS/RBDS Interrupt.
P2<5:0>
EX2
Priority External Interrupt 2.
PT2PR
A0H
Priority UART Interrupt.
P1<7:0>
P2
PUART
90H
RESET
Priority Supply Dip Monitor Interrupt.
PT0
P0<5:0>
BIT0
Priority Closed Caption Interrupt
Priority External Interrupt 1
80H
BIT1
Priority I2C interrupt
PX1
PRDS
BIT2
PES2
PX2
P0
PT1
85H
BIT3
Enable RDS/RBDS Interrupt.
ET2PR
PES2
BIT4
Enable External Interrupt 2.
Enable UART Interrupt.
B8H
BIT5
EUART
IP
UOCIII series
Reserved
Reserved
Port 0 I/O register connected to external pins

P1<7>
P1<6>

Reserved
Reserved

Reserved
Reserved
P0CFGA
96H
Reserved
Reserved
P0CFGA<5>
P0CFGA<4>
P0CFGA<3>
P0CFGA<2>
P0CFGA<1>
P0CFGA<0>
00H
P0CFGB
97H
Reserved
Reserved
P0CFGB<5>
P0CFGB<4>
P0CFGB<3>
P0CFGB<2>
P0CFGB<1>
P0CFGB<0>
00H
P0CFGB<x>/P0CFGA<x> = 00
MODE 0 Open Drain
MODE 1 Quasi Bi-Directional
MODE2 High Impedance
2003 Nov 11
36
CONFIDENTIAL

Names
Add
BIT7
BIT6
UOCIII series
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
MODE3 Push Pull
P1CFGA
9EH
P1CFGA<7>
P1CFGA<6>
P1CFGA<5>
P1CFGA<4>
P1CFGA<3>
P1CFGA<2>
P1CFGA<1>
P1CFGA<0>
00H
P1CFGB
9FH
P1CFGB<7>
P1CFGB<6>
P1CFGB<5>
P1CFGB<4>
P1CFGB<3>
P1CFGB<2>
P1CFGB<1>
P1CFGB<0>
00H
MODE 0 Open Drain
MODE3 Push Pull
P2CFGA
A6H
Reserved
Reserved
P2CFGA<5>
P2CFGA<4>
P2CFGA<3>
P2CFGA<2>
P2CFGA<1>
P2CFGA<0>
00H
P2CFGB
A7H
Reserved
Reserved
P2CFGB<5>
P2CFGB<4>
P2CFGB<3>
P2CFGB<2>
P2CFGB<1>
P2CFGB<0>
00H
MODE 0 Open Drain
MODE3 Push Pull
P3CFGA
BEH
Reserved
Reserved
Reserved
Reserved
P3CFGA<3>
P3CFGA<2>
P3CFGA<1>
P3CFGA<0>
00H
P3CFGB
BFH
Reserved
Reserved
Reserved
Reserved
P3CFGB<3>
P3CFGB<2>
P3CFGB<1>
P3CFGB<0>
00H
WLE
GF1
GF0
PD
IDL
00H
RS<0>
OV
00H
MODE 0 Open Drain
MODE 1 Quasi Bi-directional
MODE3 Push Pull
PCON
87H
SMOD
SMOD
ARD
RFI
WLE
PSW
Disable ALE during internal access to reduce Radio Frequency Interference

0: Enable
1: Disable
Watch Dog Timer enable
0: Disable
1: Enable
GF0
General purpose flag
D0H
Power-down activation bit

Idle mode activation bit
C
2003 Nov 11
Auxiliary RAM Disable, All MOVX instructions access the off-chip data memory.
0: Enable
1: Disable
In application mode, this bit should keep 0.
General purpose flag
IDL
RFI
UART Baud Rate Double Control
GF1
PD
ARD
AC
F0
RS<1>
Carry Bit
AC
Auxiliary Carry bit
F0
Flag 0, General purpose flag
37
CONFIDENTIAL

Names
Add
RS<1:0>
OV
P
PWM0
D5H
PW0E
PW0V<5:0>
PWM1
D6H
PW1E
PW1V<5:0>
PWM2
E4H
PW2E
PW2V<5:0>
PWM3
DCH
PW3E
PW3V<5:0>
PWM4
DDH
PW4E
PW4V<5:0>
RCP1
86H
DAT<7:0>
RCP2
95H
DAT<11:8>
RCP3
8EH
RA<7:0>
RCP4
8FH
BIT7
BIT6
PW0E
Reserved (0)
2003 Nov 11
EFH
BIT2
BIT1
BIT0
RESET
PW0V<5>
PW0V<4>
PW0V<3>
PW0V<2>
PW0V<1>
PW0V<0>
00H
PW1V<5>
PW1V<4>
PW1V<3>
PW1V<2>
PW1V<1>
PW1V<0>
00H
PW2V<5>
PW2V<4>
PW2V<3>
PW2V<2>
PW2V<1>
PW2V<0>
00H
PW3V<5>
PW3V<4>
PW3V<3>
PW3V<2>
PW3V<1>
PW3V<0>
00H
PW4V<5>
PW4V<4>
PW4V<3>
PW4V<2>
PW4V<1>
PW4V<0>
00H
DAT<5>
DAT<4>
DAT<3>
DAT<2>
DAT<1>
DAT<0>
00H
DAT<9>
DAT<8>
X0H
0 - Disable Pulse Width Modulator 0

1 - Enable Pulse Width Modulator 0
Pulse Width Modulator high time
PW1E

PW2E

PW3E

PW4E

DAT<7>
DAT<6>
Data location shared by CDIV<7:0>, AL<7:0>, AH<7:0>, BL<7:0>, BH<7:0>

Reset value of CDIV<7:0>, AL<7:0>, and BL<7:0> are 00H; reset value of AH<7:0> and BH<7:0> are FFH.
-
DAT<11>
DAT<10>
Data location shared by CDIV<11:8>, AL<11:8>, AH<11:8>, BL<11:8> and BH<11:8>

Reset value of CDIV<11:8>, AL<11:8>, and BL<11:8> are 0H; reset value of AH<11:8> and BH<11:8> are FH.
RA<7>
RA<6>
RA<5>
RA<4>
RA<3>
RA<2>
RA<1>
RA<0>
00H
RB<9>
RB<8>
RA<11>
RA<10>
RA<9>
RA<8>
00H
RB<5>
RB<4>
RB<3>
RB<2>
RB<1>
RB<0>
00H
NGP
RCPSET<2>
RCPSET<1>
RCPSET<0>
00H
LOW time Result (bit 7:0) minus AL

RB<11>
RB<10>
LOW time Result (bit 11:8)
RCP6
BIT3
Parity bit
RA<11:8>
RB<7:0>
BIT4
Overflow flag
High time Result (bit 11:8)
9BH
BIT5
Register Bank selector bits

RS<1:0> = 00, Bank0 (00H - 07H)
RS<1:0> = 01, Bank1 (08H - 0FH)
RS<1:0> = 10, Bank2 (10H - 17H)
RS<1:0> = 11, Bank3 (18H - 1FH)
RB<11:8>
RCP5
UOCIII series
RB<7>
RB<6>
High time Result (bit 7:0) minus BL

RCP ON
NFP
38
CONFIDENTIAL

Names
Add
RCP ON
0 - First Pulse
1 - Not First Pulse
NGP
0 - Good Pulse
1 - Not Good Pulse
E9H
RDS_LDATH
DOFL
Data overflow flag
RSTD
Reset detected
EAH
LDAT<15:8>
RDS_LDATL
EBH
LDAT<7:0>
RDS_PDATH
ECH
PDAT<15:8>
RDS_PDATL
EDH
PDAT<7:0>
RDS_CNT1
F1H
BBC<5:0>
EPB<1:0>
RDS_CNT2
F2H
GBC<5:1>
2003 Nov 11
SYNC
Synchronization found
ELB<1:0>
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
LBIN<2>
LBIN<1>
LBIN<0>
ELB<1>
ELB<0>
1CH
LDAT<13>
LDAT<12>
LDAT<11>
LDAT<10>
LDAT<9>
LDAT<8>
00H
LDAT<5>
LDAT<4>
LDAT<3>
LDAT<2>
LDAT<1>
LDAT<0>
00H
PDAT<13>
PDAT<12>
PDAT<11>
PDAT<10>
PDAT<9>
PDAT<8>
00H
PDAT<5>
PDAT<4>
PDAT<3>
PDAT<2>
PDAT<1>
PDAT<0>
00H
BBC<3>
BBC<2>
BBC<1>
BBC<0>
EPB<1>
EPB<0>
00H
GBC<2>
GBC<1>
PBIN<2>
PBIN<1>
PBIN<0>
07H
Define DAT<11:0> value:000 - CDIV<11:0> is accessed via DAT<11:0>, default = 000H

001 - AL<11:0> is accessed via DAT<11:0>, default = 000H
010 - AH<11:0> is accessed via DAT<11:0>, default = FFFH
011 - BL<11:0> is accessed via DAT<11:0>, default = 000H
100 - BH<11:0> is accessed via DAT<11:0>, default = FFFH
101 - SPF<11:0> is accessed via DAT<11:0>, default = 003H
SYNC
LBIN<2:0>
BIT6
0 - Remote Control Pre-processor disable

1 - Remote Control Pre-processor enable
NFP
RCPSET<2:0>
RDS_STAT
BIT7
UOCIII series
DOFL
RSTD
Last block identification

LBIN<2:0>=000, block A
LBIN<2:0>=001, block B
LBIN<2:0>=010, block C
LBIN<2:0>=011, block D
LBIN<2:0>=100, block C
LBIN<2:0>=101, block E (RBDS mode)
LBIN<2:0>=110, invalid block E (RDS mode)
LBIN<2:0>=111, invalid block
Error status last block
ELB<1:0>=00, no errors detect
ELB<1:0>=01, max. 2 bits
ELB<1:0>=10, max. 5 bits
ELB<1:0>=11, uncorrectable block
LDAT<15>
LDAT<14>
Last processed block data high byte

LDAT<7>
LDAT<6>
Last processed block data low byte

PDAT<15>
PDAT<14>
Previous processed block data high byte

PDAT<7>
PDAT<6>
Previous processed block data low byte

BBC<5>
BBC<4>
Bad Blocks Counter

Error Status Previous Block
EPB<1:0>=00 - no errors detected
EPB<1:0>=01 - burst error of maximum 2 bits corrected
EPB<1:0>=10 - burst error of maximum 5 bits corrected
EPB<1:0>=11 - uncorrectable block
GBC<5>
GBC<4>
GBC<3>
Good Blocks Counter (Only 5 MSBs are available)
39
CONFIDENTIAL

Names
Add
PBIN<2:0>
RDS_CTRL1
F3H
RBDS
MBBL<5:0>
RDS_CTRL2
F4H
SYM<1:0>
MGBL<5:0>
RDS_CTRL3
F5H
DAC<1:0>
NWSY
MBBG<4:0>
RDS_F0_F1
E3H
BIT7
BIT6
E6H
COEF<7:0>
ROMBK
FBH
BIT0
RESET
MBBL<3>
MBBL<2>
MBBL<1>
MBBL<0>
20H
SYM<0>
MGBL<5>
MGBL<4>
MGBL<3>
MGBL<2>
MGBL<1>
MGBL<0>
20H
Allow RBDS E Block

0 - RDS mode
1 - RBDS mode
Max Bad Block Lose
SYM<1>
Synchronization Mode
SYM<1:0>=00 - no error correction
SYM<1:0>=01 - error correction of a burst error maximum 2 bits
SYM<1:0>=10 - error correction of a burst error maximum 5 bits
SYM<1:0>=11 - no error correction
Max Good Block Lose
DAC<1>
DAC<0>
NWSY
MBBG<4>
MBBG<3>
MBBG<2>
MBBG<1>
MBBG<0>
00H
F0<1>
F0<0>
F1<3>
F1<2>
F1<1>
F1<0>
32H
COEF<13>
COEF<12>
COEF<11>
COEF<10>
COEF<9>
COEF<8>
4BH
COEF<5>
COEF<4>
COEF<3>
COEF<2>
COEF<1>
COEF<0>
CAH
TEMP_140
TEMP_130
ROMBK<2>
ROMBK<1>
ROMBK<0>
00H
Data output control

DAC<1:0>=00, standard mode
DAC<1:0>=01, fast PI search mode
DAC<1:0>=10, reduced data request
DAC<1:0>=11, decoder bypass
Start new synchronization
Max bad blocks gain
F0<3>
F0<2>
COEF<15>
COEF<14>
DCS Coefficient High Byte

COEF<7>
COEF<6>
DCS Coefficient Low Byte

STANDBY
SW_RST
STANDBY
0 - Disable Stand-by Mode

1 - Enable Stand-by Mode
SW_RST
0 - Disable Software Reset

1 - Enable Software Reset
TEMP_140
0 - Temperature of the device below 140C

1 - Temperature of the device above 140C
TEMP_130
0 - Temperature of the device below 130C

1 - Temperature of the device above 130C
2003 Nov 11
BIT1
MBBL<4>
Coarse Division Factor F1
COEF<15:8>
BIT2
MBBL<5>
F1<3:0>
RDS_COEF_L
BIT3
RBDS
Coarse Division Factor F0
E5H
BIT4
Previous Block Identification

PBIN<2:0>=000 - block A
PBIN<2:0>=001 - block B
PBIN<2:0>=010 - block C
PBIN<2:0>=011 - block D
PBIN<2:0>=100 - block C
PBIN<2:0>=101 - block E (RBDS mode)
PBIN<2:0>=110 - invalid block E (RDS mode)
PBIN<2:0>=111 - invalid block
F0<3:0>
RDS_COEF_H
BIT5
UOCIII series
40
CONFIDENTIAL

Names
Add
ROMBK<2:0>
S0BUF
9AH
S0BUF<7:0>
S0CON
99H
SM<0:1>
SM<2>
S1ADR
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
S0BUF<6>
S0BUF<5>
S0BUF<4>
S0BUF<3>
S0BUF<2>
S0BUF<1>
S0BUF<0>
00H
SM<1>
SM<2>
REN
TB8
RB8
TI
RI
00H
ROM Bank selection

ROMBK<2:0> = 000, Bank0
ROMBK<2:0> = 001, Bank1
ROMBK<2:0> = 010, Bank2
ROMBK<2:0> = 011, Bank3
ROMBK<2:0> = 100, Bank4
ROMBK<2:0> = 101, Bank5
ROMBK<2:0> = 110, Bank6
ROMBK<2:0> = 111, Reserved
S0BUF<7>
UART data buffer
SM<0>
UART Mode selection bits

SM<0:1> = 00, Shift Register
SM<0:1> = 01, 8-bit UART (variable baud rate)
SM<0:1> = 10, 9-bit UART
SM<0:1> = 11, 9-bit UART (variable baud rate)
Enables the multi processor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set, then RI will not be activated, RB8 and S0BUF will not be loaded if the
received 9th data bit is 0. In mode 1, if SM2 is set, then RI will not be activated, RB8 and S0BUF will not be loaded if no valid stop bit was received. In mode 0, SM2 has no
influence.
Enables serial reception. Set by software to enable reception. Cleared by software to disable reception.
TB8
Is the 9th data bit that will be transmitted in modes 2 and 3. Set or cleared by software as desired.
RB8
In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2 is 0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. Loading of RB8 in modes
1, 2 and 3 depends on SM2.
TI
Is the transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software.
RI
Is the receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see
SM2). Must be cleared by software.
ADR<6:0>
GC
D8H
EN_I2CINT
ENSI
ADR<6>
ADR<5>
ADR<4>
ADR<3>
ADR<2>
ADR<1>
ADR<0>
GC
00H
STA
STO
SI
AA
00H
I2C Slave Address

0 - Disable I2C general call address
1 - Enable I2C general call address
EN_I2CINT
ENSI
Setting by software
0- the I2C interrupt signal is always non-active
1- the I2C interrupt signal is activated when if the SI is set
0 - Disable I2C interface
1 - Enable I2C interface
STA
START flag. When this bit is set in slave mode, the hardware checks the I2C bus and generates a START condition if the bus is free or after the bus becomes free. If the device
operates in master mode it will generate a repeated START condition.
STO
STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C bus clears this bit. This bit may also be set in slave mode in
order to recover from an error condition. In this case no STOP condition is generated to the I2C bus, but the hardware releases the SDA and SCL lines and switches to the not
selected receiver mode. The STOP flag is cleared by the hardware
SI
2003 Nov 11
BIT6
REN
DBH
S1CON
BIT7
UOCIII series
Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur:
-A START condition is generated in master mode.
-The own slave address has been received during AA=1
-The general call address has been received while S1ADR.GC and AA=1
-A data byte has been received or transmitted in master mode (even if arbitration is lost)
-A data byte has been received or transmitted as selected slave
A STOP or START condition is received as selected slave receiver or transmitter
While the SI flag is set, SCL remains LOW and the serial transfer is suspened.SI must be reset by software.
41
CONFIDENTIAL

Names
Add
AA
S1DAT
BIT7
S1STA
D9H
STAT<4:0>
SAD
E8H
VHI
CH<1:0>
ST
SAD<7:4>
SADB
98H
SSD_ON
DC_COMP
SAD<3:0>
SCAVTXT
F9H
SCAVEM_EN
PULSE_WIDTH<1:0>
EARLY<2:0>
SP
81H
SP<7>
TCON
2003 Nov 11
88H
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions
-Own slave address is received.
-General call address is received(S1ADR.GC=1)
-A data byte is received, while the device is programmed to be a master receiver
-A data byte is received, while the device is selected slave receiver
When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received.
DAH
DAT<7:0>
BIT6
UOCIII series
DAT<7>
I2C
DAT<6>
DAT<5>
DAT<4>
DAT<3>
DAT<2>
DAT<1>
DAT<0>
00H
STAT<3>
STAT<2>
STAT<1>
STAT<0>
F8H
CH<1>
CH<0>
ST
SAD<7>
SAD<6>
SAD<5>
SAD<4>
00H
Data
STAT<4>
I2C Interface Status
VHI
0 - Analogue input voltage less than or equal to DAC voltage

1 - Analogue input voltage greater then DAC voltage
ADC Input channel select
CH<1:0> = 00,ADC3
CH<1:0> = 01,ADC0
CH<1:0> = 10,ADC1
CH<1:0> = 11,ADC2
Initiate voltage comparison between ADC input Channel and SAD<7:0> value
Note: Set by Software and reset by Hardware
Most Significant nibble of DAC input word
SSD_ON
DC_COMP
SAD<3>
SAD<2>
SAD<1>
SAD<0>
80H
PULSE_
WIDTH<1>
PULSE_
WIDTH<0>
EARLY<2>
EARLY<1>
EARLY<0>
00H
0 - Disable SSD Function

1 - Enable SSD Function
0 - Disable DC Comparator mode
1 - Enable DC Comparator mode
Least Significant nibble of 8 bit SAD value
SCAVEM_
EN
0 - Disable scavem text output for R, G, and B signals

1 - Enable scavem text output for R, G, and B signals
SCAVEM Text signal pulse width
PULSE_WIDTH<1:0>=00, 37ns
SCAVEM Text output to Video Signal Processor earlier than R,G, and B signals
EARLY<2:0>=000, 0 ns
EARLY<2:0>=001, 74 ns
EARLY<2:0>=010, 111 ns
EARLY<2:0>=011, 148 ns
EARLY<2:0>=100, 185 ns
EARLY<2:0>=101, 212 ns
EARLY<2:0>=110, 259 ns
EARLY<2:0>=111, 296 ns
SP<7>
SP<6>
SP<5>
SP<4>
SP<3>
SP<2>
SP<1>
SP<0>
07H
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00H
Stack Pointer
TF1
TF1
Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine
TR1
Timer 1 Run control bit. Set/Cleared by software to turn Timer/Counter on/off
TF0
Timer 0 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine
42
CONFIDENTIAL

Names
Add
TR0
TDACH
BIT7
BIT6
BIT5
Interrupt 1 Type control bit. Set/Cleared by Software to specify edge/low level triggered external interrupts.
IE0
Interrupt 0 Edge l flag. Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.
IT0
Interrupt 0 Type flag.Set/Cleared by Software to specify falling edge/low level triggered external interrupts
TPWE
D2H
TD<7:0>
8CH
TH0<7:0>
8DH
TH1<7:0>
8AH
TL0<7:0>
8BH
TL1<7:0>
TMOD
89H
TD<12>
TD<11>
TD<10>
TD<9>
TD<8>
00H
TD<5>
TD<4>
TD<3>
TD<2>
TD<1>
TD<0>
00H
TH0<6>
TH0<5>
TH0<4>
TH0<3>
TH0<2>
TH0<1>
TH0<0>
00H
TH1<6>
TH1<5>
TH1<4>
TH1<3>
TH1<2>
TH1<1>
TH1<0>
00H
TL0<6>
TL0<5>
TL0<4>
TL0<3>
TL0<2>
TL0<1>
TL0<0>
00H
TL1<6>
TL1<5>
TL1<4>
TL1<3>
TL1<2>
TL1<1>
TL1<0>
00H
TD<7>
TD<6>
Tuning Pulse Width Modulator Low Byte

TH0<7>
Timer 0 high byte
TH1<7>
Timer 1 high byte
TL0<7>
Timer 0 low byte
TL1<7>
Timer 1 low byte
GATE
C/T
M1
M0
GATE
Timer / Counter 1
GATE
C/T
M1,M0
GATE
C/T
M1,M0
TP2CL
9CH
TP2CL<7:0>
TP2CH
9DH
TP2CH<7:0>
2003 Nov 11
RESET
TD<13>
Tuning Pulse Width Modulator High Byte
TL1
BIT0
IT1
TD<13:8>
TL0
BIT1
Interrupt 1 Edge flag (both edges generate flag). Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.
0 - Disable Tuning Pulse Width Modulator

1 - Enable Tuning Pulse Width Modulator
TH1
BIT2
Timer 0 Run control bit. Set/Cleared by software to turn Timer/Counter on/off
TPWE
TH0
BIT3
IE1
D3H
TDACL
BIT4
UOCIII series
C/T
M1
M0
00H
Timer / Counter 0
Gating Control Timer /Counter 1

Counter/Timer 1 selector
Mode control bits Timer/Counter 1
M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler
M1,M0 = 01, 16 bit time interval or event counter
M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH1
M1,M0 = 11, stopped
Gating control Timer/Counter 0
Counter/Timer 0 selector
Mode Control bits Timer/Counter 0
M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler
M1,M0 = 01, 16 bit time interval or event counter
M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH0
M1,M0 = 11, one 8 bit time interval or event counter and one 8 bit time interval counter
TP2CL<7>
TP2CL<6>
TP2CL<5>
TP2CL<4>
TP2CL<3>
TP2CL<2>
TP2CL<1>
TP2CL<0>
00H
TP2CH<4>
TP2CH<3>
TP2CH<2>
TP2CH<1>
TP2CH<0>
00H
Indicate the low byte of the Time 2 current value.

TP2CH<7>
TP2CH<6>
TP2CH<5>
Indicate the high byte of the Time 2 current value.
43
CONFIDENTIAL

Names
Add
TP2H
92H
TP2H<7:0>
TP2L
91H
TP2L<7:0>
TP2PR
93H
TP2PR<7:0>
TP2CRL
94H
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
TP2H<7>
TP2H<6>
TP2H<5>
TP2H<4>
TP2H<3>
TP2H<2>
TP2H<1>
TP2H<0>
00H
TP2L<4>
TP2L<3>
TP2L<2>
TP2L<1>
TP2L<0>
00H
TP2PR<4>
TP2PR<3>
TP2PR<2>
TP2PR<1>
TP2PR<0>
00H
Timer 2 high byte, never change unless updated by the software.

TP2L<7>
TP2PR<7>
Timer 2 Status.
0 - No Overflow.
1 - Overflow.
TXT0
C0H
X24 POSN
DISLAY X24
AUTO FRAME
DISABLE HEADER ROLL
TP2PR<6>
TP2CRL<1>
TEST<7:0>
TP2CRL<1>
TP2CRL<0>
00H
TEST<6>
TEST<5>
TEST<4>
TEST<3>
TEST<2>
TEST<1>
TEST<0>
A0H
DISPLAY X24
AUTO
FRAME
DISABLE
HEADER
ROLL
DISPLAY
STATUS ROW
ONLY
DISABLE
FRAME
VPS ON
INV ON
00H
full-field
FIELD
POLARITY
H POLARITY
V POLARITY
00H
TEST<7>
For internal testing use.
X24 POSN
0 - Store X/24 in extension memory

1 - Store X/24 in basic page memory with packets 0 to 23
0 - Display row 24 from basic page memory
1 - Display row 24 from appropriate location in extension memory
0 - Normal Frame output
1 - Frame output is switched off automatically if any video displayed
0 - Write rolling headers and time to current display page
1 - Disable writing of rolling headers and time to into memory
0 - Display normal page rows 0 to 24
1- Display only row 24
DISABLE FRAME
0 - Normal Frame output

1 - Force Frame output to be low (0)
VPS ON
0 - VPS acquisition off

1 - VPS acquisition on
INV ON
0 - Inventory page off

1 - Inventory page on
C1H
EXT PKT OFF
8 BIT
ACQ OFF
X26 OFF
full-field
2003 Nov 11
TP2PR<5>
DISPLAY STATUS ROW

ONLY
TXT1
TP2L<5>
Timer 2 Pre-scaler, never change unless updated by the software
Timer 2 Control.
0 - Timer 2 disabled.
1 - Timer 2 enabled.
FDH
TP2L<6>
Timer 2 low byte, never change unless updated by the software.
TP2CRL<0>
TEST
UOCIII series
EXT PKT OFF
8 BIT
ACQ OFF
X26 OFF
0 - Acquire extension packets X/24,X/27,8/30/X

1 - Disable acquisition of extension packets
0 - Error check and/or correct packets 0 to 24
1 - Disable checking of packets 0 to 24 written into memory
0 - Write requested data into display memory
1 - Disable writing of data into Display memory
0 - Enable automatic processing of X/26 data
1 - Disable automatic processing of X/26 data
unused, must keep reset value -> 0
44
CONFIDENTIAL

Names
Add
FIELD POLARIY
BIT7
BIT6
BIT5
0 - Hsync reference edge is positive going

1 - Hsync reference edge is negative going
V POLARITY
0 - Vsync reference edge is positive going

1 - Vsync reference edge is negative going
C2H
ACQ_BANK<0>
REQ<3:0>
SC<2:0>
TXT3
C3H
ACQ_BANK
<3:1>
PRD<4:0>
TXT4
C4H
OSD BANK ENABLE
QUAD WIDTH ENABLE
EAST/WEST
DISABLE DOUBLE
HEIGHT
TRANS ENABLE
SHADOW ENABLE
TXT5
C5H
BKGND OUT
BKGND IN
2003 Nov 11
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
REQ<2>
REQ<1>
REQ<0>
SC<2>
SC<1>
SC<0>
00H
ACQ
BANK<1>
PRD<4>
PRD<3>
PRD<2>
PRD<1>
PRD<0>
00H
DISABLE
DBL HEIGHT
TRANS
ENABLE
SHADOW
ENABLE
00H
TEXT OUT
TEXT IN
PICTURE ON
OUT
PICTURE ON
IN
03H
0 - Vsync pulse in first half of line during even field

1 - Vsync pulse in second half of line during even field
For MCM package, this bit should be set to 1
H POLARITY
TXT2
UOCIII series
ACQ
BANK<0>
REQ<3>
Should combine TXT3 ACQ_BANK<3:1>

Page request
Start column of page request
ACQ
BANK<3>
ACQ
BANK<2>
Combine with TXT2 ACQ_BANK<0>

0000 - Select BLOCK 0 ~ 9 for acquisition storage
0001 - Reserved
0010 - Reserved
0011 - Reserved
0100 - Reserved
0101 - Reserved
0110 - Reserved
0111 - Reserved
1000 - Reserved
1001 - Reserved
1010 - Reserved
1011 - Reserved
1100 - Reserved
1101 - Reserved
1110 - Reserved
1111 - Reserved
Page Request data
OSD BANK
ENABLE
QUAD
WIDTH
ENABLE
EAST/WEST
0 - Only alpha numeric OSD characters available, 32 locations

1 - Alternate OSD location available via graphic attribute, additional 32 location
0 - Disable display of Quadruple width characters
1 - Enable display of Quadruple width characters
0 - Western language selection of character codes A0 to FF
1 - Eastern character selection of character codes A0 to FF
0 - Allow normal decoding of double height characters
1 - Disable normal decoding of double height characters
0 - Display black background as normal
1 - Display black background as video
0 - Disable display of shadow/fringing
1 - Display shadow/ fringe (default SE black)
BKGND OUT
BKGND IN
COR OUT
COR IN
0 - Background colour not displayed outside teletext boxes(teletext page)

1 - Background colour displayed outside teletext boxes(teletext page)
0 - Background colour not displayed inside teletext boxes(teletext page)
1 - Background colour displayed inside teletext boxes(teletext page)
45
CONFIDENTIAL

Names
Add
COR OUT
COR IN
TEXT OUT
TEXT IN
PICTURE ON OUT
PICTURE ON IN
TXT6
C6H
BKGND OUT
BKGND IN
COR OUT
COR IN
TEXT OUT
TEXT IN
PICTURE ON OUT
PICTURE ON IN
TXT7
C7H
STATUS ROW TOP
CURSOR ON
REVEAL
BOTTOM/TOP
DOUBLE HEIGHT
BOX ON 24
BOX ON 1-23
BOX ON 0
2003 Nov 11
BIT7
BIT6
BIT5
UOCIII series
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
COR IN
TEXT OUT
TEXT IN
PICTURE ON
OUT
PICTURE ON
IN
03H
DOUBLE
HEIGHT
BOX ON 24
BOX ON 1-23
BOX ON 0
00H
0 - COR not active outside teletext and OSD boxes(teletext page)

1 - COR active outside teletext and OSD boxes(teletext page)
0 - COR not active inside teletext and OSD boxes(teletext page)
1 - COR active inside teletext and OSD boxes(teletext page)
0 - TEXT not displayed outside teletext boxes(teletext page)
1 - TEXT displayed outside teletext boxes(teletext page)
0 - TEXT not displayed inside teletext boxes(teletext page)
1 - TEXT displayed inside teletext boxes(teletext page)
0 - VIDEO not displayed outside teletext boxes(teletext page)
1 - VIDEO displayed outside teletext boxes(teletext page)
0 - VIDEO not displayed inside teletext boxes(teletext page)
1 - VIDEO displayed inside teletext boxes(teletext page)
BKGND OUT
BKGND IN
COR OUT
0 - Background colour not displayed outside teletext boxes(newsflash/subtitle)

1 - Background colour displayed outside teletext boxes(newsflash/subtitle)
0 - Background colour not displayed inside teletext boxes(newsflash/subtitle)
1 - Background colour displayed inside teletext boxes(newsflash/subtitle)
0 - COR not active outside teletext and OSD boxes(newsflash/subtitle)
1 - COR active outside teletext and OSD boxes(newsflash/subtitle)
0 - COR not active inside teletext and OSD boxes(newsflash/subtitle)
1 - COR active inside teletext and OSD boxes(newsflash/subtitle)
0 - TEXT not displayed outside teletext boxes(newsflash/subtitle)
1 - TEXT displayed outside teletext boxes(newsflash/subtitle)
0 - TEXT not displayed inside teletext boxes(newsflash/subtitle)
1 - TEXT displayed inside teletext boxes(newsflash/subtitle)
0 - VIDEO not displayed outside teletext boxes(newsflash/subtitle)
1 - VIDEO displayed outside teletext boxes(newsflash/subtitle)
0 - VIDEO not displayed inside teletext boxes(newsflash/subtitle)
1 - VIDEO displayed inside teletext boxes(newsflash/subtitle)
STATUS ROW
TOP
CURSOR ON
REVEAL
BOTTOM/
TOP
0 - Display memory row 24 information below teletext page (on display row 24)
1 - Display memory row 24 information above teletext page (on display row 0)
0 - Disable display of cursor
1 - Display cursor at position given by TXT9 and TXT10
0 - Display as spaces characters in area with conceal attribute set
1 - Display characters in area with conceal attribute set
0 - Display memory rows 0 to 11 when double height bit is set
1 - Display memory rows 12 to 23 when double height bit is set
0 - Display each characters with normal height
1 - Display each character as twice normal height.
0 - Disable display of teletext boxes in memory row 24
1 - Enable display of teletext boxes in memory row 24
0 - Disable display of teletext boxes in memory row 1 to 23
1 - Enable display of teletext boxes in memory row 1 to 23
0 - Disable display of teletext boxes in memory row 0
1 - Enable display of teletext boxes in memory row 0
46
CONFIDENTIAL

Names
Add
TXT8
C8H
FLICKER STOP ON
HUNT
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
(Reserved)
0
FLICKER
STOP ON
HUNT
DISABLE
SPANISH
PKT 26
RECEIVED
WSS
RECEIVED
WSS ON
(Reserved)
0
00H
R<4>
R<3>
R<2>
R<1>
R<0>
00H
C<4>
C<3>
C<2>
C<1>
C<0>
00H
D<4>
D<3>
D<2>
D<1>
D<0>
00H
ROM VER<1>
ROM VER<0>
VIDEO
SIGNAL
QUALITY
xxxxxx1xB
0 - Enable Flicker Stopper circuitry

1 - Disable Flicker Stopper circuitry
0 - Allow automatic hunting for amplitude of data to be acquired
1 - Disable automatic hunting for amplitude
DISABLE SPANISH
0 - Enable special treatment of Spanish packet 26 characters

1 - Disable special treatment of Spanish packet 26 characters
PKT 26 RECEIVED
0 - No packet 26 data has been processed

1 - Packet 26 data has been processed.
Note: This flag is set by Hardware and must be reset by Software
WSS RECEIVED
0 - No Wide Screen Signalling data has been processed

1 - Wide Screen signalling data has been processed
Note: This flag is set by Hardware and must be reset by Software.
WSS ON
TXT9
C9H
0 - Disable acquisition of WSS data.

1 - Enable acquisition of WSS data.
CURSOR
FREEZE
CLEAR
MEMORY
A0
CURSOR FREEZE
0 - Use current TXT9 and TXT10 values for cursor position.

1 - Lock cursor at current position
CLEAR MEMORY
0 - Clear memory action is finished

1 - Clear memory block pointed to by TXT15
Note: This flag is set by Software and reset by Hardware
A0
R<4:0>
TXT10
CAH
CHAR A 16/12
C<5:0>
TXT11
CBH
TXT12
0 - Access memory block pointed to by TXT15

1 - Access extension packet memory
Current memory ROW value.
Note: Valid range TXT mode 0 to 24, CC mode 0 to 15
CHAR
16/12
CCH
C<5>
Character Matrix width on Display Page A and B

0 - 12 pixel width
1 - 16 pixel width
Current memory COLUMN value.
Note: Valid range TXT mode 0 to 39, CC mode 0 to 47
D<7>
D<7:0>
D<6>
D<5>
Data value written or read from memory location defined by TXT9, TXT10 and TXT15
625/525 SYNC
ROM VER<4>
ROM VER<3>
ROM VER<2>
625/525 SYNC
0 - 625 line CVBS signal is being received

1 - 525 line CVBS signal is being received
ROM VER<4>
Mask programmable identification for character set

ROM Version <4>:
0 - Spanish Flicker Stopper Disabled.
1 - Spanish Flicker Stopper Enabled (Controlled by TXT8 Bit-6).
ROM VER<3:0>
General purpose register, bits defined by mask programmable bits
1
VIDEO SIGNAL
QUALITY
2003 Nov 11
UOCIII series
Reserved
0 - Acquisition can not be synchronised to CVBS input.
1 - Acquisition can be synchronised to CVBS
47
CONFIDENTIAL

Names
Add
TXT13
F8H
VPS RECEIVED
PAGE CLEARING
525 DISPLAY
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
VPS
RECEIVED
PAGE
CLEARING
525 DISPLAY
525 TEXT
625 TEXT
PKT 8/30
FASTEXT
xxxxxxx0B
DISPLAY
BANK<1>
DISPLAY
BANK<0>
PAGE<3>
PAGE<2>
PAGE<1>
PAGE<0>
00H
MICRO
BANK<1>
MICRO
BANK<0>
BLOCK<3>
BLOCK<2>
BLOCK<1>
BLOCK<0>
00H
0 - VPS data not being received

1 - VPS data being received
0 - No page clearing active
1 - Software or Power On page clear in progress
0 - 625 Line synchronisation for Display
1 - 525 Line synchronisation for Display
525 TEXT
0 - 525 Line WST not being received

1 - 525 line WST being received
625 TEXT
0 - 625 Line WST not being received

1 - 625 line WST being received
PKT 8/30
FASTEXT
0
TXT14
CDH
DISPLAY
BANK <3:0>
PAGE<3:0>
TXT15
CEH
MICRO
BANK<3:0>
BLOCK<3:0>
TXT17
2003 Nov 11
B9H
UOCIII series
0 - No Packet 8/30/x(625) or Packet 4/30/x(525) data detected

1 - Packet 8/30/x(625) or Packet 4/30/x(525) data detected
0 - No Packet x/27 data detected
1 - Packet x/27 data detected
Reserved
DISPLAY
BANK<3>
DISPLAY
BANK<2>
0000 - Select Page 0 ~ 9 for Display

0001 - Reserved
0010 - Reserved
0011 - Reserved
0100 - Reserved
0101 - Reserved
0110 - Reserved
0111 - Reserved
1000 - Reserved
1001 - Reserved
1010 - Reserved
1011 - Reserved
1100 - Reserved
1101 - Reserved
1110 - Reserved
1111 - Reserved
Current Display page
MICRO
BANK<3>
MICRO
BANK<2>
0000 - Select BLOCK 0 ~ 9 for Micro

0001 - Reserved
0010 - Reserved
0011 - Reserved
0100 - Reserved
0101 - Reserved
0110 - Reserved
0111 - Reserved
1000 - Reserved
1001 - Reserved
1010 - Reserved
1011 - Reserved
1100 - Reserved
1101 - Reserved
1110 - Reserved
1111 - Reserved
Current Micro block to be accessed by TXT9, TXT10 and TXT11
0
FORCE
ACQ<1>
FORCE
ACQ<0>
FORCE
DISP<1>
FORCE
DISP<0>
48
CONFIDENTIAL
SCREEN
COL2
SCREEN
COL1
SCREEN
COL0
00H

Names
Add
BIT7
BIT6
BIT5
FORCE ACQ<1:0>
00 - Automatic Selection
01 - Force 525 timing, Force 525 Teletext Standard
FORCE DISP<1:0>
00 - Automatic Selection
01 - Force Display to 525 mode (9 lines per row)
10 - Force Display to 625 mode (10 lines per row)
11 - Not Valid (default to 625)
SCREEN COL<2:0>
TXT18
B2H
NOT<3:0>
field_indent
BS<1:0>
TXT19
B3H
TEN
BIT4
NOT<3>
NOT<2>
NOT<1>
NOT<0>
EXTENDED SPECIAL
GRAPHICS
CHAR SELECT ENABLE
OSD LANG ENABLE

OSD LAN<2:0>
TXT21
B5H
TEN
TC<2>
TC<1>
RESET
field_indent
BS<1>
BS<0>
00H
TC<0>
TS<1>
TS<0>
00H
OSD
LANG
ENABLE
OSD LAN<2>
OSD LAN<1>
OSD LAN<0>
00H
CC ON
I2C PORT EN
CC/TXT
02H
0 - Disable Twist function

1- Enable Twist character set
DRCS
ENABLE
OSD PLANES
EXTENDED
SPECIAL
GRAPHICS
CHAR
SELECT
ENABLE
0 - Normal OSD characters used

1 - Re-map column 9 to DRCS (TXT and CC modes),
0 - Character code columns 8 and 9 defined as single plane characters
1- Character code columns 8 and 9 defined as double plane characters
0 - Extended Special Graphics disabled (columns 8 & 9 only used for special graphics characters)
1 - Extended Special Graphics enabled (user definable range for special graphics characters)
0 - Disables character set selection in CC display mode
1 - Enables character set selection in CC display mode
Enable use of OSD LAN<2:0> to define language option for display, instead of C12/C13/C14
Alternative C12/C13/C14 bits for use with OSD menus
DISP
LINES<1>
DISP
LINES<0>
CHAR
SIZE<1>
DISP LINES<1:0>
The number of display lines per character row.

00 - 10 lines per character (defaults to 9 lines in 525 mode)
01 - 13 lines per character
CHAR SIZE<1:0>
Character matrix size.
CHAR
SIZE<0>
Reserved 0)
01 - 13 lines per character (matrix 12x13)

2003 Nov 11
BIT0
Basic Character set selection
Twist Character set selection
OSD PLANES
BIT1
TS<1:0>
DRCS ENABLE
BIT2
National Option table selection, maximum of 32 when used with East/West bit
Language control bits (C12/C13/C14) that has Twisted character set
B4H
BIT3
Defines colour to be displayed instead of TV picture and black background. The bits <2:0> are equivalent to the RGB components
000 - Transparent
001 - CLUT entry 9
010 - CLUT entry 10
011- CLUT entry 11
100 - CLUT entry 12
101 - CLUT entry 13
110- CLUT entry 14
111 - CLUT entry 15
TC<2:0>
TXT20
UOCIII series
49
CONFIDENTIAL

Names
Add
CCON
I2C PORT EN
CC/TXT
TXT22
B6H
GPF<7:0>
TXT23
A9H
NOT B<3:0>
EAST/WEST B
DRCS B ENABLE
BS B<1:0>
TXT24
AAH
BKGND OUT B
BKGND IN B
COR OUT B
COR IN B
TEXT OUT B
TEXT IN B
PICTURE ON OUT B
PICTURE ON
IN B
TXT25
ABH
BKGND OUT B
BKGND IN B
COR OUT B
COR IN B
TEXT OUT B
2003 Nov 11
BIT7
BIT6
BIT5
UOCIII series
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
0 - Closed Caption acquisition off

1 - Closed Caption acquisition on
0 - Disable I2C PORT EN
1 - Enable I2C PORT EN selection (P1.7/SDA0, P1.6/SCL0)
0 - Display configured for TXT mode
1 - Display configured for CC mode
GPF<7>
GPF<6>
GPF<5>
GPF<4>
GPF<3>
GPF<2>
GPF<1>
GPF<0>
XXH

NOT B<3>
NOT B<2>
NOT B<1>
NOT B<0>
EAST/WEST
B
DRCS B
ENABLE
BS B<1>
BS B<0>
00H
TEXT OUT B
TEXT IN B
PICTURE ON
OUT B
PICTURE ON
IN B
03H
TEXT OUT B
TEXT IN B
PICTURE ON
OUT B
PICTURE ON
IN B
03H
National Option table selection for Page B, maximum of 32 when used with East/West bit
0 - Western language selection of character codes A0 to FF on Page B
1 - Eastern language selection of character codes A0 to FF on Page B
0 - Normal OSD characters used on Page B
1 - Re-map column 8/9 to DRCS (TXT and CC modes) on Page B
Basic Character set selection for Page B
BKGND OUT
B
BKGND IN B
COR OUT B
COR IN B
0 - Background colour not displayed outside teletext boxes (Teletext page)

1 - Background colour displayed outside teletext boxes (Teletext page)
0 - Background colour not displayed inside teletext boxes (Teletext page)
1 - Background colour displayed inside teletext boxes (Teletext page)
0 - COR not active outside teletext and OSD boxes (Teletext page)
1 - COR active outside teletext and OSD boxes (Teletext page)
0 - COR not active inside teletext and OSD boxes (Teletext page)
1 - COR active inside teletext and OSD boxes (Teletext page)
0 - TEXT not displayed outside teletext boxes (Teletext page)
1 - TEXT displayed outside teletext boxes (Teletext page)
0 - TEXT not displayed inside teletext boxes (Teletext page)
1 - TEXT displayed inside teletext boxes (Teletext page)
0 - VIDEO not displayed outside teletext boxes (Teletext page)
1 - VIDEO displayed outside teletext boxes (Teletext page)
0 - VIDEO not displayed inside teletext boxes (Teletext page)
1 - VIDEO displayed inside teletext boxes (Teletext page)
BKGND OUT
B
BKGND IN B
COR OUT B
COR IN B
0 - Background colour not displayed outside teletext boxes (Sub-Title / Newsflash page)
1 - Background colour displayed outside teletext boxes (Sub-Title / Newsflash page)
0 - Background colour not displayed inside teletext boxes (Sub-Title / Newsflash page)
1 - Background colour displayed inside teletext boxes (Sub-Title / Newsflash page)
0 - COR not active outside teletext and OSD boxes (Sub-Title / Newsflash page)
1 - COR active outside teletext and OSD boxes (Sub-Title / Newsflash page)
0 - COR not active inside teletext and OSD boxes (Sub-Title / Newsflash page)
1 - COR active inside teletext and OSD boxes (Sub-Title / Newsflash page)
0 - TEXT not displayed outside teletext boxes (Sub-Title / Newsflash page)
1 - TEXT displayed outside teletext boxes (Sub-Title / Newsflash page)
50
CONFIDENTIAL

Names
Add
TEXT IN B
PICTURE ON OUT B
PICTURE ON IN B
TXT26
ACH
BIT7
BIT6
BIT5
UOCIII series
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
SHADOW
ENABLE B
BOX ON 24 B
BOX ON 1-23
B
BOX ON 0 B
03H
SCR B<2>
SCR B<1>
SCR B<0>
00H
PAGE B<0>
00H
0 - TEXT not displayed inside teletext boxes (Sub-Title / Newsflash page)

1 - TEXT displayed inside teletext boxes (Sub-Title / Newsflash page)
0 - VIDEO not displayed outside teletext boxes (Sub-Title / Newsflash page)
1 - VIDEO displayed outside teletext boxes (Sub-Title / Newsflash page)
0 - VIDEO not displayed inside teletext boxes (Sub-Title / Newsflash page)
1 - VIDEO displayed inside teletext boxes (Sub-Title / Newsflash page)
EXTENDED
DRCS
TRANS B
EXTENDED DRCS
0 - Columns 8/9 mapped to DRCS when DRCS characters enabled (32 DRCS characters)
1 - Columns 8/9/A/C mapped to DRCS when DRCS characters enabled (64 DRCS characters)
TRANS ENABLE B
0 - Display black background as normal on Page B

1 - Display black background as video on Page B
SHADOW ENABLE B
BOX ON 24 B
BOX ON 1-23 B
BOX ON 0 B
TXT27
B1H
RDS ON
SCR B<2:0>
TXT28
ADH
DISPLAY BANK
B<3:0>
PAGE B<3:0>
TXT29
2003 Nov 11
E1H
0 - Disable display of shadow/fringing on Page B

1 - Display shadow/ fringe (default SE black) on Page B
0 - Disable display of teletext boxes in memory row 24 of Page B
1 - Enable display of teletext boxes in memory row 24 of Page B
0 - Disable display of teletext boxes in memory row 1 to 23 of Page B
1 - Enable display of teletext boxes in memory row 1 to 23 of Page B
0 - Disable display of teletext boxes in memory row 0 of Page B
1 - Enable display of teletext boxes in memory row 0 of Page B
-
RDS ON
0 - RDS/RBDS disable
1 - RDS/RBDS enable
Defines colour to be displayed instead of TV picture and black background for Page B. The bits <2:0> are equivalent to the RGB components
000 - Transparent
001 - CLUT entry 9
010 - CLUT entry 10
011 - CLUT entry 11
100 - CLUT entry 12
101 - CLUT entry 13
110 - CLUT entry 14
111 - CLUT entry 15
DISPLAY
BANK B<3>
DISPLAY
BANK B<2>
DISPLAY
BANK B<1>
DISPLAY
BANK B<0>
PAGE B<3>
PAGE B<2>
PAGE B<1>
0000 - Select Page 0 ~ 9 for Display Page B

0001 - Reserved
0010 - Reserved
0011 - Reserved
0100 - Reserved
0101 - Reserved
0110 - Reserved
0111 - Reserved
1000 - Reserved
1001 - Reserved
1010 - Reserved
1011 - Reserved
1100 - Reserved
1101 - Reserved
1110 - Reserved
1111 - Reserved
Current Display page for Page B
TEN B
TS B <1>
TS B <0>
OSD PLANES
B
OSD LANG
ENABLE B
51
CONFIDENTIAL
OSD LAN B
<2>
OSD LAN B
<1>
OSD LAN B
<0>
00H

Names
Add
TEN B
TS B<1:0>
OSD PLANES B
OSD LANG ENABLE B
OSD LAN B <2:0>
TXT30
BIT7
BOTTOM/TOP
B
BIT5
BIT4
BIT3
BIT1
BIT0
RESET
STATUS ROW
TOP B
DISPLAY X24
B
DISPLAY
STATUS ROW
ONLY B
00H
GPF<11>
GPF<10>
GPF<9>
GPF<8>
0XH
9FF<8>
9FF<7>
9FF<6>
9FF<5>
XXH
BFE<3>
BFE<2>
BFE<1>
BFE<0>
XXH
BFE<11>
BFE<10>
BFE<9>
BFE<8>
XXH
GPF<13>
GPF<12>
XXH
Twist Character set selection for Page B

0 - Character code columns 8 and 9 defined as single plane characters for Display Page B
1 - Character code columns 8 and 9 defined as double plane characters (special graphics characters) for Display Page B
Enable use of OSD LAN<2:0> to define language option for display, instead of C12/C13/C14 for Display Page B
Alternative C12/C13/C14 bits for use with OSD menus for Display Page B
TC B <2>
TC B <1>
TC B <0>
DOUBLE
HEIGHT
B
BOTTOM/
TOP B
Language control bits (C12/C13/C14) that has Twisted character set for Page B
0 - Display memory rows 0 to 11 when double height bit is set on Display Page B
1 - Display memory rows 12 to 23 when double height bit is set on Display Page B
DOUBLE HEIGHT B
0 - Display each characters with normal height on Display Page B

1 - Display each character as twice normal height on Display Page B
STATUS ROW TOP B
0 - Display memory row 24 information below teletext page (on display row 24) on Display Page B
1 - Display memory row 24 information above teletext page (on display row 0) on Display Page B
DISLAY X24 B
DISPLAY STATUS ROW

ONLY B
TXT31
A1H
CC/TXT B
ACTIVE PAGE
1V8GUARD
GPF<11:8>
TXT32
A2H
GPF<11>,9FF<11:5>
TXT33
A3H
BFE<7:0>
TXT34
A4H
BFE<15:8>
TXT35
F7H
9FF<15:12>, GPF<15:12>
TXT36
FCH
BFF<4:0>
Video_process
2003 Nov 11
A5H
BIT2
0 - Disable Twist function for Page B

1 - Enable Twist character set for Page B
E2H
TC B<2:0>
BIT6
UOCIII series
0 - Display row 24 from basic page memory on Display Page B

1 - Display row 24 from appropriate location in extension memory on Display Page B
0 - Display normal page rows 0 to 24 on Display Page B
1 - Display only row 24 on Display Page B
0
CC_TXT B
ACTIVE
PAGE
1V8GUARD
0 - Display Page B configured for TXT mode

1 - Display Page B configured for CC mode
0 - Display Page A active during two page mode
1 - Display Page B active during two page mode
0 - 1.8V supply is normal
1 - 1.8Vsupply is abnormal (1.44V)
GPF<11>
9FF<11>
9FF<10>
9FF<9>

BFE<7>
BFE<6>
BFE<5>
BFE<4>

BFE<15>
BFE<14>
BFE<13>
BFE<12>

9FF<15>
9FF<14>
9FF<13>
9FF<12>
GPF<15>
GPF<14>

-
BFF<4>
BFF<3>
BFF<2>
BFF<1>
BFF<0>
XXH
DW_PA<1>
DW_PA<0>
00H

-
52
CONFIDENTIAL

Names
Add
DW_PA<1:0>
WDT
FFH
WDV<7:0>
WDTKEY
FEH
WKEY<7:0>
WSS1
BAH
WSS<3:0> ERROR
WSS<3:0>
WSS2
BBH
WSS<7:4> ERROR
WSS<7:4>
WSS3
BCH
WSS<13:11> ERROR
WSS<13:11>
WSS<10:8> ERROR
WSS<10:8>
XRAMP
FAH
XRAMP<7:0>
2003 Nov 11
BIT7
BIT6
BIT5
BIT4
UOCIII series
BIT3
BIT2
BIT1
BIT0
RESET
Double Window and Panorama feature selection:00- normal mode (both Double Window and Panorama are disable)
01 - Double Window mode enable; the others are disable
10 - Linear scaling mode enable, the others are disable
11 - non-Linear scaling mode enable, the others are disable
WDV<7>
WDV<6>
WDV<5>
WDV<4>
WDV<3>
WDV<2>
WDV<1>
WDV<0>
00H
WKEY<5>
WKEY<4>
WKEY<3>
WKEY<2>
WKEY<1>
WKEY<0>
00H
Watch Dog Timer period

WKEY<7>
WKEY<6>
Watch Dog Timer Key

Note: Must be set to 55H to disable Watch dog timer when active
0
WSS<3:0>
ERROR
WSS<3>
WSS<2>
WSS<1>
WSS<0>
00H
WSS<7:4>
ERROR
WSS<7>
WSS<6>
WSS<5>
WSS<4>
00H
0 - No error in WSS<3:0>
1 - Error in WSS<3:0>
Signalling bits to define aspect ratio (group 1)
0
0 - No errors in WSS<7:4>
Signalling bits to define enhanced services (group 2)
WSS<13:11>
ERROR
WSS<13>
WSS<12>
WSS<11>
WSS<10:8>
ERROR
WSS<10>
WSS<9>
WSS<8>
00H
XRAMP<4>
XRAMP<3>
XRAMP<2>
XRAMP<1>
XRAMP<0>
00H
Signalling bits to define reserved elements (group 4)
1 - Error in WS<10:8>
Signalling bits to define subtitles (group 3)
XRAMP<7>
XRAMP<6>
XRAMP<5>
Internal RAM access upper byte address
53
CONFIDENTIAL

UOCIII series
External (MOVX) Memory

The normal 80C51 external memory area has been
mapped internally to the device, this means that the MOVX
instruction accesses data memory internal to the device.
The movx memory map is shown in Fig.13.
FFH
FFFFH
(XRAMP)=FFH
00H
FFH
FF00H
FEFFH
(XRAMP)=FEH
FFFFH
7FFFH
MOVX @Ri, A
MOVX A, @Ri
7500H
74FFH
00H
FE00H
FFH
RDS/RBDS Display Data
MOVX @DPTR,A
MOVX A,@DPTR
01FFH
(XRAMP)=01H
7000H
6FFFH
00H
FFH
0100H
00FFH
(XRAMP)=00H
9100H
90FFH
Display RAM
for
TEXT PAGES
00H
Dynamically
Re-definable
Characters
Fig.14 Indirect addressing

(Movx address space)
8800H
87FFH
Display Registers
87E0H
Power-on Reset
Power on reset is generated internally to the UOCIII
device, hence no external reset circuitry is required.
871FH
CLUT
2000H
8700H
Software Reset
The UOCIII features a software reset (ROMBK SFR, bit 6),
which can be used by the micro-controller to reset the
following functions/blocks: stereo sound decoder, RDS,
ISP, acquisition, display, display RAM and double
window/panorama. The software reset is executed by
initially setting the corresponding bit to 1 followed by
clearing the bit to 0. It takes approximately 200 s to
complete the internal reset sequence.Please note the
micro-controller, its peripherals (e.g. timers) and program
flash are not reset.
84FFH
0FFFH
Data RAM
0000H
Lower 32K bytes
0000H
Display RAM
for
Closed Caption(1)
8000H
Upper 32K bytes
(1) Display RAM for Closed Caption, Text, RDS/RBDS is shared
Fig.13 Movx Address Map
Power Saving modes of Operation

There are three Power Saving modes, Stand-by, Idle and
Power Down, incorporated into the TCG micro-controller
(Text/Control/Graphic micro-controller) die. When utilizing
either mode, the 3.3V power to the device (Vddp & Vdda)
should be maintained. The analogue blocks are
powered-down and the clocks to various digital blocks are
disabled to minimize the power consumption. The +1.8 V
analogue supplies can be switched off.The internally
generated 1.8V will be maintained to supply the power of
80c51 and pads.
Auxiliary RAM Page Selection

The Auxiliary RAM page pointer is used to select one of
the 256 pages within the auxiliary RAM, not all pages are
allocated, refer to Fig. 14. A page consists of 256
consecutive bytes. XRAMP only works on internal MOVX
memory.
Stand-by Mode
During Stand-by mode, the Acquisition, Display, RDS, and
SSD sections of the device are disabled. This includes
analog modules, such A/D and D/A converter. Before
2003 Nov 11
54
CONFIDENTIAL

UOCIII series
A second method of exiting Idle is via an Interrupt
generated by the SAD DC Compare circuit. When TCG
micro-controller is configured in this mode, detection of
an analogue threshold at the input to the SAD may be
used to trigger wake-up of the device i.e. TV Front Panel
Key-press. As above, the interrupt is serviced, and
following the instruction RETI, the next instruction to be
executed will be the one following the instruction that put
the device into Idle.
entering standby-mode, the SSD will be allowed to

soft-mute the audio outputs. After the required 32 ms, the
video processor is powered-down and the following
functions remain active: 80c51 CPU Core
I2C
RCP (Remote Control Pre-processor)
Timer/Counters
The third method of terminating Idle mode is with a

Power On reset. Reset defines all SFRs and Display
memory to a pre-defined state, but maintains all other
RAM values. Code execution commences with the
Program Counter set to 0000.
WatchDog Timer
UART, SAD and PWMs
To enter Stand-by mode, the STANDBY bit in the
ROMBANK register must be set. The contents of the
Display memory are lost. Since the output values on RGB
and VDS are maintained the display output must be
disabled before entering this mode.
This mode should be used in conjunction with both Idle
and Power-Down modes. Hence, prior to entering either
Idle or Power-Down, the STANDBY bit should be set.
Power Down Mode

In Power Down mode the XTAL oscillator is still running.
The contents of all SFRs and Data memory are
maintained. The port pins maintain the values defined by
their associated SFRs.
The power down mode is activated by setting the PD bit in
the PCON register. It is advised to disable the WatchDog
timer prior to entering Power down. Recovery from
Power-Down takes several milli-seconds as the oscillator
must be given time to stabilize.
Idle Mode
During Idle mode, Acquisition, Display, RDS, SSD and the
CPU sections of the device are disabled. The following
functions remain active:-
There are three methods of exiting power down:
I2C
An External interrupt provides the first mechanism for

waking from Power-Down. Since the clock is stopped,
external interrupts needs to be set level sensitive prior to
entering Power-Down. The interrupt is serviced, and
following the instruction RETI, the next instruction to be
executed will be the one after the instruction that put the
device into Power-Down mode.
RCP
Timer/Counters
WatchDog Timer
UART, SAD and PWMs
To enter Idle mode the IDL bit in the PCON register must
be set. The WatchDog timer must be disabled prior to
entering Idle to prevent the device being reset. It is advice
to use the RCP (Remote Control Pre-processor) during the
Idle mode to reduce the false interrupt wake-up of 80c51 in
order to achieve the low power saving mode. The CPU
state is frozen along with the status of all SFRs, internal
RAM contents are maintained, as are the device output pin
values.
A second method of exiting Power-Down is via an

Interrupt generated by the SAD DC Compare circuit.
When TCG micro-controller is configured in this mode,
detection of a certain analogue threshold at the input to
the SAD may be used to trigger wake-up of the device
i.e. TV Front Panel Key-press. As above, the interrupt is
serviced, and following the instruction RETI, the next
instruction to be executed will be the one following the
instruction that put the device into Power-Down.
The third method of terminating the Power-Down mode
is with a Power On reset. Reset defines all SFRs and
Display memory, but maintains all other RAM values.
Code execution commences with the Program Counter
set to 0000.
There are three methods available to recover from Idle: Assertion of an enabled interrupt will cause the IDL bit to
be cleared by hardware, thus terminating Idle mode.
The interrupt is serviced, and following the instruction
RETI, the next instruction to be executed will be the one
after the instruction that put the device into Idle mode.
2003 Nov 11
55
CONFIDENTIAL

To accommodate this, another interrupt ET2PR has been

added to indicate timer overflow.
In addition to the conventional 80c51, four application
specific interrupts are incorporated internally to the device
which have the following functionality:RDS (Radio Data System Interrupt) - This interrupt is
generated when the RDS/RBDS is decoded and available.
The interrupt is activated when DAVN (data available) is
active which is generated by RDS/RBDS subblock.
DET (Supply Dip Monitor Interrupt) - This interrupt is
generated when the supply dip monitor detects at dip of
1.44V on one of the 1.8V supply pins.
CC (Closed Caption Data Ready Interrupt) - This
interrupt is generated when the device is configured for
Closed Caption acquisition. The interrupt is activated at
the end of the currently selected Slice Line as defined in
the CCLIN SFR.
BUSY (Display Busy Interrupt) - An interrupt is
generated when the Display enters either a Horizontal or
Vertical Blanking Period. i.e. Indicates when the
micro-controller can update the Display RAM without
causing undesired effects on the screen. This interrupt can
be configured in one of two modes using the MMR
Configuration Register (Address 87FF, Bit-3 [TXT/V]): TeXT Display Busy: An interrupt is generated on each
active horizontal display line when the Horizontal
Blanking Period is entered.
I/O Facility
I/O PORTS
The IC has 24 I/O lines, each is individually addressable,
or form part of 4 parallel addressable ports which are
port0, port1, port2 and port3.
The I/O cells are designed to transfer 3.3V external (Pad
side) signals to 1.8V internal (core side) signals, vice
versa. And the I/O pads for the bond-out as well as GPIO
have 5V tolerant except the I2C clock pad in High-speed
mode.
PORT TYPE
All individual ports can be programmed to function in one
of four modes, the mode is defined by two Port
Configuration SFRs. The modes available are Open Drain,
Quasi-bidirectional, High Impedance and Push-Pull.
Open Drain
The Open drain mode can be used for bi-directional
operation of a port. It requires an external pull-up resistor,
the pull-up voltage has a maximum value of 5.5V, to allow
connection of the device into a 5V environment.
Quasi bi-directional
The quasi-bidirectional mode is a combination of open
drain and push pull. It requires an external pull-up resistor
to VDDp (nominally 3.3V). When a signal transition from
0->1 is output from the device, the pad is put into push-pull
mode for one clock cycle (81.38ns) after which the pad
goes into open drain mode. This mode is used to speed up
the edges of signal transitions. This is the default mode of
operation of the pads after reset.
Vertical Display Busy: An interrupt is generated on each

vertical display field when the Vertical Blanking Period is
entered.
There are two interrupts connected to the 80c51
micro-controller peripherals as follows: -
High Impedance
The high impedance mode can be used for Input only
operation of the port. When using this configuration the two
output transistors are turned off.
ES2 - I2C Transmit/Receive interrupt.

EUART - UART Receive/Transmit interrupt.
One additional general purpose external interrupt (EX2) is
incorporated into TCG micro-controller and is only
available in QFP128 package.
Push-Pull
The push pull mode can be used for output only. In this
mode the signal is driven to either 0V or VDDp, which is
nominally 3.3V.
INTERRUPT ENABLE STRUCTURE

Each of the individual interrupts can be enabled or
disabled by setting or clearing the relevant bit in the
interrupt enable SFRs (IE and IEN1). All interrupt sources
can also be globally disabled by clearing the EA bit (IE.7).
The EDET interrupt can only be cleared by setting the
corresponding status bits in bit 4 and 7 of TXT31 or bit4
and 5 of ROMBK to 0.
Interrupt System
The device has 12 interrupt sources, each of which can be
enabled or disabled. When enabled, each interrupt can be
assigned one of two priority levels. There are four
interrupts that are common to the 80C51, two of these are
external interrupts (EX0 and EX1) and the other two are
timer interrupts (ET0 and ET1).
The TCG micro-controller family of devices have an
additional 24-bit Timer (16-bit timer with 8-bit pre-scaler).
2003 Nov 11
UOCIII series
56
CONFIDENTIAL

UOCIII series
Source
EX0
ET0
EX1
ET1
EDET
H1
Highest Priority Level1
L1
H2
Highest Priority Level0
003BH
EUART
UART
004BH
L3
H4
ERDS
falling-edge
0053H
L4
H5
EX2
low-level
005BH
Lowest
Table 7
Interrupt Priority (within same level)
INTERRUPT VECTOR ADDRESS

The processor acknowledges an interrupt request by
executing a hardware generated LCALL to the appropriate
servicing routine. The interrupt vector addresses are
shown in Table 7.
L9
H10
EUART
falling-edge
0043H
L8
H9
ET2PR
EBUSY
Timer2
L7
H8
EBUSY
Interrupt Vector
ET2PR
L6
H7
ES2
Trigger Condition
L2
H3
L5
H6
ECC
Priority within level
L10
H11
ERDS
EX2
Interrupt
Source
Source
Enable
IE.0:6
IEN1.0:4
Global
Enable
IE.7
L11
H12
Lowest Priority Level1
L12
Lowest Priority Level0
LEVEL/EDGE INTERRUPT
The external interrupt (EX0 and EX1) can be programmed
to be either level-activated or transition activated by setting
or clearing the IT0/1 bits in the Timer Control SFR(TCON).
Priority
Control
IP.0:6
IP1.0:4
ITx
Fig.15 Interrupt Structure
INTERRUPT ENABLE PRIORITY

Each interrupt source can be assigned one of two priority
levels (High/Low). The interrupt priorities are defined by
the interrupt priority SFRs (IP and IP1). A low priority
interrupt can be interrupted by a high priority interrupt, but
not by another low priority interrupt. A high priority interrupt
can not be interrupted by any other interrupt source. If two
requests of different priority level are received
simultaneously, the request with the highest priority level is
serviced. If requests of the same priority level are received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level
there is a second priority structure determined by the
polling sequence as defined in Table 7.
Source
EX0
Priority within level
0003H
ET0
Timer0
000BH
EX1
low-level or falling-edge
0013H
ET1
Timer1
001BH
EDET
1v8guard
0023H
ECC
high-level
002BH
ES2
low-level
0033H
Level, Active Low
Edge, Negative Edge
Table 8
External Interrupt Activation
Timer/Counter
Two 16 bit timers/counters are incorporated Timer0 and
Timer1. Both can be configured to operate as either timers
or event counters.
In Timer mode, the register is incremented on every
machine cycle. It is therefore counting machine cycles.
Since the machine cycle consists of 6 oscillator periods,
the count rate is 1/6 micro-controller clock(12.288MHz) =
2.048MHz.
In Counter mode, the register is incremented in response
to a negative transition at its corresponding external pin
T0/1. Since the pins T0/1 are sampled once per machine
cycle it takes two machine cycles to recognise a transition,
this gives a maximum count rate of 1/12 micro-controller
clock(12.288MHz)= 1.024MHz.
There are six special function registers used to control the
timers/counters as defined in Table 9.
Interrupt Vector
low-level or falling-edge
Table 7
Highest
Trigger Condition
Interrupt Type
SFR
Address
TCON
88H
TMOD
89H
TL0
8AH
TH0
8BH
Interrupt Priority (within same level)

Table 9
2003 Nov 11
57
CONFIDENTIAL
Timer/Counter Registers

SFR
Address
TL1
8CH
TH1
8DH
Table 9
80C51 based 8-bit micro-controllers - Philips

Semiconductors (ref. IC20) for detail of the modes and
operation.
TL0/TL1 and TH0/TH1 are the actual timer/counter
registers for timer0 / timer1. TL0/TL1 is the low byte and
TH0/TH1 is the high byte.
Timer/Counter Registers
TIMER2 WITH PRE-SCALER

An additional 24-bit Timer (16-bit timer with 8-bit
pre-scaler) is provided to allow timer periods up to 8.192
seconds. This timer remains active during IDLE mode.
TP2L sets the lower value of the period for timer 2 and
TP2H is the upper timer value. TP2PR provides an 8-bit
pre-scaler for timer 2. The value on TP2PR, TP2H and
TP2L shall never change unless updated by the software.
If the micro reads TP2R, TP2H orTP2L at any stage, this
should return the value written and not the current timer 2
value. The timer 2 should continue after overflow by
re-loading (hardware) the timer with the values of SFRs
TP2PR, TP2H and TP2L.
TP2CL and TP2CH indicate the current timer 2 value.
These should be readable both when the timer 2 is active
and inactive. Once the timer 2 is disable, the timer 2 value
at the time of disabling should be maintained on the SFRs
TP2CL and TP2CH. At a count of zero (on TP2CL and
TP2CH), the overflow flag should be set:- TP2CRL<1> - 0
= no timer 2 overflow, 1= timer 2 overflow.
TP2CRL is the control and status for timer 2. TP2CRL.0 is
the timer enable and TP2CRL.1 is the timer overflow
status. The overflow flag will need to be reset by software.
Hence, if required, software may poll flag rather than use
interrupt. Upon overflow an interrupt should also be
generated.
Reset values of all registers should be 00 hex.
TF1 TR TF0 TR IE1 IT1 IE0 IT0

Symbol
Position
Name and Significance
TF1
TCON.7
TR1
TCON.6
TF0
TCON.5
TR0
TCON.4
Timer 1 overflow flag. Set by hardware on timer/counter overflow.

Cleared by hardware when processor
vectors to interrupt routine.
Timer 1 Run control bit. Set/cleared
by software to turn timer.counter
on/off.
Timer 0 overflow flag. Set by hardware on timer/counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.
Timer 0 Run control bit. Set/cleared
by software to turn timer.counter
on/off.
Symbol
Position
IE1
TCON.3
IT1
TCON.2
IE0
TCON.1
IT0
TCON.0
Interrupt 1 Edge flag. Set by hardware

when external interrupt edge
detected. Cleared when interrupt
processed.
Interrupt 1 Type control bit.
Set/cleared by software to specify falling edge/low level triggered external
interrupts.
Interrupt 0 Edge flag. Set by hardware
when external interrupt edge
detected. Cleared when interrupt
processed.
Interrupt 0 Type control bit.
Set/cleared by software to specify falling edge/low level triggered external
interrupts.
Fig.16 Timer/Counter Control (TCON) register
Gat C/T M1 M0 Gat C/T M1 M0

Timer 1
Gate
Timer2 interval = (TP2H * 256 + TP2L) * (TP2PR + 1) * 0.4883us
Timer 0
Gating control when set. Timer/counter is enabled only

while external interrupt 0/1 is high and TR control bit is
set. When cleared timer/counter is enabled whenever TR
control bit is set.
Timer or Counter selector. Cleared for timer operation
(input from system clock). Set for counter operation (input
from T input pin.
C/T
M1
M0
0
0
1
0
1
0
WatchDog Timer
The WatchDog timer is a counter that once in an overflow
state forces the micro-controller in to a reset condition. The
purpose of the WatchDog timer is to reset the
micro-controller if it enters an erroneous processor state
(possibly caused by electrical noise or RFI) within a
reasonable period of time. When enabled, the WatchDog
circuitry will generate a system reset if the user program
fails to reload the WatchDog timer within a specified length
of time known as the WatchDog interval.
The WatchDog timer consists of an 8-bit counter with an
16-bit pre-scaler. The pre-scaler is fed with a signal whose
frequency is 1/6 * 12.288MHz = 2.048MHz. The 8 bit timer
is incremented every t seconds where:
Operating
8048 Timer, TL serves as 5-bit prescaler.
16-bit Timer/Counter, TL and TH are cascaded.
8-bit auto-reload Timer/Counter, TH holds a value
which is to be loaded into TL.
timer 0: two 8-bit Timers/Counters. TL0 is controlled by
timer 0 control bits. TH0 is controlled by timer 1 control
bits. timer 1: stopped.
Fig.17 Timer/Counter Mode control (TMOD)

The Timer/Counter function is selected by control bits C/T
in the Timer Mode SFR (TMOD). These two
Timer/Counter have four operating modes, which are
selected by bit-pairs (M1.M0) in the TMOD. Refer to the
2003 Nov 11
UOCIII series
t=6x65536x1/12.288x106 = 32ms
58
CONFIDENTIAL

WATCHDOG TIMER OPERATION
The WatchDog operation is activated when the WLE bit in
the Power Control SFR (PCON) is set. The WatchDog can
be disabled by Software by loading the value 55H into the
WatchDog Key SFR (WDTKEY). This must be performed
before entering Idle/Power Down mode to prevent exiting
the mode prematurely.
Once activated the WatchDog timer SFR (WDT) must be
reloaded before the timer overflows. The WLE bit must be
set to enable loading of the WDT SFR, once loaded the
WLE bit is reset by hardware, this is to prevent erroneous
Software from loading the WDT SFR.
The value loaded into the WDT defines the WatchDog
interval.
UOCIII series
0.1628us. e.g. if TD<6:0> = 01H then 1 in 128 periods will
be extended by 0.1628us, if TD<6:0>=02H then 2 in 128
periods will be extended.
The TPWM will not start to output a new value until TDACH
has been written to. Therefore, if the value is to be
changed, TDACL should be written before TDACH.
SAD SOFTWARE A/D
Four successive approximation Analogue to Digital
Converters can be implemented in software by making use
of the on board 8-bit Digital to Analogue Converter and
Analogue Comparator.
SAD Control
The control of the required analogue input is done using
the channel select bits CH<1:0> in the SAD SFR, this
selects the required analogue input to be passed to one of
the inputs of the comparator. The second comparator input
is generated by the DAC whose value is set by the bits
SAD<7:0> in the SAD and SADB SFRs. A comparison
between the two inputs is made when the start compare bit
ST in the SAD SFR is set, this must be at least one
instruction cycle after the SAD<7:0> value has been set.
The result of the comparison is given on VHI one
instruction cycle after the setting of ST.
WatchDog interval = (256 - WDT) * t = (256 -WDT) * 32ms.
The range of intervals is from WDT=00H which gives

8.192s to WDT=FFH which gives 32ms.
PORT Alternate Functions
The Ports 0, 1,2 and 3 are shared with alternate functions
to enable control of external devices and circuitry. The
alternate functions are enabled by setting the appropriate
SFR and also writing a 1 to the Port bit that the function
occupies.
PWM PULSE WIDTH MODULATORS
The device has five 6-bit Pulse Width Modulated (PWM)
outputs for analogue control. The PWM outputs generate
pulse patterns with a repetition rate of 10.4166us, with the
high time equal to the PWM SFR value multiplied by
0.1628us. The analogue value is determined by the ratio
of the high time to the repetition time, a D.C. voltage
proportional to the PWM setting is obtained by means of
an external integration network (low pass filter).
VDDP
ADC0
ADC1
MUX
ADC2
4-1
ADC3
+
-
CH<1:0>
PWM Control
The relevant PWM is enabled by setting the PWM enable
bit PWxE in the PWMx Control register. The high time is
defined by the value PWxV<5:0>
SAD<7:0>
VHI
8-bit
DAC
Fig.18 SAD Block Diagram

TPWM TUNING PULSE WIDTH MODULATOR
The device has a single 14-bit PWM that can be used for
Voltage Synthesis Tuning. The method of operation is
similar to the normal PWM except the repetition period is
20.833us.
SAD Input Voltage

The external analogue voltage that is used for comparison
with the internally generated DAC voltage does not have
the same voltage range. The DAC has a lower reference
level of VSSA and an upper reference level of VDDA. The
resolution of the DAC voltage with a nominal value is
3.3/256 ~= 13mV. The external analogue voltage has a
lower value equivalent to VSSA and an upper value
equivalent to VDDP - Vtn, were Vtn is the threshold voltage
for an NMOS transistor. The reason for this is that the input
TPWM Control
Two SFRs are used to control the TPWM, they are TDACL
and TDACH. The TPWM is enabled by setting the TPWE
bit in the TDACH SFR. The most significant bits TD<13:7>
alter the high period between 0 and 20.833us. The 7 least
significant bits TD<6:0> extend certain pulses by a further
2003 Nov 11
59
CONFIDENTIAL

UOCIII series
F/S-mode (Fast/Standard: 12kHz~384kHz)
pins for the analogue signals (P3.0 to P3.3) are 5V tolerant

for normal port operations, i.e. when not used as analogue
input. To protect the analogue multiplexer and comparator
circuitry from the 5V, a series transistor is used to limit the
voltage. This limiting introduces a voltage drop equivalent
to Vtn (~0.6V) on the input voltage. Therefore, for an input
voltage in the range VDDp to VDDp-Vtn the SAD returns the
same comparison value.
Hs-mode can operate up to 2.048 Mbit/s.

Fast-mode can operate up to 384kbit/s, which also covers
Standard-mode (up to 100kHz).
The SCLH-out (Serial CLock line/signal in Hs-mode
system) frequency in Hs-mode is specified in SFR,
HSBIR<4:0>, and in F/S-mode is specified in SFR,
FSBIR<6:0>.
The micro-controller peripheral is controlled by the Serial
Control SFR (S1CON) and its Status is indicated by the
status SFR (S1STA). Information is transmitted/received
to/from the I2C bus using the Data SFR (S1DAT) and the
Slave Address SFR (S1ADR) is used to configure the
slave address of the peripheral.
SAD DC Comparator Mode

The SAD module incorporates a DC Comparator mode
which is selected using the DC_COMP control bit in the
SADB SFR. This mode enables the micro-controller to
detect a threshold crossing at the input to the selected
analogue input pin (P3.0, P3.1, P3.2 or P3.3) of the
Software A/D Converter. A level sensitive interrupt is
generated when the analogue input voltage level at the pin
falls below the analogue output level of the SAD D/A
converter.
This mode is intended to provide the device with a
wake-up mechanism from Power-Down or Idle when a
key-press on the front panel of the TV is detected.
The following software sequence should be used when
utilizing this mode for Power-Down or Idle:1. Disable INT1 using the IE SFR.
Hs-mode
The various serial rates are shown below: -
Reload-value in
HSBIR<4:0>
MOD_CLK divided by
MOD_CLK=12.288MHz
not allowed
2.048MHz
1.365MHz
12
1.024MHz
2. Set INT1 to level sensitive using the TCON SFR.
15
0.819MHz
3. Set the D/A Converter digital input level to the desired

threshold level using the SAD/SADB SFRs and select
the required input pin (P3.0, P3.1, P3.2 or P3,3) using
CH1, CH0 in the SAD SFR.
18
0.6875MHz
21
0.585MHz
24
0.512MHz
4. Enter DC Compare mode by setting the DC_COMP

enable bit in the SADB SFR.
31
96
0.128MHz
5. Enable INT1 using the IE SFR.

Table 10 I2C Serial Rates Hs-mode
6. Enter Power-Down/Idle. Upon wake-up the SAD

should be restored to its conventional operating mode
by disabling the DC_COMP control bit.
I2C Serial I/O Bus
The I2C bus consists of a serial data line (SDA) and a serial
clock line (SCL). The definition of the I2C protocol can be
found in The I2C-bus Specification v2.1, January 2000,
Philips Semiconductor.
The device operates in four modes: Master Transmitter
Master Receiver
Slave Transmitter
Slave Receiver
Each of the 4 modes above can operate at the next speed
modes:
Hs-mode (High speed: 128kHz~2.048MHz) or
2003 Nov 11
60
CONFIDENTIAL

The 80c51 Micro-controller incorporates a full duplex

UART with a single byte receive buffer, meaning that it
commence reception of a second byte before the first is
read form the receive buffer. The UARTs RX and TX pins
connect to P1.4 & P1.5 respectively.
Two registers (S0CON, S0BUF) control the UART along
with SMOD bit of PCON register: -
F/S mode
Reload-value in
FSBIR<6:0>
MOD_CLK divided by
MOD_CLK=12.288MHz
not allowed
16
not allowed
24
not allowed
32
384kHz
40
307kHz
48
256kHz
56
219kHz
64
192kHz
72
170.65kHz
80
168.75kHz
12
104
118.15kHz
14
120
102.4kHz
15
128
96kHz
24
200
61.45kHz
33
272
45.2kHz
37
304
40.4kHz
49
400
30.7kHz
127
1024
12kHz
UOCIII series
SFR
Address
PCON
87H
S0CON
99H
S0BUF
9AH
Table 12 UART Special Function Registers

S0CON
The serial port control and status register is the Special
Function Register S0CON. This register contains not only
the mode selection bits, but also the 9th data bit for
transmit and receive (TB8 and RB8), and the serial port
interrupt bits (TI and RI).
Table 11 I2C Serial Rates F/S mode1

1. F/S-SCL frequencies between 0 and 100 kHz are allowed if the F/S bit in FSBIR is
0 (Standard mode); F/S-SCL frequencies between 0 and 400kHz are allowed if the
F/S-bit in FSBIR is 1 (Fast mode).
I2C Port Enable

One external I2C port is available. This port is enabled
using TXT21.I2C PORT EN. Any information transmitted to
the device can only be acted upon if the port is enabled.
Internal communication between the 80c51
micro-controller and the TV Signal Processor will continue
regardless of the value written to TXT21.I2C PORT EN.
I2S Port Enable
Five external I2S port are available. Each port is enabled
using I2S.EN_I2SDI1, I2S.EN_I2SDO1, I2S.EN_I2SDO2,
I2S.EN_I2SCLK, and I2S.EN_I2SWS. Any information
transmitted/received to/from the device can only be
activated upon if the port is enabled.
UART Peripheral
2003 Nov 11
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CONFIDENTIAL

SM0
SM1
SM2
Symbol
SM0
SM1
SM2
Position
S0CON.7
S0CON.6
S0CON.5
REN
S0CON.4
Symbol
TB8
Position
S0CON.3
RB8
S0CON.2
TI
S0CON.1
REN
TB8
RB8
TI
Mode 0: Serial data enters and exits through RxD. TxD

outputs the shift clock. 8 bits are transmitted/received
(LSB first). The baud rate is fixed at 1/6 the frequency of
clk.
Mode 1: 10 bits are transmitted (through TxD) or received
(through RxD): a start bit (0), 8 data bits (LSB first), and a
stop bit (1). On receive, the stop bit goes into RB8 in
Special Function Register S0CON. The baud rate is
determined by the Timer 1 overflow rate.
(through RxD): start bit (0), 8 data bits (LSB first), a 9th
data bit, and a stop bit (1). On Transmit, the 9th data bit,
TB8 in S0CON, can be assigned the value of 0 or 1. For
example, the parity bit could be moved into TB8. On
receive, the 9th data bit goes into RB8 in S0CON, while the
stop bit is ignored. The baud rate is programmable to
either 1/32 or 1/64 the frequency of the micro-controller
clock.
(through RxD): a start bit (0), 8 data bits (LSB first), a 9th
data bit, and a stop bit (1). In fact, mode 3 is the same as
mode 2 in all respects except baud rate. The baud rate is
determined by the Timer 1 overflow rate.
RI

Mode selection bit 0.
Mode selection bit 1.
Enables the multi processor
communication feature in modes
2 and 3. In mode 2 or 3, if SM2 is
set, then RI will not be activated,
RB8 and S0BUF will not be
loaded if the received 9th data
bit is 0. In mode 1, if SM2 is set,
then RI will not be activated,
RB8 and S0BUF will not be
loaded if no valid stop bit was
received. In mode 0, SM2 has no
influence.
Enables serial reception. Set by
software to enable reception.
Cleared by software to disable
reception.
Is the 9th data bit that will be
transmitted in modes 2 and 3.
Set or cleared by software as
desired.
In modes 2 and 3, RB8 is the 9th
data bit that was received. In
mode 1, if SM2 is 0, RB8 is the
stopbit that was received. In
mode 0, RB8 is not used. Loading of RB8 in modes 1, 2 and 3
depends on SM2.
Is the transmit interrupt flag. Set
by hardware at the end of the 8th
bit time in mode 0, or at the
In all four modes, transmission is initiated by any

instruction that uses S0BUF as a destination register.
Reception is initiated in mode 0 by the condition RI = 0
and REN = 1. In the other modes reception is initiated by
the incoming start bit if REN = 1.
UART Multi-Processor Communications
Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received.
The 9th bit goes into RB8, followed by a stop bit. The port
can be programmed such that when the stop bit is
received, the serial port interrupt will be activated only if
RB8 = 1. This feature is enabled by setting bit SM2 in
S0CON. A way to use this feature in multi-processor
systems is as follows:
When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address
byte which identifies the target slave. An address byte
differs from a data byte. The 9th bit is 1 in an address byte
and 0 in a data byte. With SM2 = 1, no slave will be
interrupted by a data byte reception. An address byte,
however, will interrupt all slaves, so that each slave can
examine the received byte and see if it is being addressed.
The addressed slave will clear its SM2 bit and prepare to
receive the data bytes that will follow. The slaves that
werent being addressed leave their SM2s set and go on
about their business, ignoring the incoming data bytes.
SM2 has no effect in mode 0, and in mode 1 it can be used
to check the validity of the stop bit. When receiving in
Fig.19 S0CON Special Function Registers
S0BUF
This register is implemented twice. Writing to S0BUF
writes to the transmit buffer. Reading from S0BUF reads
from the receive buffer. Only hardware can read from the
transmit buffer and write to the receive buffer.
SMOD bit of PCON
SMOD is the double baud rate bit. If SMOD=1 the baud
rate in mode 1, 2 and 3 is doubled. In mode 0 SMOD is not
used.
UART Modes
The serial port can operate in 4 modes: -
2003 Nov 11
UOCIII series
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CONFIDENTIAL

UOCIII series
Remote Control Pre-processor
The remote control pre-processor is used to reduce the
number of wake-ups for the 80c51 core (from IDLE
mode).
mode 1, if SM2 = 1, the receive interrupt will not be

activated unless a valid stop bit is received.
S0BUF Registers
This register is implemented twice. Writing to S0BUF
writes to the transmit buffer. Reading from S0BUF reads
from the receive buffer. Only hardware can read from the
transmit buffer and write to the receive buffer.
To Start the remote control pre-processor, bit 7 of RCP6

register (SFR address EEH), must be programmed to 1.
Afterward, SW has to program the RCP-SFRs:
UART Baud Rates

NOTE: fclk used in the following calculations refers to the
micro-controller clock frequency (12.288MHz).
The serial port can operate with different baud rates
depending on its mode. The baud rate in mode 0 is derived
from state 2 and state 5 and thus fixed:
Mode 0 baud rate = fclk/ 6
The baud rate in mode 2 depends on the value of bit
SMOD.
Clock divider rate CDIV (= divider between Xtal

and RCP counter)
AL = 75% of the nominal, shortest allowable
LOW pulse
AH = 125% of the nominal, longest allowable
pulse MINUS AL (saves timer span & is easier
for SW)
BL, BH = same as AL, AH, but then for the
HIGH time of the pulse
Because RC5 does not have a real start-pulse (long, with

other timing) the registers AL, AH, BL, BH dont have to
be written every pulse transition.
If SMOD = 0, the baud rate is fclk/32

If SMOD = 1, the baud rate is fclk/16
Further the SW (re-)programs:

SMOD
Mode 2 baud rate =
2
------------------ f clk
32
The baud rates in mode 1 and 3 are determined by the

Timer 1 overflow rate and the value of SMOD as follows:
SMOD
Mode 1, 3 baud rate =
2
------------------ ( Timer1OverflowRate )
32
The Timer 1 interrupt should be disabled in this

application. The Timer itself can be configured for either
timer or counter operation, and in any of its 3 running
modes. In the most typical applications, it is configured for
timer operation, in the auto-reload mode (high nibble of
TMOD = 0010B). In that case the baud rate is given by the
formula:
Mode 1, 3 Baud Rate =
NGP = 0 -> the flag that tells the RCP-HW has

found a timing-error (not in the first pulse) and
so the RC5 message string decoding must be
terminated.
NFP = 0 -> means the RCP-HW is hunting for
the first pulse. If there occurs a timing-error during the first pulse, the micro gets NO wake-up
interrupt. The RCP keeps hunting for a pulse
that matches the start-pulse-timing. (= ideal
for protocols with a ling start-pulse). The
RCP-HW sets NFP=1, to signal that the first
(start-) pulse was found. Further NFP=1 takes
care that any following-pulse-with-error
ALWAYS generates a wake-up interrupt (terminate decoding).
Now the SW goes to sleep in IDLE mode. The Xtal clock

continues, watchdog timer, timer & RCP keep working
(with same Xtal frequency).
SMOD
f clk
2
------------------ -----------------------------------------32
6 ( 256 T1H )
One can achieve very low baud rates with Timer 1 by

leaving the Timer 1 interrupt enabled, and configuring the
Timer to run as a 16-bit timer (high nibble of TMOD =
0001B), and using the Timer 1 interrupt to do a 16-bit
software reload.
When an RC-INT arrives, the micro-core wake-up in

STANDBY mode. Now the SW must read the RCP results
from RA, RB (two 12-bits, folded into 3 SFRS:- RCP3,
RCP4, and RCP5) plus the error flags NFP and NGP.
(note that after the FIRST pulse, the RCP-HW will always
come back with NGP=0).
For further details on the UART operation refer to 80C51

Based 8-Bit Micro-controllers - Philips Semiconductors
(ref. IC20).
When there is an error (NGP=1), then the RC-string

decoding must be terminated (i.e. further, trailing bits will
make an the following string an invalid one).
2003 Nov 11
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CONFIDENTIAL

With NO-ERROR the SW only has to check if RA and RB
are longer than 1x tp (minus 75% of the shortest allowable
pulse=AL) which show whether the pulse had a width of
1x tp or 2x tp.
UOCIII series
At the END of an RC5 string there is a special condition: a
LOW-pulse, followed by a HIGH data-clean time (>2.5tp),
WITHOUT subsequent interrupt. A simple solution is to
load the BH register BEFORE the last pulse with 3xtp
(minus AL). As a consequence you will get an INT after
3tp data clean time: in this special case NGP=1 shows
during 3tp nothing has happened, to the message has
ended OK.
This simplifies the decoding SW considerably (timing

errors are already checked by RCP-HW), for RC5 the
bi-phase decoding-method is similar to the older SW.
If an error NGP=1 is received, then break-off the decoding
and let SW set NFP=0, so that the HW starts hunting
again for the FIRST pulse.
The following table shows the timing characteristics of

some existing Remote Control Protocols:-
Name
RC5
Sony
NEC
Motorola
Japan
Daewoo
Samsung
Denon
Startbit
889us
2.4ms
9ms
3ms
3.38ms
8ms
4.5ms
Shortest
889us
600us
560us
512us
420us
450us
560us
275us
Longest
1178us
1.2ms
1.69ms
1024us
1.27ms
1.45ms
1.69ms
1.9ms
Repeat
113.8ms
45ms
67.5ms
34ms
90ms
60ms
60ms
65ms
Table 13 Remote Control Protocols

I2S Clock Output Selection
The I2S Clock output can be selected via
I2S.I2S_CLK<1:0> SFRs. The output clock is shown in
below:fs=32kHz
I2S.I2S_CLK<1:0>
I2S Clock Output
00
256fs
01
128fs
10
64fs
11
not allowed
information that has been requested. The Display reads

the SRAM information and converts it to RGB output
values.
The display RAM is initialized on power-on to a value of
20H throughout. The contents of the display RAM is not
maintained when entering power saving modes (stand-by,
idle, and power-down). Upon leaving standby mode and
resuming normal operation, the display RAM is initialized
to a value of 20H throughout again (by hardware). The
same applies when a software reset is issued. In this case,
the display RAM is initialized to 20H throughout as well.
The Display RAM occupies a maximum of 20K with an
address range from 2000H to 6FFFH; the TXT14.
DISPLAY BANK<3:0> and TXT15.MICRO BANK<3:0>
must keep default value 0000. The RDS/RBDS Display
Data occupies 1.25K with an address range from 7000H to
74FF H. The three modes although having different
address ranges occupy physical the same SRAM area.
When TXT27.RDS ON = 1, the RDS/RBDS Display
memory would map to the physical SRAM area. When
TXT27.RDS ON=0, TXT21.CC/TXT=1 / 0, then the CC /
TXT memory would map to the physical SRAM area.
Table 14 I2S Clock Output Selection

LED Support
All port pins have a 4mA current sinking capability to
enable LEDs in series with current limiting resistors to be
driven directly, without the need for additional buffering
circuitry.
Data Capture
The Data Capture section takes in the analogue
Composite Video and Blanking Signal (CVBS) from Video
Signal Processor, and from this extracts the required data,
which is then decoded and stored in SFR or memory.
SRAM MEMORY INTERFACE

The SRAM memory interface controls the access to the
embedded SRAM and page clearing. The SRAM is shared
between Data Capture and Display sections. The Data
Capture section uses the SRAM to store acquired
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The extraction of the data is performed in the digital
domain. The first stage is to convert the analogue CVBS
signal into a digital form. This is done using an ADC
sampling at 12.288MHz. The data and clock recovery is
then performed by a Multi-Rate Video Input Processor
(MulVIP). From the recovered data and clock the following
data types are extracted WST Teletext (625/525),Closed
Caption, VPS, WSS(625). The extracted data is stored in
either memory (SRAM) via the SRAM Memory Interface or
in SFR locations.
UOCIII series
Data Standards
The data and clock standards that can be recovered are
shown in Table 15 below:-
Data Capture Features

Video Signal Quality detector.
Data Capture for 625 line WST
Data Standard
Clock Rate
625WST
6.9375 MHz
525WST
5.7272 MHz
VPS
5.0 MHz
625WSS
5.0 MHz
Closed Caption
500 KHz
Table 15 Data Slicing Standards
Data Capture for 525 line WST
Data Capture Timing

The Data Capture timing section uses the Synchronisation
information extracted from the CSI signal to generate the
required Horizontal and Vertical reference timings.
The timing section automatically recognises and selects
the appropriate timings for either 625 (50Hz)
synchronisation or 525 (60Hz) synchronisation. A flag
TXT12.Video Signal Quality is set when the timing section
is locked correctly to the incoming CVBS signal. When
TXT12.Video Signal Quality is set another flag
TXT12.625/525 SYNC can be used to identify the
standard.
Data Capture for US Closed Caption

Data Capture for VPS data (PDC system A)
Data Capture for 625 line Wide Screen Signalling (WSS)
bit decoding
Automatic selection between 525 WST/625WST
Automatic selection between 625WST/VPS on line 16 of
VBI
Real-time capture and decoding for WST Teletext in
Hardware, to enable optimized microprocessor
throughput
Up to 10 pages stored On-Chip
Acquisition
The acquisition sections extracts the relevant information
from the serial stream of data from the MulVIP and stores
it in memory.
Inventory of transmitted Teletext pages stored in the

Transmitted Page Table (TPT) and Subtitle Page Table
(SPT)
Automatic detection of FASTEXT transmission
625 WST ACQUISITION

The family is capable of acquiring 625-line and 525-line
World System Teletext. Teletext pages are identified by
seven numbers: magazine (page hundreds), page tens,
page units, hours tens, hours units, minutes tens and
minutes units. The last four digits, hours and minutes, are
known as the subcode, and were originally intended to be
time related, hence their names.
Real-time packet 26 engine in Hardware for processing

accented, G2 and G3 characters
Signal quality detector for WST/VPS data types
Comprehensive Teletext language coverage
Vertical Blanking Interval (VBI) data capture of WST
data
Analogue to Digital Converter
The CVBS input is passed through a differential to single
ended converter (S/D-Conv+Level-shift). The analogue
output of S/D-Conv+Level-shift is converted into a digital
representation by a Video ADC with a sampling rate of
12.288MHz.
Making a page request

A page is requested by writing a series of bytes into the
TXT3.PRD<4:0> SFR which correspond to the number of
the page required. The bytes written into TXT3 are stored
in a RAM with an auto-incrementing address. The start
address for the RAM is set using the TXT2.SC<2:0> to
define which part of the page request is being written,
TXT2.ACQ_BANK<0> and TXT3.ACQ_BANK<3:1> are
used to define which bank and TXT2.REQ<3:0> is used to
define which of the 10 page requests in the selected bank
Multi Rate Video Input Processor

The multi rate video input processor is a Digital Signal
Processor designed to extract the data and recover the
clock from the digital CVBS signal.
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and to display each page header as it arrives until the

correct page has been found.
When a page request is changed (i.e.: when the TXT3
SFR is written to) a flag (PBLF) is written into bit 5, column
9, row 25 of the corresponding block of the page memory.
The state of the flag for each block is updated every TV
line, if it is set for the current display block, the acquisition
section writes all valid page headers which arrive into the
display block and automatically writes an alpha-numerics
green character into column 7 of row 0 of the display block
every TV line.
When a requested page header is acquired for the first
time, rows 1 to 23 of the relevant memory block are
cleared to space, i.e.: have 20h written into every column,
before the rest of the page arrives. Row 24 is also cleared
if the TXT0.X24 POSN bit is set. If the TXT1.EXT PKT OFF
bit is set the extension packets corresponding to the page
are also cleared.
The last 8 characters of the page header are used to
provide a time display and are always extracted from every
valid page header as it arrives and written into the display
block
The TXT0. DISABLE HEADER ROLL bit prevents any
data being written into row 0 of the page memory except
when a page is acquired off air i.e.: rolling headers and
time are not written into the memory. The TXT1.ACQ OFF
bit prevents any data being written into the memory by the
teletext acquisition section.
When a parallel magazine mode transmission is being
received only headers in the magazine of the page
requested are considered valid for the purposes of rolling
headers and time. Only one magazine is used even if don't
care magazine is requested. When a serial magazine
mode transmission is being received all page headers are
considered to be valid.
is being modified. If TXT2.REQ<3:0> is greater than 09h,

then data being written to TXT3 is ignored. Table 16 shows
the contents of the page request RAM.
Up to 10 pages of teletext can be acquired on the 10 page
device when TXT1.EXT PKT OFF is set to logic 1; and up
to 9 pages can be acquired when this bit is set to logic 0.
If the 'Do Care' bit for part of the page number is set to 0
then that part of the page number is ignored when the
teletext decoder is deciding whether a page being
received off air should be stored or not. For example, if the
Do Care bits for the 4 subcode digits are all set to 0 then
every subcode version of the page will be captured.
Start
Column
Byte
Identification
PRD<4>
PRD<3>
PRD<2>
PRD<1>
PRD<0>
Magazine
DO CARE
HOLD
MAG2
MAG1
MAG0
Page Tens
DO CARE
PT3
PT2
PT1
PT0
Page Units
DO CARE
PU3
PU2
PU1
PU0
Hours Tens
DO CARE
HT1
HT0
Hours Units
DO CARE
HU3
HU2
HU1
HU0
Minutes Tens
DO CARE
MT2
MT1
MT0
Minutes Units
DO CARE
MU3
MU2
MU1
MU0
Error Mode
E1
E0
Table 16 The contents of the Page request RAM

Note: MAG = Magazine PT = Page Tens PU = Page Units
HT = Hours Tens HU = Hours Units
MT = Minutes Tens MU = Minutes Units E = Error check
mode
When the Hold bit is set to 0 the teletext decoder will not
recognise any page as having the correct page number
and no pages will be captured. In addition to providing the
user requested hold function this bit should be used to
prevent the inadvertent capture of an unwanted page
when a new page request is being made. For example, if
the previous page request was for page 100 and this was
being changed to page 234, it would be possible to capture
page 200 if this arrived after only the requested magazine
number had been changed.
The E1 and E0 bits control the error checking which should
be carried out on packets 1 to 23 when the page being
requested is captured. This is described in more detail in a
later section (Error Checking).
For a multi page device, each packet can only be written
into one place in the teletext RAM so if a page matches
more than one of the page requests the data is written into
the area of memory corresponding to the lowest numbered
matching page request.
At power-up each page request defaults to any page, hold
on and error check mode 0.
Error Checking
Before teletext packets are written into the page memory
they are error checked. The error checking carried out
depends on the packet number, the byte number, the error
check mode bits in the page request data and the TXT1.8
BIT bit.
If an uncorrectable error occurs in one of the Hamming
checked addressing and control bytes in the page header
or in the Hamming checked bytes in packet 8/30, bit 4 of
the byte written into the memory is set, to act as an error
flag to the software. If uncorrectable errors are detected in
any other Hamming checked data the byte is not written
into the memory.
Rolling Headers and Time

When a new page has been requested it is conventional
for the decoder to turn the header row of the display green
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UOCIII series
Teletext Memory Organisation

The teletext memory is divided into 10 banks of 10 blocks.
Normally, when the TXT1.EXT PKT OFF bit is logic 0,
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when a page header is received for that page. The bit in

the SPT is set when a page header for the page is received
which has the subtitle page header control bit (C6)
set.The bit for a particular page in the TPT is set when a
page header is received for that page. The bit in the SPT
is set when a page header for the page is received which
has the subtitle page header control bit (C6) set.
each of blocks 0 to 8 contains a teletext page arranged in

the same way as the basic page memory of the page
device and block 9 contains extension packets. When the
TXT1.EXT PKT OFF bit is logic 1, no extension packets
are captured and block 9 of the memory is used to store
another page. The number of the memory block into which
a page is written corresponds to the page request number
which resulted in the capture of the page.
Packet 0, the page header, is split into 2 parts when it is
written into the text memory. The first 8 bytes of the header
contain control and addressing information. They are
Hamming decoded and written into columns 0 to 7 of row
25. Row 25 also contains the magazine number of the
acquired page and the PBLF flag but the last 14 bytes are
unused and may be used by the software, if necessary.
Packet 26 Processing
One of the uses of packet 26 is to transmit characters
which are not in the basic teletext character set. The family
automatically decodes packet 26 data and, if a character
corresponding to that being transmitted is available in the
character set, automatically writes the appropriate
character code into the correct location in the teletext
memory. This is not a full implementation of the packet 26
specification allowed for in level 2 teletext, and so is often
referred to as level 1.5.
By convention, the packets 26 for a page are transmitted
before the normal packets. To prevent the default
character data over writing the packet 26 data the device
incorporates a mechanism which prevents packet 26 data
from being overwritten. This mechanism is disabled when
the Spanish national option is detected as the Spanish
transmission system sends even parity (i.e. incorrect)
characters in the basic page locations corresponding to
the characters sent via packet 26 and these will not over
write the packet 26 characters anyway. The special
treatment of Spanish national option is prevented if
TXT12. ROM VER R4 is logic 0 or if the TXT8.DISABLE
SPANISH is set.
Packet 26 data is processed regardless of the TXT1. EXT
PKT OFF bit, but setting theTXT1.X26 OFF disables
packet 26 processing.
The TXT8. Packet 26 received bit is set by the hardware
whenever a character is written into the page memory by
the packet 26 decoding hardware. The flag can be reset by
writing a 0 into the SFR bit.
Row 25 Data Contents

The Hamming error flags are set if the on-board 8/4
Hamming checker detects that there has been an
uncorrectable (2 bit) error in the associated byte. It is
possible for the page to still be acquired if some of the
page address information contains uncorrectable errors if
that part of the page request was a 'don't care'. There is no
error flag for the magazine number as an uncorrectable
error in this information prevents the page being acquired.
The interrupted sequence (C9) bit is automatically dealt
with by the acquisition section so that rolling headers do
not contain a discontinuity in the page number sequence.
The magazine serial (C11) bit indicates whether the
transmission is a serial or a parallel magazine
transmission. This affects the way the acquisition section
operates and is dealt with automatically.
The newsflash (C5), subtitle (C6), suppress header (C7),
inhibit display (C10) and language control (C12 to 14) bits
are dealt with automatically by the display section,
described below.
The update (C8) bit has no effect on the hardware. The
remaining 32 bytes of the page header are parity checked
and written into columns 8 to 39 of row 0. Bytes which pass
the parity check have the MSB set to 0 and are written into
the page memory. Bytes with parity errors are not written
into the memory.
In the first edition of ETS 300 706, the @ symbol is

available for display at level 1 only when:
1). the page uses the Latin G0 set and selects the English
national option set,
or
2). when the Hebrew G0 character set is selected.
The device will also display @ in response to the packet 26
triplet containing NULL accent (mode value 10000) and
character 4/0 providing the Latin G0 set is currently
selected.
The * character is available as a level 1 character in all of
the defined G0 character sets and it is very unlikely that a
* character would be invoked at level 1.5 via the triplet
NULL accent, character 2/A. Therefore, the second edition
Inventory Page
If the TXT0.INV on bit is 1, memory block 8 is used as an
inventory page. The inventory page consists of two tables,
- the Transmitted Page Table (TPT) and the subtitle page
table (SPT).
In each table, every possible combination of the page tens
and units digit, 00 to FFh, is represented by a byte. Each
bit of these bytes corresponds to a magazine number so
each page number, from 100 to 8FF, is represented by a
bit in the table.The bit for a particular page in the TPT is set
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of ETS 300 706 defines that the @ symbol should be
displayed in response to the NULL accent, character 2/A
triplet for all G0 character set.
The IC will display the * character while providing * is sent
as the fallback character on the level 1 page, and depend
on the software (DDS) to implement the first edition of ETS
300 706 which should also display *, or the second edition
of ETS 300 706 which should display the @ symbol.
version of the packet are the same so they are stored

whenever either version of the packet is acquired.
In 525 line text each packet 26 only contains ten 24/18
Hamming encoded data triplets, rather than the 13 found
in 625 line text. The tabulation bit is used as an extra bit
(the MSB) of the designation code, allowing 32 packet 26s
to be transmitted for each page. The last byte of each
packet 26 is ignored.
FASTEXT DETECTION
When a packet 27, designation code 0 is detected,
whether or not it is acquired, the TXT13. FASTEXT bit is
set. If the device is receiving 525 line teletext, a packet
X/0/27/0 is required to set the flag. The flag can be reset
by writing a 0 into the SFR bit.
525 WST
The 525 line format is similar to the 625 line format but the
data rate is lower and there are less data bytes per packet
(32 rather than 40). There are still 40 characters per
display row so extra packets are sent each of which
contains the last 8 characters for four rows. These packets
can be identified by looking at the tabulation bit (T), which
replaces one of the magazine bits in 525 line teletext.
When an ordinary packet with T = 1 is received, the
decoder puts the data into the four rows starting with that
corresponding to the packet number, but with the 2 LSBs
set to 0. For example, a packet 9 with T = 1 (packet X/1/9)
contains data for rows 8, 9, 10 and 11. The error checking
carried out on data from packets with T = 1 depends on the
setting of the TXT1. 8 BIT bit and the error checking control
bits in the page request data and is the same as that
applied to the data written into the same memory location
in the 625 line format.
The rolling time display (the last 8 characters in row 0) is
taken from any packets X/1/1, 2 or 3 received. In parallel
magazine mode only packets in the correct magazine are
used for rolling time. Packet number X/1/0 is ignored.
The tabulation bit is also used with extension packets. The
first 8 data bytes of packet X/1/24 are used to extend the
Fastext prompt row to 40 characters. These characters are
written into whichever part of the memory the packet 24 is
being written into (determined by the X24 Posn bit).
Packets X/0/27/0 contain 5 Fastext page links and the link
control byte and are captured, Hamming checked and
stored by in the same way as are packets X/27/0 in 625
line text. Packets X/1/27/0 are not captured.
Because there are only 2 magazine bits in 525 line text,
packets with the magazine bits all set to 0 are referred to
as being in magazine 4. Therefore, the broadcast service
data packet is packet 4/30, rather than packet 8/30. As in
625 line text, the first 20 bytes of packet 4/30 contain
encoded data which is decoded in the same way as that in
packet 8/30. The last 12 bytes of the packet contains half
of the parity encoded status message. Packet 4/0/30
contains the first half of the message and packet 4/1/30
contains the second half. The last 4 bytes of the message
are not written into memory. The first 20 bytes of the each
2003 Nov 11
UOCIII series
BROADCAST SERVICE DATA DETECTION

When a packet 8/30 is detected, or a packet 4/30 when the
device is receiving a 525 line transmission, the TXT13.
Packet 8/30. The flag can be reset by writing a 0 into the
SFR bit. The data of packet 8/30 is written to the block 9.
VPS ACQUISITION
When the TXT0. VPS ON bit is set, any VPS data present
on line 16, field 0 of the CVBS signal at the input of the
teletext decoder is error checked and stored in row 25,
block 9 of the basic page memory. The device
automatically detects whether teletext or VPS is being
transmitted on this line and decodes the data
appropriately.
column
0
Teletext page
row 25 header data
9 10 11
VPS
byte 11
12 13 14
15 16 17 18 19 20 21
VPS
VPS
byte 12 byte 13
VPS
VPS
byte 14 byte 15
VPS
byte 4
22 23
VPS
byte 5
Fig.20 VPS Data Storage

Each VPS byte in the memory consists of 4 bi-phase
decoded data bits (bits 0-3), a bi-phase error flag (bit 4)
and three 0s (bits 5-7). The TXT13. VPS Received bit is
set by the hardware whenever VPS data is acquired. The
flag can be reset by writing a 0 into the SFR bit.
625 WSS ACQUISITION

The Wide Screen Signalling data transmitted on line 23
gives information on the aspect ratio and display position
of the transmitted picture, the position of subtitles and on
the camera/film mode. Some additional bits are reserved
for future use. A total of 14 data bits are transmitted. All of
the available data bits transmitted by the Wide Screen
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UOCIII series
Signalling signal are captured and stored in SFRs WSS1,

WSS2 and WSS3. The bits are stored as groups of related
bits and an error flag is provided for each group to indicate
when a transmission error has been detected in one or
more of the bits in the group. Wide screen signalling data
is only acquired when the TXT8.WSS ON bit is set. The
TXT8.WSS RECEIVED bit is set by the hardware
whenever wide screen signalling data is acquired. The flag
can be reset by writing a 0 into the SFR bit.
RDS_Subsystem
The RDS_SUBSYSTEM contains Serialiser, RDS
demodulator, and RDS/RBDS decoder.
CLOSED CAPTION ACQUISITION

The US Closed Caption data is transmitted on line 21 (525
line timings) and is used for Captioning information, Text
information and Extended Data Services. Closed Caption
data is only acquired when TXT21.CC ON bit is set.
Two bytes of data are stored per field in SFRs, the first bye
is stored in CCDAT1 and the second byte is stored in
CCDAT2. The value in the CCDAT registers are reset to
00h at the start of the Closed Caption line defined by
CCLIN.CS<4:0>. At the end of the Closed Caption line an
interrupt is generated if IE.ECC is active.
The processing of the Closed Caption data to convert into
a displayable format is performed by Software.
DEMODULATOR
The RDS demodulator regenerates the raw RDS bit
stream (bit rate=1187.5 Hz) from the modulated RDS
signal in two steps. The first step is the demodulation of the
Double-Side-Band Suppressed-Carrier signal around 57
kHz into a baseband signal, by carrier extraction and
down-mixing. The second step is the BPSK demodulation
of the biphase coded baseband signal, by clock extraction
and correlation. The raw RDS bit stream data is provided
for further processing by the RDS/RBDS decoder block.
Serialiser
The RDS Serialiser converts the 304kHz 10-bits parallel
data to 9.728MHz 32-bits serial data (10-bits data, 22-bits
dummy). The output bitstream data of the Serialiser will
then feed to Demodulator.
DECODER
The RDS/RBDS decoder handles the complete data
processing and decoding of the continuously received
serial RDS/RBDS demodulator output data stream.
Different data processing modes are software controllable
via SFRs.
The RDS/RBDS decoder provides the RDS/RBDS block
detection, error detection, error correction,
synchronization, flywheel for synchronization hold, and
programmable block data output. New processed
RDS/RBDS block information is signalled (interrupt) to the
micro-controller as new data available by use of the
DAVN output. The block data and the corresponding
status information will be output to the RDS SFRs and can
be read out by micro-controller via SFR Interface.
The processing of the RDS/RBDS data to convert into a
displayable format is performed by Software.
RDS/RBDS
The Radio Data System (RDS)/ Radio Broadcast Data
System (RBDS) informations are carried in FM radio
channels. The FM radio channels are located in the range
from 87.5MHz to 108MHz. Once a radio channel is tuned,
the MPX signal is processed by this block.
RDS/RBDS Features
Demodulation of the European Radio Data System
(RDS) or the USA Radio Broadcast Data System
(RBDS) signal
RDS and RBDS block detection
Error detection and correction
Fast block synchronization
RDS/RBDS Block Detection

The RDS/RBDS block detection is always active.
For a received sequence of 26 data bits a valid block and
corresponding offset are identified via syndrome
calculation.
During synchronization search, the syndrome is calculated
with every new received data bit (bit-by-bit) for a received
26-bit sequence. If the decoder is synchronized, syndrome
calculation is activated only after 26 data bits for each new
block received.
Under RBDS reception situation, besides the RDS block
sequences with (A, B, C/C, D) offset also block sequences
of 4 blocks with offset E may be received. If the decoder
detects an E-block, the block is marked in the block
Synchronization control (flywheel)

Mode control for RDS/RBDS processing
Different RDS/RBDS block information output modes
Analogue to Digital Converter
The RDS input is passed to a single ended to differential
converter (S/D-conv+L-shift). The analogue output of
S/D-conv+L-shift is converted into a digital representation
by a Video ADC with a sampling rate of 304kHz.
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carried out until the first valid and error free block has been
received. Then the next expected block calculated and
syndrome calculation is done after the next 26 bits have
been received. The block-span in which the second valid
and expected block can be received is selectable via
previously setting of the Max_Bad_Blocks_Gain
(MBBG<4:0>). If the second received block is an invalid
block, then the bad_blocks_counter is incremented and
again the new next expected block is calculated. If the
bad_blocks_counter value reaches the pre-selected
Max_Bad_Blocks_Gain, then the bit-by-bit search for the
first block is started again.
If synchronization is found, the synchronization status flag
(SYNC) is set and available via SFR read. The
synchronization is held until the bad_blocks_counter value
reaches the pre-selected Max_Bad_Blocks_Lose value
(used for synchronization hold) or an external restart of
synchronization is performed (NWSY=1; or power-on
reset).
identification number (BlNr<2:0>) and is stored in the SFR

LBIN<2:0>. In RBDS processing mode the block is
signalled as valid E-block and in RDS processing mode,
where only RDS blocks are expected, signalled as invalid
E-block.
This information can be used by the micro-controller to
detect E-block sequences and identify RDS or RBDS
transmitter stations.
Error Detection and Correction

The RDS/RBDS error detection and correction recognizes
and corrects potential transmission errors within a
received block via parity-check in consideration of the
offset word of the expected block. Burst errors with a
maximum length of 5 bits are corrected with this method.
After synchronization has been found the error correction
is always active depending on the pre-selected error
correction mode of synchronization (mode SYNCA ...
SYNCD), but cannot be carried out in every reception
situation.
During synchronization search, the error correction is
disable for detection of the first block and is enable for
processing of the second block depending on the
pre-selected error correction mode for synchronization
(mode SYNCA ... SYNCD).
The processed block data and the status of error
correction are stored in the SFRs (Status Registers).
EXB1
EXB0
Description
no errors detected
burst error of max. 2 bits corrected
burst error of max. 5 bits corrected
uncorrectable block
FLYWHEEL FOR SYNCHRONIZATION HOLD

For a fast detection of loss of synchronization an internal
flywheel shall be implemented. Therefore one counter
(bad_blocks_counter) checks the number of uncorrectable
blocks and a second counter (good_blocks_counter)
checks the number of error free or correctable blocks.
Error blocks increment the bad_blocks_counter and valid
blocks increment the good_blocks_counter. If the counter
value of the good_blocks_counter reaches the
pre-selected Max_Good_Blocks_Lose value (MGBL<5:0>
the good_blocks_counter and bad_blocks_counter are
reset to zero. But if the bad_blocks_counter reaches the
pre-selected Max_Bad_Blocks_Lose value (MBBL<5:0>)
then new synchronization search (bit-by-bit) is started
(SYNC=0) and both counters are reset to zero.
The flywheel function is only activated if the decoder is
synchronized. The synchronization is held until the
bad_blocks_counter reaches the pre-selected
Max_Bad_Blocks_Lose value (loss of synchronization) or
an external forced start of new synchronization search
(NWSY=1) is performed. The maximum values for the
flywheel counters are both adjustable via SFR in a range
of 0 to 63.
Table 17 RDS processed error correction

Processed blocks are characterized as uncorrectable
under the following conditions:
During synchronization search, if the burst error (for the
second block) is higher than allowed by the pre-selected
correction mode SYNCA ... SYNCD.
After synchronization has been found, if the burst error
exceeds the correctable max. 5 bit burst error or if errors
are detected but error correction is not possible.
Bit Slip Correction

During poor reception situation phase shifts of one bit to
the left or right (+/- 1 bit slip) between the RDS/RBDS clock
and data may occur, depending on the lock conditions of
the demodulator clock regeneration.
If the decoder is synchronized and detects a bit slip
(BSLP=1), the synchronization is corrected +1, 0 or -1 bit
via block detection on the respectively shifted expected
new block.
Synchronization
The decoder is synchronized if two valid blocks in a valid
sequence are detected by the block detection.
The search for the first block is done by a bit-by-bit
syndrome calculation, starting after the first 26 bits have
been received. This bit-by-bit syndrome calculation is
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Data Processing Control
The decoder should provide different operating modes
selectable by NWSY, SYM0, SYM1, DAC0 and DAC1
inputs via the SFRs. The data processing control performs
the pre-selected operating modes and controls the
requested output of the RDS/RBDS information.
RBDS Processing Mode

The decoder should be suitable for receivers intended for
the European (RDS) as well as for the USA (RBDS)
standard. If RBDS mode is selected (RBDS=1) via the
SFR, the block detection and the error detection and
correction are adjusted to RBDS data processing. That is,
also E blocks are treated as valid blocks. If RBDS is reset
to zero (RDS_CTRL.RBDS=0), RDS mode is selected.
Restart of Synchronization Mode

The restart synchronization (NWSY) control mode
immediately terminates the actual synchronization and
restarts a new synchronization search procedure
(NWSY=1). The NWSY flag is automatically reset after the
restart of synchronization by decoder (NWSYRe pulse).
This mode is required for a fast new synchronization on the
RDS/RBDS data from a new transmitter station if the
tuning frequency is changed by the radio set.
Restart of synchronization search is furthermore
automatically carried out if the internal flywheel signals a
loss of synchronization.
Data Available Control Modes

The decoder provides three different RDS/RBDS data
output processing modes plus one decoder bypass mode
selectable via the data available control mode inputs
DAC0 and DAC1.
Error Correction Control Mode For Synchronization

For error correction and identification of valid blocks during
synchronization search as well as synchronization hold,
four different modes are selectable (SYM<1>, SYM<0>).
mode SYNCA (SYM<1>=0, SYM<0>=0): no error
correction; blocks detected as correctable are treated as
invalid blocks internal bad_blocks_counter still
incremented even if correctable errors detected. If
synchronized only error free blocks increment the
good_blocks_counter. All blocks except error free
blocks increment the bad_blocks_counter.
mode SYNCB (SYM<1>=0, SYM<0>=1): error
correction of burst error max. 2 bits; blocks corrected are
treated as valid blocks, all other errors detected are
treated as invalid blocks. If synchronized error free and
correctable max. 2 bit error increment the
good_blocks_counter.
mode DAVA:
(DAC1=0,
DAC0=0)
Standard output mode: If the decoder is

synchronized and a new block is received (every
26 bits), the actual RDS/RBDS information of the
last two blocks is available with every new
received block (approx. every 21.9ms).
mode DAVB:
(DAC1=0,
DAC0=1)
Fast PI search mode: During synchronization

search and if a new A or C block is received, the
actual RDS/RBDS information of this or the last
two A or C blocks respectively is available with
every new received A or C block. If the decoder
is synchronized, the "standard output mode" is
active.
mode DAVC:
(DAC1=1,
DAC0=0)
Reduced data request output mode: If the

decoder is synchronized and two new blocks are
received (every 52 bits), the actual RDS/RBDS
information of the last two blocks is available with
every two new received blocks (approx. every
43.8ms).
mode DAVD:
(DAC1=1,
DAC0=1)
Decoder bypassed mode: If this mode is selected

then the OutMux output of the decoder is reset to
low (OutMux=0). Then the internal row buffer
output is active and the decoder is bypassed.
This mode is not available in normal application
mode.
Table 18 DAV Modes

The decoder provides:- data output of the
block-identification of the last and previously processed
blocks, the RDS/RBDS information words and error
detection/correction status of the last two blocks as well as
general decoder status information.
In addition the decoder output is controlled indirectly by the
data request (SFR read) by micro-controller. The decoder
receives a data overflow (DOFL) signal controlled by the
SRF. This DOFL signal has to be set to high (DOFL=1) if
the decoder is synchronized and a new RDS/RBDS block
is received before the previously processed block was
completely transmitted via SFRs. After detection of data
overflow the SFRs are not updated (no DecWrE) until reset
of the data overflow flag (DOFL=0) by reading via the
SFRs or if NWSY=1 which results in start of new
synchronization search (SYNC=0).
mode SYNCC (SYM<1>=1, SYM<0>=0): error

correction of burst error max. 5 bits; blocks corrected are
treated as valid blocks, all other errors detected are
treated as invalid blocks. If synchronized error free and
correctable max. 5 bit error increment the
good_blocks_counter.
mode SYNCD (SYM<1>=1, SYM<0>=1): no error
correction; blocks detected as correctable are treated as
invalid always incremented even if correctable errors
detected. If synchronized error free blocks are
correctable max. 5 bit errors increment the
good_blocks_counter. Only uncorrectable blocks
increment the bad_blocks_counter.
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UOCIII series
Data Output of RDS/RBDS Information

The decoded RDS/RBDS block information and the
current decoder status should be available via the SFRs.
For synchronization of data request between
micro-controller and decoder the additional data available
output (DAVN) is used for the interrupt. For DAVN timing
information see next section.
If the decoder has processed new information for the
micro-controller the data available signal (DAVN) is
activated (low) under the following condition: During synchronization search in DAVB mode if a valid
A or C block has been detected. This mode can be used
for fast search tuning (detection and comparison of the
PI code contained in the A and C blocks.
If the decoder is synchronized and in DAVC mode two

new blocks have been processed.
During synchronization search in any DAV mode except

DAVD mode, if two blocks in the correct sequence have
been detected (synchronization criterion fulfilled).
DAVN Timing
The processed RDS/RBDS data are available for
micro-controller request for at least 20ms after the DAVN
signal was activated. The DAVN signal is always
automatically de-activated (high) after ~ 10ms.
If the decoder is synchronized and in any DAV mode

except DAVD mode loss of synchronization is detected
(flywheel loss of synchronization, resulting in restart of
synchronization search).
In any DAV mode except DAVD mode, if a reset caused
by power-on or voltage-drop is detected (PresN=0).
Remark: If the decoder is synchronized, the DAVN
signal is always activated after 21.9ms in DAVA or
DAVB mode and after 43.8ms in DAVC mode
independent of valid or invalid blocks are detected.
If the decoder is synchronized and in mode DAVA and

DAVB a new block has been processed. This mode is
the standard output mode, if the decoder is
synchronized.
The decoder ignores new processed RDS/RBDS blocks if

the DAVN signal is active (low).
Fig.21 DAVN LOW-time (decoder is synchronized)
RDS SFRs
SYMBOL
PARAMETER
Typical
UNIT
tDVL
data valid to DAVN LOW
2.0
us
tTDAV
data valid period
21.9
ms
tDV
data valid
21.9
ms
tDAVL
data available signal is LOW
10.1
ms
CONTROL REGISTER
The RDS has 4 input control registers to which can be
written by the micro-controller via the MOVX.
The RDS provides 3 different RDS/RBDS data output
processing modes plus one decoder module bypass mode
selectable via the control registers DAC<1:0>.
The NWSY control signal is to start new synchronization
process, if set to high. This bit of the control register is
Table 19 Data Available Signal (DAVN)
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demodulator module) clock pulses and has to be used

directly as RSTD register-flag set signal.
Last block identification number, LBIN<2:0> hold the block
number of the last processed RDS/RBDS data block. The
LBIN<2:0> are controlled by the output signals, BlNr<2:0>,
of decoder module. The LBIN<2:0> registers has to be
connected to the inputs of the register(PBlN<2:0>) which
holds the previously processed block number. So if
RCopyE is set to high while DecWrE is active a copy from
the last to the previously block number will be done.
Error status of last block, ELB<1:0>, these registers are
controlled by the output signals, EXB1 & EXB0. The
ELB<1:0> holds the error status of the last processed
RDS/RBDS data block. The output of these registers has
to be connected to the input of the register (EPB<1:0>)
which holds the previously processed error status. So, if
RCopyE is set to high while DecWrE is active a copy from
the last to the previously error status will be done.
Bad block counter registers, BBC<5:0>, represent the
actual bad_blocks_counter value.
Good block counter registers, GBC<5:1>, represent the
actual good_blocks_counter value.
reset to low with a positive NWSYRe output pulse

generated automatically by the decoder module.
The maximum invalid blocks allowed during
synchronization search (SYNC=0). If the first block needed
for synchronization has been found and the expected
second block (after 26 bits) is an invalid block, then the
decoder module internal_bad_blocks_counter is
incremented and the next expected block is calculated;
exception: if RBDS mode is selected and the first block is
block E, then the next expected block is always block A,
until synchronization is found or the maximum
bad_blocks_counter value is reached. If the decoder
module internal bad_blocks_counter reaches the value of
the MBBG<4:0>, then immediately start of new
synchronization search (bit-by-bit) is started to find a new
first block. The function of Max_Bad_Blocks_Gain is
disable if MAX_Bad_Blocks_Gain is set to zero. Only in
this case the 2 path synchronization search function is
activated.
For error correction and identification of valid blocks during
synchronization search as well as synchronization hold, 4
different modes are selectable (SYM<1>, SYM<0>).
MBBL<5:0> - Max_Bad_Blocks_Lose: maximum invalid
blocks allowed while synchronized (SYNC=1). If the
decoder module internal bad_blocks_counter reaches this
value, then immediately start of new synchronization
search (bit-by-bit) is started (SYNC=0) and the internal
bad_blocks_counter as well as the good_blocks_counter
itself are reset to zero.
MGBL<5:0> - Max_Good_Blocks_Lose: maximum valid
blocks required to clear the decoder module internal
bad_blocks_counter. Only activated while synchronized
(SYNC=1). If the decoder module internal
good_blocks_counter reaches this value, then
immediately the bad_blocks_counter and the
good_blocks_counter itself are reset to zero.
RBDS - If this bit set to high, then allow processing of
RBDS E block. Otherwise, if set to low, it will enter RDS
mode.
RDS/RBDS DECODED DATA REGISTER

The decoder module has 4 output registers to put the
processed/decoded RDS/RBDS block data. These
registers can be read by the micro-controller after
detection of the RDS interrupt (DAVN=low).
Last processed data, LDAT<15:0>, hold the parallel output
of the 16 bit from Data<15:0> decoder module output bus,
which represents the information word of the last
processed RDS/RBDS data block. The output of this
registers has to be connected to the input of the register
PDAT<15:0> which holds the previously processed block
data. So if RCopyE is set to high while DecWrE is active a
copy from the last to the previously block will be done.
DISPLAY
The display section is based on the requirements for a
Level 1.5 WST Teletext and US Closed Caption. There are
some enhancements for use with locally generated
On-Screen Displays.
The display section reads the contents of the Display
memory and interprets the control/character codes. Using
this information and other global settings, the display
produces the required RGB signals and Video/Data (Fast
Blanking) signal for the TV signal processing.
The display is synchronised to the TV signal processing by
way of Horizontal and Vertical sync signals generated
within UOCIII. From these signals all display timings are
derived.
STATUS REGISTER
The RDS module has one status register.
The output signal, SYNC, from decoder module indicates
the synchronization found. It is set high, if synchronization
is found; otherwise reset to zero. The SYNC output signal
directly effects the status register.
RSTD is set to high, if a reset occurred, caused by
power-on reset or voltage drop. RSTD register is set by
SRSTD signal output from decoder module. The RSTD
status flag has to be cleared automatically after the status
register was read by micro-controller. SRSTD is set to high
(after power-on reset) for the first received 26 RDCL(from
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device.The display is configured as a fixed 25 rows

with 40 characters per row.
Display Features
Teletext and Enhanced OSD modes
Level 1.5 WST features
CC:- This is the display configured as the US Closed

Caption mode with the same functionality as the
PC83C771 device. The display is configured as a
maximum of 16 rows with a maximum of 48
characters per row.
US Closed Caption Features

50Hz/60Hz display timing modes
Two page operation for 16:9 screens
Serial and Parallel Display Attributes
OSD:-This is the display configured as either TXT or CC

mode but without the restriction of display size or
character matrix.
Single/Double/Quadruple Width and Height for

characters
Smoothing capability of both Double Size, Double Width
& Double Height characters
There is an option of 10/13/16/18 lines per display row for

CC style OSD mode, the characters used in these rows
can be either 12x13, 12x16, 12X18, 16X16, 16x18.
In CC style OSD mode the number of rows and columns
available in limited by the maximum row value of 16, the
maximum column value of 48 and the maximum number of
character location of 624. This gives a full occupied display
of 16 rows by 39 columns for maximum rows, or 13 rows
by 48 columns for maximum columns.
In TXT style OSD mode the maximum number of rows is
25 and the maximum number of columns is 40, both of
these limits can be achieved simultaneously.
Note: Not all combinations of lines per row and maximum
display rows give a sensible OSD display, since there is
limited number of TV scan lines available.
Special Function Register, TXT21 and memory mapped
register are used to control the mode selection.
Scrolling of display region

Variable flash rate controlled by software
Globally selectable scan lines per row 9/10/13/16/18.
Globally selectable character matrix (HxV) 12x9/10,
12x13, 12x16, 16x16 and 16x18
Italics, Underline and Overline
Soft Colours using CLUT with 4096 colour palette.
Fringing (Shadow) selectable from N-S-E-W direction.
Fringe colour selectable
Contrast reduction of defined area is available in both
TXT and CC mode
Double window
Cursor
The following is a list of features available in each mode.

Each setting can either be a serial or parallel attribute, and
some have a global effect on the display.
Special Graphics characters with two planes, allowing

four colours per character
64 Software re-definable DRCs (Dynamically
Re-definable Characters), when its used as 4 colour
mode for each pixel, the number of DRCs will be 32
4 WST Character sets(G0/G2) in single device (e.g.
Latin, Cyrillic, Greek, Arabic)
G1 Mosaic graphics, Limited G3 Line drawing
characters
WST Character sets and Closed Caption Character set
in single device
Panorama Mode, display 4:3 signals on 16:9 screen
SCAVEM for Text
Display Modes
The display section has three distinct modes with different
features available in each. The two modes are:
TXT:- This is the display configured as the WST mode
with additional serial and global attributes to enable
the same functionality as the SAA5497 (ETT)
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UOCIII series
Feature
TXT
CC
Flash
serial
serial
Boxes
TXT/OSD (Serial)
serial
Horizontal Size
x1/x2/x4 (serial)
x1/x2 (serial)
Vertical Size
x1/x2 (serial)
x4 (global)
x1/x2 (serial)
Italic
N/A
serial
Foreground
colours
8 (serial)
8+8 (parallel)
Background
colours
8 (serial)
16 (serial)
Soft Colours
(CLUT)
16 from 4096
16 from 4096
Table 20 Display Features
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Feature
TXT
CC
Underline
N/A
serial
Overline
N/A
serial
Fringe
N+S+E+W
N+S+E+W
Fringe Colour
16 (Global)
16 (Serial)
Smoothing
YES (Global)
YES (Global)
Fast Blanking
Polarity
YES
YES
Screen Colour
16 (Global)
16 (Global)
DRCS
64 (Global)
64 (Global)
Character Matrix
(HxV)
12x9/10/13/16
12x9/10/13/16,
16x16/18
No. of Rows
25
16
No. of Columns
40
48
No of Characters
displayable
1000
624
Cursor
YES
YES
Special Graphics
(2 planes per
character)
32
32
Scroll
NO
YES
mode the background colour is displayed. Character

locations where boxes are not set show video/screen
colour (depending on the setting in the display control
register. REG0: Display Control) in stead of the
background colour.
TXT: Two types of boxes exist the Teletext box and the
OSD box. The Teletext box is activated by the start box
control character (0Bh), Two start box characters are
required begin a Teletext box, with box starting between
the 2 characters. The box ends at the end of the line or
after a end box control character.
TXT mode can also use OSD boxes, they are started using
size implying OSD control characters
(BCh/BDh/BEh/BFh). The box starts after the control
character (set after) and ends either at the end of the row
or at the next size implying OSD character (set at). The
attributes flash, teletext box, conceal, separate graphics,
twist and hold graphics are all reset at the start of an OSD
box, as they are at the start of the row. OSD Boxes are only
valid in TV mode which is defined by TXT5=03h and
TXT6=03h.
SIZE
The size of the characters can be modified in both the
horizontal and vertical directions.
CC: Two sizes are available in both the horizontal and
vertical directions. The sizes available are normal (x1),
double (x2) height/width and any combination of these.
The attribute setting is always valid for the whole row.
Mixing of sizes within a row is not possible.
TXT: Three horizontal sizes are available
normal(x1),double(x2),quadruple(x4). The control
characters normal size (0Ch/BCh) enables normal size,
the double width or double size (0Eh/BEh/0Fh/BFh)
enables double width characters. Any two consecutive
combination of double width or double size
(0Eh/BEh/0Fh/BFh) activates quadruple width characters,
provided quadruple width characters are enabled by
TXT4.Quad Width Enable.
Three vertical sizes are available normal(x1), double(x2),
quadruple(x4). The control characters normal size
(0Ch/BCh) enable normal size, the double height or
double size (0Dh/BDh/0Fh/BFh) enable double height
characters. Quadruple height character are achieved by
using double height characters and setting the global
attributes TXT7.Double Height (expand) and
TXT7.Bottom/Top.
If double height characters are used in teletext mode,
single height characters in the lower row of the double
height character are automatically disabled.
Table 20 Display Features

Display Feature Descriptions
FLASH
Flashing causes the foreground colour pixel to be
displayed as the background pixels.The flash frequency is
controlled by software setting and resetting display
register REG0: Status at the appropriate interval.
CC: This attribute is valid from the time set (see Table 27)
until the end of the row or until otherwise modified.
TXT: This attribute is set by the control character flash
(08h) and remains valid until the end of the row or until
reset by the control character steady (09h).
BOXES
CC: This attribute is valid from the time set until end of row
or otherwise modified if set with Serial Mode 0. If set with
Serial Mode 1, then it is set from the next character
onwards.
In CC text mode the background colour is displayed
regardless of the setting of the box attribute bit. Boxes take
affect only during mixed mode, where boxes are set in this
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writing data to a RAM that resides in the MOVX address

space of the 80C51.
ITALIC
CC: This attribute is valid from the time set until the end of
the row or otherwise modified. The attribute causes the
character foreground pixels to be offset horizontally by 1
pixel per 4 scan lines (interlaced mode). The base is the
bottom left character matrix pixel. The pattern of the
character is indented as shown in Fig.22
0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10
0
1 12x16 character matrix
2
3
4
5
6
7
8
9
10
11
12
13
14
15
12x10 character matrix
12x13 character matrix
UOCIII series
Indented by 7/6/4
RED3-0
b11. . .b4
GRN3-0
b7. . .b4
BLU3-0
b3. . .b0
0000
0000
0000
0000
0000
1111
...
...
...
...
1111
1111
0000
14
1111
1111
1111
15
Indented by 6/5/3
Indented by 5/4/2
Indented by 4/3/1
Table 21 CLUT Colour values
Indented by 3/2/0
Indented by 2/1
Indented by 1/0
Indented by 0
Field 1
Field 2
Italy Shift
Indented
by 10
Indented
by 9
Indented
by 8
Indented
by 7
Indented
by 6
Indented
by 5
Indented
by 4
Indented
by 3
Indented
by 2
Indented
by 1
Indented
by 0
Scan Line
-2
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Pixels 0
Character Size
4
2
8
6
4 6
10 12 14
16 Wide x 18 High
Fig.22 Italic Characters

TXT: The Italic attribute is not available.
COLOURS
CLUT (Colour Look Up Table)

A CLUT (Colour Look Up Table) with 16 colour entries is
provided. The colours are programmable out of a palette
of 4096(4 bits per R, G and B). The CLUT is defined by
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Colour
entry
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The default value of the CLUT when entering TXT mode is
given in the table below, this gives the required full
intensity teletext colours.
Full Intensity
Equivalent
(Foreground)
CLUT
Address
UOCIII series
Serial Mode 1, then the colour is set from the next
character onwards.
The background colour can be chosen from all 16 CLUT
entries.
TXT: The control character New background (1Dh) is
used to change the background colour to the current
foreground colour. The selection is immediate (Set at)
and remains valid until the end of the row or until otherwise
modified.
The TEXT background control characters map to the
CLUT entries as shown below:
Full Intensity
Equivalent
(Background)
CLUT
Address
Default<11:0>
000000000000
Black
000000000000
Black
111100000000
Red
111100000000
Red
000011110000
Green
000011110000
Green
111111110000
Yellow
111111110000
Yellow
Control Code
Defined Colour
CLUT Entry
000000001111
Blue
000000001111
Blue
00h+1Dh
Black
111100001111
Magenta
111100001111
Magenta
01h+1Dh
Red
000011111111
Cyan
000011111111
Cyan
02h+1Dh
Green
10
111111111111
White
111111111111
White
03h+1Dh
Yellow
11
04h+1Dh
Blue
12
05h+1Dh
Magenta
13
06h+1Dh
Cyan
14
07h+1Dh
White
15
Default<11:0>
Table 22TXT Default CLUT map
Foreground Colour
CC: The foreground colour can be chosen from 8 colours
on a character by character basis. Two sets of 8 colours
are provided. A serial attribute switches between the
banks (see Table 27 Serial Mode 1, bit 7). The colours are
the CLUT entries 0 to 7 or 8 to 15.
TXT: The foreground colour is selected via a control
character. The colour control characters takes effect at the
start of the next character (Set-After) and remain valid
until the end of the row, or until modified by a control
character. Only 8 foreground colours are available.
The TEXT foreground control characters map to the CLUT
entries as shown below:
Control Code
Defined Colour
CLUT Entry
00h
Black
01h
Red
02h
Green
03h
Yellow
04h
Blue
05h
Magenta
06h
Cyan
07h
White
Table 24 Background CLUT mapping

BACKGROUND DURATION
The attribute when set takes effect from the current
position until to the end of the text display defined in
REG4:Text Area End.
CC: The background duration attribute (see Table 27,
Serial Mode 1, bit 8) in combination with the End Of Row
attribute (see Table 27, Serial Mode 1, bit 9) forces the
background colour to be display on the row until the end of
the text area is reached.
TXT: This attribute is not available.
UNDERLINE
The underline attribute causes the characters to have the
bottom scan line of the character cell forced to foreground
colour, including spaces. If background duration is set,
then underline is set until the end of the text area.
CC: The underline attribute (see Table 27, Serial Mode
0/1, bit 4) is valid from the time set until end of row or
otherwise modified.
Table 23 Foreground CLUT mapping
OVERLINE
The overline attribute causes the characters to have the
top scan line of the character cell forced to foreground
colour, including spaces. If background duration is set,
then overline is set until the end of the text area.
Background Colour
CC: This attribute is valid from the time set until end of row
or otherwise modified if set with Serial Mode 0. If set with
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UOCIII series
defined by TXT10.C<5:0>. The position of the cursor can
be fixed using TXT9.CURSOR FREEZE.
CC: The valid range for row is 0 to 15. The valid range for
column is 0 to 47. The cursor remains rectangular at all
times, its shape is not affected by italic attribute, therefore
it is not advised to use the cursor with italic characters.
TXT: The valid range for row positioning is 0 to 24.The
valid range for column is 0 to 39.
CC: The overline attribute (see Table 27, Serial Mode 0/1,
bit 5) is valid from the time set until end of row or otherwise
modified. Overlining of Italic characters is not possible.
END OF ROW
CC: The number of characters in a row is flexible and can
determined by the end of row attribute (see Table 27,
Serial Mode 1, bit 9). However the maximum number of
character positions displayed is determined by the setting
of the REG2:Text Position Horizontal and REG4:Text Area
End.
NOTE: When using the end of row attribute the next
character location after the attribute should always be
occupied by a space.
TXT: This attribute is not available, Row length is fixed at
40 characters.
ABCDEF
Fig.24 Cursor Display
SPECIAL GRAPHICS CHARACTERS
-Normal Special Graphics character
Mode(TXT20.Extended special graphics = 0)
CC/TXT: Several special characters are provided for
improved OSD special effects. These characters provide a
choice of 4 colours within a character cell. Addressing is
therefore done using only the even character addresses.
The total number of special graphics characters is limited
to max. 32 when Extended Special Graphics is not
enabled. They are stored in the character codes 8Xh, 9Xh
of the character table (32 ROM characters), or in the DRCs
which overlay character codes 8Xh, 9Xh, AXh and CXh (if
Extended DRC is enabled). Each special graphics
character uses two consecutive normal characters. The
pixel planes are stored in adjacent characters, always
starting with an even character. Special graphics
characters are activated when
TXT20/TXT29.OSD_PLANE = 1.
FRINGING
A fringe (shadow) can be defined around characters. The
fringe direction is individually selectable in any of the
North, South, East and West direction using
REG3:Fringing Control. The colour of the fringe can also
be defined as one of the entries in the CLUT, again using
REG3:Fringing Control.
CC: The fringe attribute (see Table 27, Serial Mode 0, bit
9) is valid from the time set until the end of the row or
otherwise modified.
TXT: The display of fringing in TXT mode is controlled by
the TXT4.SHADOW bit. When set all the alphanumeric
characters being displayed are shadowed, graphics
characters are not shadowed.
-Extended Special Graphics character

Mode(TXT20.Extended special graphics = 1)
CC:- When "TXT20.Extended special graphics" is
enabled, all characters from the ROM can be used as
special graphics characters in this mode. Each special
graphics character uses two consecutive characters from
the normal Character Set. Closed Caption character code
bit-14 enables display of special graphics on a character
by character basis.
Fig.23 South and Southwest Fringing
note: Special Graphics capability extended to any

character only in Closed_Caption Mode
CURSOR
The cursor operates by reversing the background and
foreground colours in the character position pointed to by
the active cursor position. The cursor is enabled using
TXT7.CURSOR ON. When active, the row the cursor
appears on is defined by TXT9.R<4:0> and the column is
2003 Nov 11
Four-colour on-screen display characters can be created

in closed caption and teletext style sets, provided they are
either 12x13 or 16x16 or16x18 characters. Four-colour
characters are generated by overlaying two consecutive
78
CONFIDENTIAL

two-colour characters. For example see following figure.
The two characters on the left could overlap to produce the
four-colour character on the right. For the character
definition the black would represent a 1 and the white
would represent a 0. Four-colour characters can easily be
defined using the DDS tool. The character is defined on a
pixel-by-pixel basis, after checking four colours option.
UOCIII series
Height, Double Width and Double Size Characters are all
improved when smoothing is enabled.
Character and Attribute Coding
CC MODE
Character coding is split into character oriented attributes
(parallel) and character group coding (serial). The serial
attributes take effect either at the position of the attribute
(Set At), or at the following location (Set After) and remain
effective until either modified by a new serial attribute or
until the end of the row. A serial attribute is represented as
a space (the space character itself however is not used for
this purpose), the attributes that are still active, e.g.
overline and underline will be visible during the display of
the space. The default setting at the start of a row is:
1x size, flash and italics OFF
The colours here have been used for the example. Four
colours are achieved by using the foreground and the
background colours, for example CLUT entries 0 and 1,
and the default (for four-colour characters) CLUT entries 6
and 7. In your application software you will need to define
the CLUT Table entries to obtain the colours that you
require and the foreground and the background colours.
Plane 1
Plane 0
Colour
Colour Allocation
Blue
Background Colour
Display mode = superimpose
White
Foreground Colour
fringing OFF
Red
CLUT Entry 6 or 14 depending on

the set bank
Green
CLUT Entry 7 or 15 depending on

the set bank
overline and underline OFF
background colour duration = 0

end of row = 0
The coding is done in 15 bit words. The codes are stored
sequentially in the display memory. A maximum of 768
character positions can be defined for a single display.
Table 25 Special Character Colour allocation

PARALLEL CHARACTER CODING
.
Background Colour
set at (Mode 0)
Serial Attribute
Background Colour
set after (Mode 1)
VOLUME
Bits
Description
0-7
8 bit character code
8-10
3 bits for 8 foreground colours
11
Mode bit:
0 = Parallel code
12-13
Character Select Selection:

00 = Character Set 0
Foreground Colour
Background Colour
Normal Character
Foreground Colour 7
Foreground Colour 6
Special Character
14
Character Definition:
0 = Single Plane Character
Fig.25 Special Character Example
1 = Two Plane Character (four colour)
Table 26 Parallel Character Coding
The example in Fig.25 can be done with 8 special graphics

characters.
Smoothing
Smoothing is available in both TXT and CC modes and is
activated using MMR 87E4<5:4>. The clarity of Double
2003 Nov 11
79
CONFIDENTIAL

UOCIII series
SERIAL CHARACTER CODING
Bits
Description
Serial Mode 0
(set at)
Serial Mode 1
Char.Pos. 1 (set at)
Char.Pos. >1 (set after)
0-3
4 bits for 16 Background

colours
4 bits for 16 Background colours
4 bits for 16 Background colours
0 = Underline OFF
1 = Underline ON
Horizontal Size:
0 = normal
1 = x2
0 = Underline OFF
1 = Underline ON
0 = Overline OFF
1 = Overline ON
Vertical Size:
0 = normal
1 = x2
0 = Overline OFF
1 = Overline ON
Display mode:
0 = Superimpose
1 = Boxing
Display mode:
0 = Superimpose
1 = Boxing
Display mode:
0 = Superimpose
1 = Boxing
0 = Flash OFF
1 = Flash ON
Foreground colour switch

0 = Bank 0 (colours 0-7)
Foreground colour switch

0 = Italics OFF
1 = Italics ON
Background colour duration:

0 = stop BGC
1 = set BGC to end of row
Background colour duration

(set at):
0 = stop BGC
1 = set BGC to end of row
0 = Fringing OFF
1 = Fringing ON
End of Row
0 = Continue Row
1 = End Row
End of Row (set at):

0 = Continue Row
1 = End Row
10
Switch for Serial coding

mode 0 and 1:
Switch for Serial coding mode 0

and 1:
Switch for Serial coding mode 0

and 1:
0 = mode 0
1 = mode 1
1 = mode 1
Mode bit:
Mode bit:
Mode bit:
1 = Serial code
1 = Serial code
1 = Serial code
0 = Cont. Red. OFF

1 = Cont. Red. ON
0 = Cont. Red. OFF

1 = Cont. Red. ON
0 = Cont. Red. OFF

1 = Cont. Red. ON
11
12
Table 27 Serial Character Coding
Bits 12/13 of the parallel character coding are used to

select the character set on character by character basis. In
CC Mode only, bits 13 and 12 of character code can
Character ROM Selection in CC Mode
2003 Nov 11
80
CONFIDENTIAL

control the character set selection when TXT20<4> is set.
When TXT20<4> is reset to 0 the normal BS<1:0>
bits(TXT18<1:0>) control character set selection as for
Text mode.
attribute will behave in exactly the same fashion as the

background colour attribute.
The actual contrast reduction is carried out in the Video
Signal Processor die and is simply switched in and out by
the cont_red signal from TCG micro-controller. The effect
of contrast reduction is to reduce the brightness and
contrast of the video image behind the OSD. For this
reason, contrast reduction is only visible in mixed screen
mode with superimposed text.
In table 28 shows the character set selection. Although the

hardware allow to select from 4 character sets, due to the
DDS tool limitation the Set 0 is only for teletext.
CC Mode
Char code<13:12>
character
Set
Example
Language
00
Set 0
Latin
01
Set 1
Greek
10
Set 2
Cyrillic
11
Set 3
Arabic
UOCIII series
TXT MODE
Character coding is in a serial format, with only one
attributes being changed at any single location. The serial
attributes take effect either at the position of the attribute
(Set At), or at the following location (Set After). The
attribute remains effective until either modified by new
serial attributes or until the end of the row.The default
settings at the start of a row is:
foreground colour white (CLUT Address 7)
background colour black (CLUT Address 8)
Horizontal size x1, Vertical size x1 (normal size)
Table 28 Character Set Selection
Alphanumeric ON
Serial mode 0
Serial mode 0 means that these attributes are valid from
the time set until the end of the row or until otherwise
modified. This differs from serial mode 1, where they are
valid from the next character onwards.
Contiguous Mosaic Graphics

Release Mosaics
Flash, Box, Conceal and Twist OFF
The attributes have individual codes which are defined in
the basic character table below:
Serial mode 1
Serial mode 1 means that these attributes are valid from
the character following the character code until the end of
the row or until otherwise modified. This differs from serial
mode 0 where they are also valid for the character code
itself. However, for the first character of each line, serial
mode 1 behaves differently.
When a serial mode 1 character code is set in position 1 of
a line, attributes are valid from the time set as in mode 0.
There is also a different set of attributes. All but two of
these attributes are the same as for the rest of the line. The
two different attributes are horizontal and vertical size, bits
4 and 5 respectively. These replace Underline and
Overline.
Contrast Reduction in CC Mode
When bit 12 of the serial character coding is set, this
generates a contrast reduction box. By setting TXT5 bits 5
and 4, contrast reduction can be enabled inside, or
outside, these boxes. When contrast reduction is active,
the cont_red output signal is set low. The cont_red signal
is always synchronized with VDS. With regard to
interaction with other features, the contrast reduction
2003 Nov 11
81
CONFIDENTIAL

b7
b6
b5
b4
bits
b3 b2 b1 b0
column
row
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
0
alpha
black
alpha
red
alpha
green
alpha
yellow
alpha
blue
alpha
magenta
alpha
cyan
alpha
white
graphics
black
graphics
red
graphics
green
graphics
yellow
graphics
blue
graphics
magenta
graphics
cyan
graphics
white
conceal
display
contiguous
graphics
separated
graphics
flash
steady
end
box
start
box
normal
height
double
height
double
width
double
size
0
1
UOCIII series
0 0 0
0
10
1
1
1 0
1
1 1
1
1
0
1
0
0 0
1
1
1
1
0
0
0 01
0
1
1 0 1
1
0
0
1 0
2 2a 3 3a 4 5 6 6a 7 7a 8 8a 9 9a A
Nat
Opt
Nat
Opt
Nat
Opt
Nat
Opt
twist
Nat
Opt
Nat
Opt
black
bkgnd
new
bkgnd
hold
graphics
release
graphics
Nat
Opt
Nat
Opt
Nat
Opt
Nat
Opt
Nat
Opt
Nat
Opt
Nat
Opt
O O
O O
S S
S S
D D
D D
O O
O O
S S
S S
D D
D D
O O
O O
S S
S S
D D
D D
O O
O O
S S
S S
D D
D D
O O
O O
S S
S S
D D
D D
O O
O O
S S
S S
D D
D D
O O
O O
S S
S S
D D
D D
O O
O O
S S
S S
D D
D D
O O
O O
S S
S S
D D
D D
O O
O O
S S
S S
D D
D D
O O
O O
S S
S S
D D
D D
O O
O O
S S
S S
D D
D D
O O
O O
S S
S S
D D
D D
O O
O O
S
S
S S
D
D
D D
O O
O O
S S
S S
D D
D D
O O
O O
S S
S S
D D
D D
B
bkgnd
black
bkgnd
red
bkgnd
green
bkgnd
yellow
bkgnd
blue
bkgnd
magenta
bkgnd
cyan
bkgnd
white
norm sz
OSD
dbl ht
OSD
dbl wd
OSD
dbl sz
OSD
Fig.26 TXT Basic Character Set (Pan-European)
2003 Nov 11
82
CONFIDENTIAL
E/W = 0
E/W = 1
11 11 11
0 1 1
1 0 1
11 11 11
0 1 1
1 0 1
D E F
D E F

Screen and Global Controls
A number of attributes are available that affect the whole
display region, and cannot be applied selectively to
regions of the display.
UOCIII series
Display Mode
TV SCAN LINES PER ROW

The number of TV scan lines per field used for each
display row can be defined, the value is independent of the
character size being used. The number of lines can be
either 10/13/16 per display row. The number of TV scan
lines per row is defined TXT21.DISP_LINES<1:0>.
A value of 9 lines per row can be achieved if the display is
forced into 525 line display mode by
TXT17.DISP_FORCE<1:0>, or if the device is in 10 line
mode and the automatic detection circuitry within display
finds 525 line display syncs.
CHARACTER MATRIX (HXV)
There are five different character matrices available, these
are 12x13, 12x16, 16x16 and 16x18. The selection is
made using TXT21.CHAR_SIZE<1:0> and is independent
of the number of display lines per row.
If the character matrix is less than the number of TV scan
lines per row then the matrix is padded with blank lines. If
the character matrix is greater than the number of TV scan
lines then the character is truncated.
MOD
<1 0>
Description
Video
0 0
Video mode disables all display

activities and sets the RGB to true
black and VDS to video.
Full Text
0 1
Full Text mode displays screen

colour at all locations not covered by
character foreground or background
colour. The box attribute has no
effect.
Mixed Screen
Colour
1 0
Mixed Screen mode displays screen

colour at all locations not covered by
character foreground, within boxed
areas or, background colour.
Mixed Video
1 1
Mixed Video mode displays video at

all locations not covered by
character foreground, within boxed
areas or, background colour.
Table 29 Display Modes

TXT: The display mode is controlled by the bits in the TXT5
and TXT6. There are 3 control functions - Text on,
Background on and Picture on. Separate sets of bits are
used inside and outside Teletext boxes so that different
display modes can be invoked. TXT6 is used if the
newsflash (C5) or subtitle (C6) bits in row 25 of the basic
page memory are set otherwise TXT5 is used. This allows
the software to set up the type of display required on
newsflash and subtitle pages (e.g. text inside boxes, TV
picture outside) this will be invoked without any further
software intervention when such a page is acquired.
Display Modes
CC: When attributes superimpose or when boxing (see
Table 27, Serial Mode 0/1, bit 6) is set, the resulting display
depends on the setting of the following screen control
mode bits in REG0:Display Control.
Picture On
Text On
Background
On
Text mode, black screen
Text mode, background always black
Text mode
Video mode
Mixed text and TV mode
Text mode, TV picture outside text area
Effect
Table 30 TXT Display Control Bits
2003 Nov 11
83
CONFIDENTIAL

Screen Colour
Screen colour is displayed from 10.5 us to 62.5 us after the
active edge of the HSync input and on TV lines 23 to 310
inclusive, for a 625 line display, and lines 17 to 260
inclusive for a 525 line display.
The screen colour is defined by REG0:Display Control and
points to a location in the CLUT table. The screen colour
covers the full video width. It is visible when the Full Text
or Mixed Screen Colour mode is set and no foreground or
background pixels are being displayed.
Display Map
The display map allows a flexible allocation of data in the
memory to individual rows.
Sixteen words are provided in the display memory for this
purpose. The lower 10 bits address the first word in the
memory where the row data starts. This value is an offset
in terms of 16-bit words from the start of Display Memory
(8000 Hex). The most significant bit enables the display
when not within the scroll (dynamic) area.
The display map memory is fixed at the first 16 words in
the closed caption display memory.
b9
b8
b7
b6
b5
b4
b3
b2
b1
Display
possible
Soft Scrolling
display possible
Display
possible
ROW
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Fig.27 Display Map and Data Pointers

SOFT SCROLL ACTION
The dynamic scroll region is defined by the REG5:Scroll
Area, REG6:Scroll Range, REG14:Top Scroll line and the
REG8:Status Register. The scroll area is enabled when
the SCON bit is set in REG8: Status.
The position of the soft scroll area window is defined using
the Soft Scroll Position (SSP<3:0), and the height of the
window is defined using the Soft Scroll Height (SSH<3:0>)
both are in REG6:Scroll Range. The rows that are scrolled
through the window are defined using the Start Scroll Row
(STS<3:0>) and the Stop Scroll Row (SPS<3:0>) both are
in REG5:Scroll Area.
The soft scrolling function is done by modifying the Scroll
Line (SCL<3:0>) in REG14: Top Scroll Line. and the first
scroll row value SCR<3:0> in REG8:Status. If the number
of rows allocated to the scroll counter is larger than the
defined visible scroll area, this allows parts of rows at the
top and bottom to be displayed during the scroll function.
The registers can be written throughout the field and the
values are updated for display with the next field sync.
Care should be taken that the register pairs are written to
by the software in the same field.
Only a region that contains only single height rows or only
double height rows can be scrolled.
b0
Pointer to Row Data

Reserved, should be set to 0
Text Display Enable, valid outside Soft Scroll Area
0 = Disable
1 = Enable
Table 31 Display map Bit Allocation
2003 Nov 11
Text Area
Display Data
TEXT DISPLAY CONFIGURATION

Two types of area are possible. The one area is static and
the other is dynamic. The dynamic area allows scrolling of
a region to take place. The areas cannot cross each other.
Only one scroll region is possible.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Enable bit = 0
Display Map Entries
Display Memory
Text Display Controls
b11 b10
UOCIII series
84
CONFIDENTIAL

ROW
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Soft Scroll Position

Pointer SSP<3:0> e.g. 6
Soft Scroll Height
SSH<3:0> e.g.4
Usable for OSD Display
Start Scroll Row

STS<3:0> e.g. 3
Should not be used for

OSD Display
Soft Scrolling Area

Should not be used for
OSD Display
Stop Scroll Row
SPS<3:0> e.g. 11
Usable for OSD Display
Fig.28 Soft Scroll Area
ROW
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0-63 lines
row0
row1
P01 NBC
row2
row3
row4
row5
row6
row7
row8
Closed
Captioning data row n

Closed Captioning data row n+1
row13
Scroll Area
Offset
Visible area
for scrolling
row14
Fig.29 CC Text Areas
2003 Nov 11
85
CONFIDENTIAL
UOCIII series

Two Page Display
This mode enables two different pages to be displayed
side by side for use with 16:9 TV Screens. Fig.30 shows
the possible combinations for two page display. The facility
is restricted to 1H/1V. Two page mode is selected using Bit
0 of Display Configuration register 87FF. Two character

spaces are required between the pages to allow the
display logic to switch correctly.
Screen Colour Area
Text
Screen Colour Area
Text
OSD
Text
Screen Colour Area
Text
UOCIII series
Screen Colour Area
Text
Video
Text
Screen Colour Area
Screen Colour Area
Video
Video
CC
Screen Colour Area

CC
OSD
CC
OSD
Screen Colour Area
Text
Text
Fig.30 Two Page TXT/CC/Video Combination
2003 Nov 11
Text
Subtitle
86
CONFIDENTIAL
CC
OSD

UOCIII series
Screen Colour: Only the Screen colour definition for Text
is required to be duplicated since only 1 CC page is
possible on a side with video on the other. The Text
Screen Colour register Txt17<2:0> applies to Text area A
and Txt27<2:0> shall determine Screen Colour in Text
Area B.
Two CC_TXT mode control bits exist in two page mode,

TXT21<0> controls Text Area A and TXT31<6> (CC_TXT
B) controls Text Area B.
TXT:When displaying two teletext pages side by side, Text Area
A display is selected using the Page A<3:0> register
TXT14<3:0> and Text Area B is selected using the Page
B<3:0> register TXT28<3:0>. The rolling header and time
information written by Acquisition will only apply to the
active page.
Active Page Operation:
i) When reset to logic 0 (default value), acquisition writes
the header and time information to Text Area A. When set
to logic 1, acquisition writes the header and time
information to Text Area B.
ii) The display uses the Active Page bit to direct which
page (0 = Text Area A, 1 = Text Area B) to allow
operation of the Reveal bit, TXT7<5>, and Cursor,
TXT7<6>. The Expand mode is controlled individually on
each page.
CC:- When CC display mode is selected in two page mode
only one screen half may be used for CC/OSD and the
other either Text or Video. Two page CC display side by
side is not possible due to CC display RAM limitation (only
1 block RAM for CC).
To allow some flexibility in 2 page mode the DRCS Enable
bit is duplicated for the second page into TXT23<2>. This
allows two Text OSD pages, displayed in 2 page mode, to
use Character Rom OSD in one page and DRCS in the
other.
Double Window
In this mode, the video picture will display in the left half of
the screen, the other half is for Text. The control bit is
enabled in SFR Video_process.DW_PA<1:0>=01
enables double window functionality.
Character Set Selection

Individual control of the Basic Character Set / Twist
Character Set and National Option Table are possible
using TXT18, TXT19, TXT23 and TXT29. The East/West
bit TXT4<5> will apply to both pages.
Boxes
The teletext mode control registers (TXT5 & TXT6) are
duplicated (TXT24 & TXT25) so that, for example, a text
page can be displayed on one side and a subtitled page.
Display Attributes
Separate control of Fringing, Screen colour and
Transparent mode is required for each Text Area.
Fringing: Control of which page has fringing is controlled
by TXT4<0> for Text Area A and TXT26<3> for Text Area
B. The fringe colour and direction applies to both pages i.e.
Fringing Control MMR 87F3.
Trans: The facility to display Black background as
transparent is controlled by TXT4<1> for Text Area A and
TXT26<6> for Text Area B.
2003 Nov 11
87
CONFIDENTIAL

UOCIII series
Panorama
Linear and non-linear horizontal scaling circuit for aspect
ratio conversion 4:3 video signal to 16:9 screen are
controlled by SFR Video_process.DW_PA<1:0>.
DW=0, without Text, two-page=0
DW_PA<1:0>
DW=0, with Text, two-page=0
Modes
00
Normal mode, both DW and Panorama mode

are disable.
01
Double Window Mode Enable
10
Enable linear scaling for 4:3 video signal

displaying on 16:9 screen.
11
Enable non-linear scaling for 4:3 video signal

displaying on 16:9 screen
Text
Table 32 DW and Panorama Scaling Modes
DW=0, two-page=1
4:3 video signal
Text
linear scaling
DW=1, two-page=1
Text
non-linear scaling
Fig.31 Double Window Feature
Fig.32 4:3 Video Signal Scaling to 16:9 Screen
2003 Nov 11
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CONFIDENTIAL

Display Positioning (Single Page)
The display consists of the Screen Colour covering the
whole screen and the Text Area that is placed within the
visible screen area. The screen colour extends over a
UOCIII series
large vertical and horizontal range so that no offset is
needed. The text area is offset in both directions relative to
the vertical and horizontal sync pulses.
Horizontal Sync.
Screen Colour Offset = 7.11s
Vertical
Sync.
6 Lines
Offset
Screen Colour Area

H-Sync delay
Text Area
0.25 char. offset
Text Area Start

Text Area End
49.78s
Fig.33 Display Area Positioning (Single Page)
Display Positioning (Two Page)

The display consists of the two Screen Colours covering
each half of the screen and two Text Areas that are placed
within the visible screen area. The screen colour extends
over a large vertical and horizontal range so that no offset
is needed. The both text areas are offset in both directions
relative to the vertical and horizontal sync pulses. The
second page may be positioned relative to HSYNC delay
using the Page B Position MMR, active to the vertical and
horizontal sync pulses. The second page may be
positioned relative to HSYNC delay using the Page B
Position MMR.
2003 Nov 11
89
CONFIDENTIAL
Text
Vertical
Offset

UOCIII series
Horizontal Sync.
Screen Colour Offset = 7.11s
Vertical
Sync.
6 Lines
Offset
Screen Colour Area

H-Sync delay
Text
AreaA
0.25 char. offset
Text
Vertical
Offset
Text
AreaB
Text Area
Start A
Text Area
Start B
Text Area End A

Page B Start
Text Area
End B
0.25 char. offset

Min.
2 Char.
Spaces
49.78s
Fig.34 Display Area Positioning (Two Page)
The visible text area for Page A is controlled using the
TEXT AREA START and TEXT AREA END MMRs. Page
B visible text area is controlled using the TEXT AREA
START B and TEXT AREA END B MMRs.
2003 Nov 11
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CONFIDENTIAL

Three extra memory mapped registers control the position

of the second page: REG17: Text Area Start B, REG18:
Text Area End B and REG19: Page B Position.
Page B positioning register controls the positioning of Text
Area B relative to HSYNC delay. A minimum two character
gap should be allowed between each page to allow the
reset of attributes.
Control of the vertical offset is as per single page operation
using REG1: Text Position Vertical Register.
The text area can be defined to start with an offset in the
horizontal direction as follows:
SCREEN COLOUR DISPLAY AREA

This area is covered by the screen colour. The screen
colour display area starts with a fixed offset of 8 us from
the leading edge of the horizontal sync pulse in the
horizontal direction. A vertical offset is not necessary.
Horizontal
starts 7.11us after the leading edge of H-Sync for

49.78 us.
Vertical
line 9, field 1 (321, field 2) with respect to leading

edge of vertical sync (line numbering using 625
Standard).
UOCIII series
Table 33 Screen Colour Display Area
Horizontal
TEXT DISPLAY AREA (SINGLE PAGE)

The text area can be defined to start with an offset in both
the horizontal and vertical direction.
Up to 48 full sized characters per row.

Start position setting from 3 to 128 characters from
the leading edge of H-Sync. Fine adjustment in
quarter characters.
Table 35 Text Display Area B

Horizontal
Up to 48 full sized characters per row.

Start position setting from 3 to 64 characters from
the leading edge of H-Sync. Fine adjustment in
quarter characters.
Vertical
256 lines (nominal 41- 297).

Start position setting from leading edge of vertical
sync legal values are 4 to 64 lines.
(line numbering using 625 Standard)
The horizontal offset is set in REG17: Text Area Start. The

offset is done in full width characters using TAS B<5:0>
and quarter characters using HOP B<1:0> for fine setting.
The values 00h to 03h for TAS<5:0> will result in a
corrupted display.
The width of the text area is defined in REG18: Text Area
End by setting the end character value TAE B<5:0>. This
number determines where the background colour of the
Text Area B will end if set to extend to the end of the row.
It will also terminate the character fetch process thus
eliminating the necessity of a row end attribute. This
entails however writing to all positions.
Table 34 Text Display Area

The horizontal offset is set in REG2: Text Area Start. The
offset is done in full width characters using TAS<5:0> and
quarter characters using HOP<1:0> for fine setting. The
values 00h to 03h for TAS<5:0> will result in a corrupted
display.
The width of the text area is defined in REG4:Text Area
End by setting the end character value TAE<5:0>. This
number determines where the background colour of the
Text Area will end if set to extend to the end of the row. It
will also terminate the character fetch process thus
eliminating the necessity of a row end attribute. This
entails however writing to all positions.
The vertical offset is set in REG1:Text Position Vertical
Register. The offset value VOL<5:0> is done in number of
TV scan lines.
NOTE: REG1:Text Position Vertical Register should not
be set to 00 Hex as the Display Busy interrupt is not
generated in these circumstances.
Character Set
To facilitate the global nature of the device the character
set has the ability to accommodate a large number of
characters, which can be stored in different matrices.
CHARACTER MATRICES
The character matrices that can be accommodated are: (HxVxPlanes) 12x9x1, 12x13x1, 12x16x1, 16x16x1 and
16x18x1. These modes allow two colours per character
position.
In CC mode four additional character matrices are
available to allow four colours per character: (HxVxPlanes) 12x13x2, 12x16x2, 16x16x2 and 16x18x2.
The characters are stored physically in ROM in a matrix of
size either 12x16, 16x18.
CHARACTER SET SELECTION
Four character sets are available in the device. A set can
consist of alphanumeric characters as required by the
WST Teletext or FCC Closed Captioning, Customer
TEXT DISPLAY AREA (TWO PAGE)

Control of Page A in two page mode is as per the control
in single page mode.
2003 Nov 11
91
CONFIDENTIAL

definable On-Screen Display characters, and Special
Graphic characters.
CC:- Two control mechanism are available controlled
using TXT20<4>.
When Char Select Enable is set inactive (TXT20<4>):
Only a single character set can be used for display and this
is selected using the Basic Set selection TXT18.BS<1:0>.
When selecting a character set in CC mode the Twist Set
selection TXT19.TS<1:0> should be set to the same value
as TXT18.BS<1:0> for correct operation.
When Char Select Enable is set active (TXT20<4>):
The Character Set is selected using the Display Character
code (Bit-12 & Bit-13) on a character by character basis.
Selection is as per the basic character set selection
(TXT18.BS<1:0>).
TXT:- Two character sets can be displayed at once. These
are the basic G0 set or the alternative G0 set (Twist Set).
The basic set is selected using TXT18.BS<1:0>, The
alternative/twist character set is defined by
TXT19.TS<1:0>. Since the alternative character set is an
option it can be enabled or disabled using TXT19.TEN,
and the language code that is defined for the alternative
set is defined by TXT19.TC<2:0>.
The National option table is selected using
TXT18.NOT<3:0>. A maximum of 32 National Option
tables can be defined when combined with the E/W control
bit (TXT4 Bit-5).
An example of the character set selection and definitions
is shown in Table 36
S<1:0>/TS<1:0>
Character
Set
Example Language
00
Set 0
Latin
01
Set 1
Greek
10
Set 2
Cyrillic
11
Set 3
Closed Caption
UOCIII series
4000H
CHAR PIXEL
DATA
Look-Up Set3
0600
Look-Up Set2
0400
0800H
Look-Up Set1
0200
LOOK-UP
Basic + Nat Opt
2048 location
Look-Up Set 0
0000H
0000
Fig.35 ROM Organization

Although the hardware implement of character set
selection of Closed Caption can select one of the four sets,
but due to the DDS tool restrictive, the Look-Up Set 0 is for
Teletext only; the Look-Up Set1, Set2 and Set3 are for
Closed Caption and Teletext depend on S/W setting.
Table 36 Character Set Selection

ROM ADDRESSING
Three ROMs are used to generate the correct pixel
information. The first contains the National Option look-up
table, the second contains the Basic Character look-up
table and the third contains the Character Pixel
information. Although these are individual ROM, since
they do not need to be accessed simultaneously they are
all combined into a single ROM unit.
2003 Nov 11
0800
14 x 16 bits
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CONFIDENTIAL

UOCIII series
CHARACTER TABLE
The character table is shown in Table 37:Character code columns (Bits 4-7)
0
Character code rows (Bits 0-3)
SP
1/2
"
&
<
>
Table 37 Closed Caption Character Table
Special Characters are in column 8 & 9.

Additional table locations for normal characters
Table locations for normal characters
Re-definable Characters
A number of Dynamically Redefinable Characters (DRC)
are available. These are mapped onto the normal
character codes, and replace the predefined ROM value.
-Extended DRC Mode(TXT26.EXTENDED DRCS = 1):

Extra character codes (column A/C) will be used as DRC
characters, thus there are max. 64 DRCs.
Each character is stored in a matrix of 16x18x1 (H x Vx
planes), this allows for all possible character matrices.
-Normal DRC Mode(TXT26.EXTENDED DRCS = 0):

There are 32 DRCs, the first 16 occupy the character
codes 80Hto 8FH, the second 16 occupy the locations 90H
to 9FH. This allows for 32 DRCs in TXT mode, 32 DRCs
in CC mode and 32 Normal or 16 Special DRCs in OSD
mode.The remapping of the standard OSD to the DRCs is
activated when the TXT20.DRCS ENABLE<7> for Page A,
or TXT23.DRCS ENABLE<2> for Page B bit is set. The
selection of Normal or Special OSD symbols is defined by
the TXT20.OSD PLANES<6> for Page A, TXT29.OSD
PLANES<4> for Page B.
2003 Nov 11
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CONFIDENTIAL

Micro Address
8800h
CHAR 0
CHAR 32
CHAR 1
CHAR 33
CHAR 2
CHAR 34
8823h
8824h
8847h
8848h
8C80h
8CA3h
8CA4h
8CC7h
8CC8h
8CEBh
886Bh
CHAR XX
90B8h
8C38h
CHAR 30
CHAR 62
CHAR 31
CHAR 63
90DBh
90DCh
8C5Bh
8C5Ch
Line
No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
16 bits
90FFh
8C7Fh
UOCIII series
Hex
440
003
00C
030
0C0
300
C00
C00
300
C00
030
00C
003
000
1A8
000
Top Left
Pixel
Fig.36 Organisation of DRC RAM
MSB
LSB
Fringing
Top Line
Bottom Line
Fringing
Line not used
Line 1 from
character below
DEFINING CHARACTERS
The DRC RAM is mapped into the 80C51 RAM address
space and starts at location 8800H. The character matrix
is 16 bits wide and therefore requires two bytes to be
written for each word, the first byte (even addresses)
addresses the lower 8 bits and the second byte (odd
addresses) addresses the upper 8 bits.
For characters of 9, 10, 16 or 18 lines high the pixel
information starts in the first address and continues
sequentially for the required number of address.
Characters of 13 lines high are slightly different to the
others as they have the added feature of fringing across
row boundaries. This is not normally possible, but can be
achieved by programming a copy of the bottom line of the
character above and the top line of the character below
within the DRCS character definition. This technique is
especially useful for clustered characters.
Bottom Right
Pixel
Fig.37 13 Line High DRCs Character Format

Display Synchronization
The horizontal and vertical synchronizing signals from the
TV deflection are used as inputs. Both signals can be
inverted before being delivered to the Display section for
timing reference.
CC: The polarity is controlled using either VPOL or HPOL
in REG2:Text position Vertical.
TXT: SFRs bits TXT1.HPOL & TXT1.VPOL control the
polarity.
Video/Data Switch (Fast Blanking) Polarity
The polarity of the Video/Data (Fast Blanking) signal can
be inverted. The polarity is set with the VDSPOL in REG7:
RGB Brightness register.
With the addition of the larger 18 line high characters, this

feature of fringing across clustered characters is no longer
essential. For DRCS, however, this feature has been
retained for backward compatibility. It should be noted that
13 line ROM characters are no longer coded in this way.
The required character is defined with an initial offset of 1
address with the bottom line of the character above copied
into the very first address (line 0). The top line of the
character below is copied below the character definition
(line 14), see Fig.37. Only lines 1 to 13 are actually
displayed. Lines 0 and 14 are only read by the fringing
generator.
To allow some flexibility in 2 page mode the DRCS Enable
bit is duplicated for the second page into TXT23<2>.This
shall allow two Text OSD pages, displayed in 2 page
mode, to use Character ROM OSD in one page and DRCS
in the other.
2003 Nov 11
Line 13 from
character above
VDSPOL
VDS
Condition
RGB display
Video Display
RGB display
Video Display
Table 38 Fast Blanking Signal Polarity

Video/Data Switch Adjustment
To take into account the delay between the RGB values
and the VDS signal due to external buffering, the VDS
signal can be moved in relation to the RGB signals. The
VDS signal can be set to be either a clock cycle before or
94
CONFIDENTIAL

after the RGB signal, or coincident with the RGB signal.
This is done using VDEL<2:0> in REG15:Configuration.
Contrast Reduction
TXT: The COR bits in SFRs TXT5 & TXT6 control when
the COR output of the device is activated (i.e. Pulled-low).
This output is intended to act on the TVs display circuits to
reduce contrast of the video when it is active. The result of
contrast reduction is to improve the readability of the text
in a mixed teletext and video display.
The bits in the TXT5 & TXT6 SFRs allow the display to be
set up so that, for example, the areas inside teletext boxes
will be contrast reduced when a subtitle is being displayed
but that the rest of the screen will be displayed as normal
video.
In Teletext display mode the serial teletext box attribute
and OSD box attribute define the region of the screen
where Contrast Reduction is active.
In CC display mode the serial character attribute Boxing
is used to define the region of the screen in which the
Contrast Reduction is active.
RGB Brightness Control

A brightness control is provided to allow the RGB upper
output voltage level to be modified. The RGB amplitude
may be varied between 60% and 100%.
The brightness is set in the RGB Brightness register as
follows: BRI3-0
RGB Brightness
0 0 0 0
Lowest value
...
1 1 1 1
UOCIII series
...
Highest value
Table 39 RGB Brightness
Memory Mapped Registers

The memory mapped registers are used to control the
display. The registers are mapped into the Micro-controller
MOVX address space, starting at address 87E0h and
extending to 87FF.
MMR MAP
ADD
R/W
Functions
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SRC<3>
SRC<2>
SRC<1>
SRC<0>
msh
MOD<1>
MOD<0>
87F0
R/W
Display
Control
87F1
R/W
Text Position
Vertical
VPOL
HPOL
VOL<5>
VOL<4>
VOL<3>
VOL<2>
VOL<1>
VOL<0>
87F2
R/W
Text Area Start
HOP<1>
HOP<0>
TAS<5>
TAS<4>
TAS<3>
TAS<2>
TAS<1>
TAS<0>
87F3
R/W
Fringing
Control
FRC<3>
FRC<2>
FRC<1>
FRC<0>
FRDN
FRDE
FRDS
FRDW
87F4
R/W
Text Area End
TAE<5>
TAE<4>
TAE<3>
TAE<2>
TAE<1>
TAE<0>
87F5
R/W
Scroll Area
SSH<3>
SSH<2>
SSH<1>
SSH<0>
SSP<3>
SSP<2>
SSP<1>
SSP<0>
87F6
R/W
Scroll Range
SPS<3>
SPS<2>
SPS<1>
SPS<0>
STS<3>
STS<2>
STS<1>
STS<0>
87F7
R/W
VDSPOL
BRI<3>
BRI<2>
BRI<1>
BRI<0>
87F8
Status read
BUSY
FIELD
SCON
FLR
SCR<3>
SCR<2>
SCR<1>
SCR<0>
87F8
Status write
SCON
FLR
SCR<3>
SCR<2>
SCR<1>
SCR<0>
87FC
R/W
H-Sync. Delay
HSD<6>
HSD<5>
HSD<4>
HSD<3>
HSD<3>
HSD<1>
HSD<0>
87FD
R/W
V-Sync. Delay
VSD<6>
VSD<5>
VSD<4>
VSD<3>
VSD<2>
VSD<1>
VSD<0>
2003 Nov 11
RGB Brightness
95
CONFIDENTIAL

87FE
R/W
Top Scroll Line
87FF
R/W
Configuration
87E0
R/W
Text Area Start

B
87E1
R/W
87E2
UOCIII series
SCL<3>
SCL<2>
SCL<1>
SCL<0>
CC
VDEL<2
>
VDEL<1>
VDEL<0>
TXT/V
Two_Page
HOPB<1>
HOPB<0
>
TASB<5>
TASB<4>
TASB<3>
TASB<2>
TASB<1>
TASB<0>
Text Area End B
TAEB<5>
TAEB<4>
TAEB<3>
TAEB<2>
TAEB<1>
TAEB<0>
R/W
Page B Position
PGB<6>
PGB<5>
PGB<4>
PGB<3>
PGB<2>
PGB<1>
PGB<0>
87E3
R/W
Text Position
Vertical B
VOLB<5>
VOLB<4>
VOLB<3>
VOLB<2>
VOLB<1>
VOLB<0>
87E4
R/W
Text Position
Vertical Range
SMTHB
SMTH
RANGE
<1>
RANGE
<0>
RANGEB
<1>
RANGEB
<0>
Table 40 MMR Map
MMR BIT DEFINITION
Names
Display Control.
SRC<3:0>
msh
MOD<1:0>
Text Position
Vertical
VPOL
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
SRC<3>
SRC<2>
SRC<1>
SRC<0>
msh
MOD<1>
MOD<0>
00H
VOL<4>
VOL<3>
VOL<2>
VOL<1>
VOL<0>
00H
TAS<4>
TAS<3>
TAS<2>
TAS<1>
TAS<0>
00H
FRC<0>
FRDN
FRDE
FRDS
FRDW
00H
Screen Colour definition

00 - Video
01 - Full Text
10 - Mixed Screen Colour
11 - Mixed Video
VPOL
HPOL
VOL<5>
0 - Input polarity
1 - Inverted input polarity
HPOL
VOL<5:0>
Text Area Start
0 - Input Polarity
1 - Inverted input polarity
Display start Vertical Offset from V-Sync. (lines)
HOP<1>
HOP<0>
TAS<5>
HOP<1:0>
Fine Horizontal Offset in quarter of characters
TAS<5:0>
Text area start
Fringing Control.
FRC<3:0>
FRDN
FRC<3>
FRC<2>
FRC<1>
Fringing colour, value address of CLUT

0 - No fringe in North direction
1 - Fringe in North direction
FRDE
2003 Nov 11
0 - No fringe in East direction

1 - Fringe in East direction
96
CONFIDENTIAL

FRDS
0 - No fringe in South direction

1 - Fringe in South direction
FRDW
0 - No fringe in West direction

1 - Fringe in West direction
Text Area End
TAE<5:0>
Scroll Area
TAE<5>
TAE<4>
TAE<3>
TAE<2>
TAE<1>
TAE<0>
00H
SSH<1>
SSH<0>
SSP<3>
SSP<2>
SSP<1>
SSP<0>
00H
SPS<2>
SPS<1>
SPS<0>
STS<3>
STS<2>
STS<1>
STS<0>
00H
BRI<3>
BRI<2>
BRI<1>
BRI<0>
00H
SCON
FLR
SCR<3>
SCR<2>
SCR<1>
SCR<0>
00H
SCR<3>
SCR<2>
SCR<1>
SCR<0>
00H
Text Area End, in full characters

SSH<3>
SSH<2>
SSH<3:0>
Soft Scroll Height
SSP<3:0>
Soft Scroll Position
Scroll Range
SPS<3>
SPS<3:0>
Stop Scroll row
STS<3:0>
Start Scroll row
RGB Brightness
VDSPOL
VDSPOL
VDS Polarity
0 - RGB (1), Video (0)
1 - RGB (0), Video (1)
BRI<3:0>
RGB Brightness control
Status read
BUSY
FIELD
BUSY
0 - Access to display memory will not cause display problems

1 - Access to display memory could cause display problems.
FIELD
0 - Odd Field
1 - Even Field
FLR
SCR<3:0>
Status write
0 - Active flash region foreground and background displayed

1 - Active flash region background only displayed
First scroll row
-
SCON
FLR
UOCIII series
SCON
FLR
0 - Scroll area disabled

1 - Scroll area enabled
0 - Active flash region foreground and background colour displayed
1 - Active flash region background colour only displayed
SCR<3:0>
H-Sync. delay
First Scroll Row

-
HSD<6:0>
V-Sync Delay
Top Scroll Line

SCL<3:0>
Configuration
2003 Nov 11
HSD<4>
HSD<3>
HSD<3>
HSD<1>
HSD<0>
00H
VSD<6>
VSD<5>
VSD<4>
VSD<3>
VSD<2>
VSD<1>
VSD<0>
00H
V-Sync delay in number of TV lines

-
VDEL<2>
VDEL<1>
VDEL<0>
SCL<3>
SCL<2>
SCL<1>
SCL<0>
00H
Top line for scroll

CC
CC
HSD<5>
H-Sync delay, in full size characters

-
VSD<6:0>
HSD<6>
TXT/V
0 - OSD mode
1 - Closed Caption mode
97
CONFIDENTIAL
Two_Page
00H

VDEL<2:0>
TXT/V
Two_Page
Text Area Start B
Pixel delay between VDS and RGB output

000 - VDS switched to video, not active
001 - VDS active one pixel earlier then RGB
010 - VDS synchronous to RGB
100 - VDS active one pixel after RGB
BUSY Signal switch
0 - Vertical
1 - Horizontal
Two Page mode select
0 - Single page
1 - Dual page
HOP<1>
HOP<0>
TAS<5>
TAS<4>
TAS<3>
TAS<2>
TAS<1>
TAS<0>
00H
TAE<5>
TAE<4>
TAE<3>
TAE<2>
TAE<1>
TAE<0>
00H
PGB<6>
PGB<5>
PGB<4>
PGB<3>
PGB<2>
PGB<1>
PGB<0>
00H
VOLB<5>
VOLB<4>
VOLB<3>
VOLB<2>
VOLB<1>
VOLB<0>
00H
HOP<1:0>
Fine Horizontal Offset in quarter of characters
TAS<5:0>
Text area start
Text Area End B

TAE<5:0>
Page B Position
PGB<6:0>
Text Position
Vertical B
VOLB<5:0>
Vertical Range
SMTHB
SMTH
RANGE<1:0>
RANGEB<1:0>
UOCIII series
Text Area End, in full characters

0
Page B Position
-
Page B start Vertical Offset from V-Sync. Value is in horizontal scan lines. Must be set to VOL<5:0> in double window mode.
-
SMTHB
SMTH
RANGE
<1>
RANGE
<0>
0 - Smoothing inactive (page B)

1 - Smoothing active for Double Size, Double Height and Double Width (page B)
0 - Smoothing inactive (single page or page A)
1 - Smoothing active for Double Size, Double Height and Double Width (single page or page B)
Bits<7:6> of VOL (single page or page A vertical offset)
Bits<7:6> of VOLB (page B vertical offset). Must be set to RANGE<1:0> in double window and two page mode.
Table 41 MMR Descriptions
2003 Nov 11
RANGEB
<1>
98
CONFIDENTIAL
RANGEB
<0>
00H

SCAVEM TEXT OUTPUT
UOCIII series
FLASH MEMORY
These may be programmed/erased via the ISP Interface.
The flash memory can be erased/written over 100k times.
The Scavem (Scan Velocity Modulator) circuit is existed in

the Video Signal Processor die. The function is to enhance
edge details by varying the speed of the electric beam,
providing a sharp and crisp picture. The generated
character would have this feature by providing a
SCAVTXT signal to video processing die. The SCAVTXT
signal is generated from R, G and B signals. The SFR,
SCAVTXT.SCAVEM_EN is high active to enable the
signal output. The Scavem text processing needs about
200ns. The SCAVTXT signal should go to Video Signal
Processor earlier than R, G and B signals 200ns as well.
ISP Interface
ISP is via Hs-mode I2C upto 1.2 Mb/s.
FLASH MEMORY ORGANIZATION
Sector x-1
page ss-1
For flexibility of adjusting the delay between SCAVTXT

and R, G, and B signals, an SFR, SCAVTXT. EARLY<2:0>
is for this purpose.
EARLY<2:0>
SCAVTXT output earlier than R, G, and B signals
page 1
000
0 ns
page 0
001
74 ns
010
111 ns
011
148 ns
100
185 ns
101
212 ns
110
259 ns
111
296 ns
Sector 1
256 bytes
Sector 0
Fig.38 Flash memory organization
Table 42 Delay between SCAVTXT and R, G, B
The sectors are used to put program and character codes.
The pulse width of SCAVEM text signal is defined in the

SFR, SCAVTXT.PULSE_WIDTH<1:0>.
PULSE_WIDTH<1:0>
SCAVEM Text pulse width
00
37 ns
01
74 ns
10
111 ns
11
148 ns
Table 43 SCAVEM Text pulse width
2003 Nov 11
99
CONFIDENTIAL

Programming procedures
Flash programming procedure is shown as below:
Enter ISP mode
Erase flash
write flash
verify flash
UOCIII series
Enter ISP mode
There are mainly two cases using ISP mode when the
UOCIII is mounted on PCB or TV. One case is the content
of flash memory is empty. Another case is that the
customer code (program and character codes) were
programmed in flash memory and need to be upgraded.
Enter ISP mode when flash memory is empty
In this case, the I2C bus is not occupied by the
micro-controller, therefore follow the flows:- send the
correct slave address, erase flash, write flash, and verify
flash sections can access to the flash memory via I2C.
Enter ISP mode when code is existed in flash memory
and is running
In this case, embedded software should release the
I2C-bus first and then following the flows:- send the correct
slave address, erase flash, write flash, and verify flash
sections can access to the flash memory via I2C.
The complete programming flow is supported by the WISP
tool from Philips Semiconductors.
Power-on-reset
Fig.39 Flash programming procedure
2003 Nov 11
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CONFIDENTIAL

UOCIII series
FUNCTIONAL DESCRIPTION OF VIDEO PROCESSOR
QSS Sound circuit
Vision IF amplifier
The sound IF amplifier is similar to the vision IF amplifier

and has an external AGC decoupling capacitor.
The vision IF amplifier can demodulate signals with

positive and negative modulation. The PLL demodulator is
completely alignment-free.
The VCO of the PLL circuit is internal and the frequency is
fixed to the required value by using the clock frequency of
the TCG -Controller as a reference. The setting of the
various frequencies (e.g. 38, 38.9, 45.75 and 58.75 MHz)
can be made via the control bits IFA-IFC in subaddress
2FH. Because of the internal VCO the IF circuit has a high
immunity to EMC interferences.
The output of the AFC detector can be read from output
byte 04H and has a resolution of 7 bits (25 kHz per step).
By means of this information a fast tuning algorithm can be
designed.
The IC contains a group delay correction circuit which can
be switched between the BG and a uncompensated group
delay response characteristic. This has the advantage that
in multi-standard receivers no compromise has to be made
for the choice of the SAW filter. This group delay correction
is realised for the demodulated CVBS output signal. The
IC contains in addition a sound trap circuit with a
switchable centre frequency.
Digital Broadcast reception
Apart from processing analogue TV signals, the IF circuit
can also preprocess digital TV signals before they are sent
to a digital signal processor. These signals have to be
supplied to the sound IF inputs. In this mode the IF
reference frequency is fixed at 43.008 or 49.152 MHz. It is
also possible to supply an external reference signal to
demodulator. The demodulator multiplies the incoming
signal with the fixed oscillator frequency. The mixed down
signal is low pass filtered to obtain a I-signal. The Stereo
and AV Stereo versions have a differential output,
however, it is possible to use a single-ended output. The
various output signal conditions can be set by means of
the IFO2-IFO0 bits in subaddress 31H (see also table 94).
The Mono versions have a single-ended output.
The AGC has two modes of operation: the internal mode
in which the IC sets the gain with its own reference and an
external mode in which the gain can be controlled with an
external circuit. In the second case the SIFAGC pin is used
as an input to control the IF gain with an external circuit.
The single reference QSS mixer is realised by a multiplier.

In this multiplier the SIF signal is converted to the
intercarrier frequency by mixing it with the regenerated
picture carrier from the VCO. The mixer output signal is
supplied to the output via a high-pass filter for attenuation
of the residual video signals. With this system a high
performance hi-fi stereo sound processing can be
achieved.
The AM sound demodulator is realised by a multiplier. The
modulated sound IF signal is multiplied in phase with the
limited SIF signal. The demodulator output signal is
supplied to the output via a low-pass filter for attenuation
of the carrier harmonics.
Switching between the QSS output and AM output is made
by means of the AM bit in subaddress 33H.
FM demodulator
The FM demodulator is realised as narrow-band PLL with
internal loop filter, which provides the necessary selectivity
without using an external band-pass filter. To obtain a
good selectivity a linear phase detector and a constant
input signal amplitude are required. For this reason the
intercarrier signal is internally supplied to the demodulator
via a gain controlled amplifier and AGC circuit. To improve
the selectivity an internal bandpass filter is connected in
front of the PLL circuit.
The nominal frequency of the demodulator is tuned to the
required frequency (4.5/5.5/6.0/6.5 MHz) by means of a
calibration circuit which uses the clock frequency of the
TCG(1) -Controller as a reference. It is also possible to
frequencies of 4.72 and 5.74 MHz so that a second sound
channel can be demodulated. In the latter application an
external bandpass filter has to be applied to obtain
sufficient selectivity (the sound input can be activated by
means of the setting of CMB2-CMB0 bits in subaddress
4AH). The setting to the wanted frequency is realised by
means of the control bits FMA, FMB and FMC in the
control bit 33H.
From the output status bytes it can be read whether the
PLL frequency is inside or outside the window and whether
the PLL is in lock or not. With this information it is possible
to make an automatic search system for the incoming
sound frequency. This can be realised by means of a
software loop which switches the demodulator to the
(1) TCG = Text/Control/Graphics
2003 Nov 11
101
CONFIDENTIAL

various frequencies and then select the frequency on
which a lock condition has been found.
The amplitude deemphasis output signal changed with 6
dB by means of the AGN bit. In this way output signal
differences between the 4.5 MHz standard (frequency
deviation 25 kHz) and the other standards (frequency
deviation 50 kHz) can be compensated.
FM radio mode
The FM demodulator can be used for the demodulation of
FM radio signals. This mode is activated by means of the
FMR-bit (subaddress 34H). The selectivity must be made
by means of a SAW filter at the sound input with a centre
frequency of 33.4 MHz for Europe and 41.25 MHz for the
USA. For this application the IF demodulator must be set
to a fixed frequency (43.008 MHz for Europe and
49.152 MHz for the USA). The resulting input frequency
for the FM demodulator is then 9.6 MHz for Europe and
7.9 MHz for the USA. This frequency must be selected by
means of the bits FMA, FMB and FMC (see table 104). In
the FM radio mode the demodulated intercarrier sound
output signal can be supplied to the output pin(s) (FMRO)
so that an external bandpass filter can be applied between
this pin and the SSIF pin.
The SSIF input can be either pin 33 or pin 53 (pins 96 or
76 respectively for the face down version). The selection
is made by means of the ESSIF bit in subaddress 35H.
The mono intercarrier sound circuit can also be combined
with an external FM tuner (IF frequency of 10.7 MHz). In
that case an external 10.7 MHz bandpass filter is required.
The demodulator centre frequency is set with the FMD bit
(subaddress 33H).
FM stereo decoding is possible in versions that contain the
digital multi-standard stereo decoder. This mode is
selected by means of the IFO2-IFO0 bits in subaddress
31H.
Audio input selector and volume control
STEREO AND AV STEREO VERSIONS
The audio input selector circuit has 4 external stereo
inputs, a stereo output for SCART/CINCH and stereo
outputs for headphone and audio power amplifiers. The
selection is made with the bits SAS2/0, SO2/0 and
HPO2/0. AV stereo versions without Audio DSP have no
headphone output. The input signal selection for the
volume controlled audio outputs is realised by the HPO2/0
bits.
2003 Nov 11
UOCIII series
The gain from an external audio input to each of the
(non-controlled) analog output is 0 or +6 dB (controlled by
the DSG bit). A supply voltage of 5V allows input and
output amplitude of 1VRMS full scale. The audio selector
circuit has a separate supply voltage pin. For audio output
signal amplitudes of 2VRMS full scale, as required to
comply with the SCART specification, the audio supply
voltage must be 8V. In that case the gain of the audio
amplifier must be doubled. This can be realised with the
DSG bit in subaddress 32H.
The circuit contains an analogue stereo volume control
circuit with a control range of about 70 dB. This volume
control circuit is used for the headphone channel (stereo
versions with Audio DSP) or for the main channel (AV
stereo versions without Audio DSP). The analogue control
circuit also contains an Automatic Volume Levelling (AVL)
function. When this function is activated it stabilises the
audio output signal to a certain level so that big fluctuations
of the output power are prevented.
MONO VERSIONS
The audio input selector circuit has 4 inputs for mono
signals. The selection is made with the HPO2/0 bits.
The circuit contains an analogue volume control circuit
with a control range of about 70 dB and an AVL circuit.
CVBS and Y/C input signal selection
ALL VERSIONS
The ICs have 3 inputs for external CVBS signals. All CVBS
inputs can be used as Y input for the insertion of Y/C
signals. However, the CVBS(Y)2 input has to be combined
with the C3 input. It is possible to add and extra
CVBS(Y/C) input via the pins which are intended to be
used for YUV interface (or RGB/YPRPB input). The
selection of this additional CVBS(Y/C) input is made via
the YC bit. The CVBS selector has one independently
switchable output. The switch configuration is given in
Fig. 40. The choice of the various modes can be made via
the INA-IND bits in subaddress 38H.
The function of the IFVO/SVO/CVBSI pin is determined by
the SVO1/SVO0 bits. When used as output a selection can
be made between the IF video output signal or the
selected CVBS signal (monitor out). This pin can also be
used as additional CVBS input. This signal is inserted in
front of the group delay / sound trap circuit. It is also
possible to use the group delay and sound trap circuit for
the CVBS2 signal (via the CV2 bit).
102
CONFIDENTIAL

For the CVBS(Y/C) inputs the circuit can detect whether a
CVBS or Y/C signal is present on the input. The result can
be read from the status register (YCD bit in subaddress
03H) and this information can be used to put the input
switch in the right position (by means of the INA-IND bits
in subaddress 38H). The Y/C detector is only active for the
CVBS(Y)3/C3, CVBS(Y)4/C4 and CVBS(Y)x/Cx inputs. It
is not active for the CVBS(Y)2/C3 input.
UOCIII series
The video ident circuit can be connected to all video input
signals. This ident circuit is independent of the
synchronisation and can be used to switch the
time-constant of the horizontal PLL depending on the
presence of a video signal (via the VID bit). In this way a
very stable OSD can be realised. The result of the video
ident circuit can be read from the output bit SID
(subaddress 00)
SYS
H/V
SYNC
VIDEO
SID
CFA0
IDENTIFICATION
SEPARATOR
4H/2H PAL/NTSC
GD
CV2 or SVO1
IFOUT
COMB FILTER
C
SVO1/SVO0
SOUND TRAP
GROUP DELAY
+
CORRECTION
IFOX
CVBS1
SVO1
IFOUT
SVO/IFOUT/CVBSI
CVBS/Y-2 CVBS/Y-3 C3
Fig.40 CVBS switch

Synchronisation circuit
The IC contains separator circuits for the horizontal and
vertical sync pulses. To obtain an accurate timing of the
displayed picture the input signal of the sync separator is
not derived from the various CVBS/Y or RGB/YPRPB
inputs but from the YOUT pin. For this reason the YOUT
pin must be capacitively coupled to the YSYNC pin. The
delay between the various inputs and the YOUT signal can
have rather large differences (e.g. comb filter active or
not). By choosing the YOUT signal as input signal for the
sync separator these delays have no effect on the picture
position. Only for RGB signals without sync on green the
input of the sync separator has to be connected to one of
the CVBS inputs. This selection is made by means of the
SYS bit.
2003 Nov 11
CVBS/Y-4
C4 CVBS/Y-x Cx
YSYNC CVBSO
G/Y-3
The horizontal drive signal is obtained from an internal

VCO which is running at a frequency of 25 MHz. This
oscillator is stabilised to this frequency by using the clock
signal coming from the reference oscillator of the TCG
-Controller.
To obtain a stable On-Screen-Display (OSD) under all
conditions it is important that the first control loop is
switched off or set to low gain when no signal is available
at the input. The input signal condition is detected by the
video identification circuit. The video identification circuit
can automatically switch first control loop to a low gain
when no input signal is available. This mode is obtained
when the VID bit is set to 0. When the VID bit is 1 the
mode of the first control loop can be switched by means of
the FOA/FOB or POC bits.
103
CONFIDENTIAL

UOCIII series
For a good performance during normal TV reception

(display of the front-end signal) various connections are
active between the vision IF amplifier and the
synchronisation circuit (e.g. gating pulses for the AGC
detector and noise gating of the sync separator). These
connections are not allowed when external video signals
are displayed. The switching of these connections can be
coupled to the input signal selection bits (INA-IND). This
mode is obtained when the VDXEN bit is 0. Due to the
input signal selector configuration it is possible that the
internal CVBS signal is available on one of the other CVBS
inputs. In this condition the connections between the vision
IF amplifier and the synchronisation circuit can be
switched on and off by means of the VDX bit. The VDXEN
bit must be set to 1 for this mode.
When the vertical amplitude is compressed (zoom

factor <1) it is still possible to display the black current
measuring lines in the overscan. This function is activated
by means of the bit OSVE in subaddress 40H.
The vertical synchronisation is realised by means of a

divider circuit.
The functionality of this pin is controlled by the VGM1/0

and LED bits.
Horizontal and vertical drive

The horizontal drive is switched on and off via the soft
start/stop procedure. The soft start function is realised by
means of variation of the TON of the horizontal drive
pulses. During the soft-stop period the horizontal output
frequency is doubled resulting in a reduction of the EHT so
that the picture tube capacitance can easily be discharged.
In addition the horizontal drive circuit has a low-power
start-up function.
The vertical ramp generator needs an external resistor and
capacitor. For the vertical drive a differential output current
is available. The outputs must be DC coupled to the
vertical output stage.
The IC has the following geometry control functions:
Vertical amplitude
Vertical slope
S-correction
Vertical shift
Vertical zoom
Vertical scroll
Vertical linearity correction. When required the linearity
setting for the upper and lower part of the screen can
have a different setting.
Horizontal shift
EW width
EW parabola width
EW upper and lower corner parabola correction
EW trapezium correction
The vertical guard input is combined with an I/O function.

The following functions can be realised with this pin:
Just vertical guard input.
Combination of vertical guard and LED drive output. In
this condition the output is high-ohmic during the vertical
retrace (1 ms) so that the vertical guard pulse can be
detected.
Single ended output switch
Input port
When the East-West geometry function is not required

(e.g. for 90 picture tubes) the EW output pin can be used
for the connection of the AVL capacitor. This function is
chosen by means of the AVLE bit.
The UOCIII devices can also be used as input processor
for 100 Hz or LCD TV receivers. In that case the deflection
drive signals are not required. For these applications an
H/V timing signal can be obtained from the flyback
input/sandcastle output pin. This mode is activated by
means of the CSY bit (subaddress 4AH). The horizontal
output pin is switched to high in this condition. A change
of the CSY bit is possible only in the stand-by mode
(STB = 0).
Chroma, luminance and feature processing
Some versions contain a 4H/2H (2D) adaptive PAL/NTSC
comb filter. The comb filter is automatically activated when
standard CVBS signals are received. A signal is
considered as standard signal when a PAL or NTSC
signal is identified and when the vertical divider is in the
modes standard narrow window or standard TV
norm.For non-standard signals and for SECAM signals
the comb filter is bypassed and the signal is filtered by
means of bandpass and trap filters.
The chroma band-pass and trap circuits (including the
SECAM cloche filter) are realised by means of internal
filters and are tuned to the right frequency by comparing
the tuning frequency with the reference frequency of the
colour decoder.
The circuit contains the following picture improvement
features:
Horizontal parallelogram and bow correction.

2003 Nov 11
104
CONFIDENTIAL

Peaking control circuit. The peaking function can be
activated for all incoming CVBS, Y/C and RGB/YPRPB
signals. Various parameters of the peaking circuit can
be adapted by means of the I2C-bus. The main
parameters are:
Peaking centre frequency (via the PF1/PF0 bits in
subaddress 19H).
Ratio of positive and negative peaks (via the
RPO1/RPO0 bits in subaddress 47H). The peaks in
the direction white are the positive peaks.
Ratio of pre- and aftershoots (via the RPA1/RPA0
bits in subaddress 47H).
Video dependent coring in the peaking circuit. The
coring can be activated only in the low-light parts of the
screen. This effectively reduces noise while having
maximum peaking in the bright parts of the picture.
Black stretch. This function corrects the black level for
incoming signals which have a difference between the
black level and the blanking level. The amount of
stretching (A-A in Fig. 72) and the minimum required
back ground to activate the stretching can be set by
means of the I2C-bus (BSD/AAS in subaddress 45H).
Gamma control. When this function is active the transfer
characteristic of the luminance amplifier is made
non-linear. The control curve can be adapted by means
of I2C-bus settings (see Fig. 74). It is possible to make
the gamma control function dependent on the picture
content (Average Picture Level, APL). The effect is
illustrated in Fig. 75. Previously this function was
mentioned under the name white stretch function.
Blue-stretch. This circuit is intended to shift colour near
white with sufficient contrast values towards more blue
to obtain a brighter impression of the picture.
Dynamic skin tone (flesh) control. This function is
realised in the YUV domain by detecting the colours
near to the skin tone.
Scan-Velocity modulation output. Also the SVM function
can be activated for all incoming CVBS, Y/C and
RGB/YPRPB signals. The delay between the RGB
output signals and the SVM output signal can be
adjusted (by means of the SVM2-SVM0 bits in
subaddress 48H) so that an optimum picture
performance can be obtained. Furthermore a coring
function can be activated. It is possible to generate Scan
Velocity Modulation drive signals during the display of
full screen teletext (not in mixed mode). Another
feature is that the SVM output signal can be made
dependent on the horizontal position on the screen
(parabola on the SVM output).
2003 Nov 11
UOCIII series
Colour decoder
The ICs decode PAL, NTSC and SECAM signals. The
PAL/NTSC decoder does not need external reference
crystals but has an internal clock generator which is
stabilised to the required frequency by using the clock
signal from the reference oscillator of the TCG
-Controller.
Under bad-signal conditions (e.g. VCR-playback in feature
mode), it may occur that the colour killer is activated
although the colour PLL is still in lock. When this killing
action is not wanted it is possible to overrule the colour
killer by forcing the colour decoder to the required standard
and to activate the FCO-bit (Forced Colour On) in
subaddress 3CH. The sensitivity of the colour decoder for
PAL and NTSC can be increased by means of the setting
of the CHSE1/CHSE0 bits in subaddress 3CH.
The Automatic Colour Limiting (ACL) circuit (switchable
via the ACL bit in subaddress 3BH) prevents that
oversaturation occurs when signals with a high
chroma-to-burst ratio are received. The ACL circuit is
designed such that it only reduces the chroma signal and
not the burst signal. This has the advantage that the colour
sensitivity is not affected by this function.
The SECAM decoder contains an auto-calibrating PLL
demodulator which has two references, viz: the divided
reference frequency (obtained from the -Controller)
which is used to tune the PLL to the desired free-running
frequency and the bandgap reference to obtain the correct
absolute value of the output signal. The VCO of the PLL is
calibrated during each vertical blanking period, when the
IC is in search or SECAM mode. The frequency offset of
the B-Y demodulator can be reduced by means of the
SBO1/SBO0 bits in subaddress 3CH.
The base-band delay line is integrated. In devices without
CVBS comb filter this delay line is also active during NTSC
to obtain a good suppression of cross colour effects. The
demodulated colour difference signals are internally
supplied to the delay line. The baseband comb filter can be
switched off by means of the BPS bit (subaddress 3CH).
The subcarrier output is combined with a 3-level output
switch (0 V, 2.1 V and 4.5 V). The output level and the
availability of the subcarrier signal is controlled by the
CMB2-CMB0 bits.
105
CONFIDENTIAL

UOCIII series
RGB output circuit
Table 44 Addition of WP, CL and gain register settings
In the RGB control circuit the signal is controlled on

contrast, brightness and saturation. The IC has a YUV
interface so that additional picture improvement ICs can
be applied. To compensate signal delays in the external
YUV path the clamp pulse in the control circuit can be
shifted by means of the CLD bit in subaddress 44H. When
the YUV interface is not required some of the pins can be
used for the insertion of RGB/YPRPB signals or as
additional CVBS(Y)/C input. When the YUV interface is not
used one of the pins (VOUT) is transferred to general
purpose output switch (SWO1). The IC has also a YUV
interface to the digital die. Via this loop digital features like
double window are added.
WPR(GB)
A tint control is available for the base-band U/V signals.

For this reason this tint control can be activated for all
colour standards. The signals for OSD and text are
internally supplied to the control circuit. The output signal
has an amplitude of about 1.2 V black-to-white at nominal
input signals and nominal settings of the various controls.
To obtain an accurate biasing of the picture tube the
Continuous Cathode Calibration system has been
included in these ICs. The system is slightly adapted
compared with the previous circuits. In the new
configuration the cut-off level of the picture tube is
controlled with a continuous loop whereas the correction of
the amplitude of the output signals is realised by means of
a digital loop. As a consequence the current measurement
can be controlled from the -Processor. The value of the
high current in the CCC loop can be chosen via the SLG0
and SLG1 bits (subaddresses 42H and 46H). The gain
control in the 3 RGB channels is realised by means of 7-bit
DACs. The total gain control range is 6 dB. The change
in amplitude at the cathodes of the picture tube for one
LSB is about 1.1 VP-P. The setting of the control DAC is
determined by the following registers:
The white point setting of the R, G and B channel in
subaddress 20H to 22H. This register has a resolution of
6 bits and the control range in output signal amplitude is
3 dB.
The cathode drive setting (CL3-CL0 in subaddress
42H). This setting is valid for all channels, the resolution
is 4 bits and the control range is 3 dB.
The gain setting of the R, G and B channel. During
switch on this register is loaded with the preset gain
setting of subaddress 23H to 25H and when necessary
it will be adapted by the CCC control loop. These
registers have a resolution of 7 bits. The control of the
gain setting is illustrated in table 44.
2003 Nov 11
B5
B4
B3
B2
B1
B0 max 64
CL
B3
B2
B1
B0
CCC-gain
B6
B5
B4
B3
B2
B1
B0 max 126
R(GB)-gain B6
B5
B4
B3
B2
B1
B0 max 126
max 60
The setting of the gain registers of the 3 channels can be

stored during switch off and can be loaded again during
switch-on so that the drive conditions are maintained.
When required the operation of the CCC system can be
changed into a one-point black current system. The
switching between the 2 possibilities is realised by means
of the EGL bit (EGL = 0) in subaddress 42H. When used
as one-point control loop the system will control the black
level of the RGB output signals to the low reference
current and not on the cut off point of the cathode. In this
way spreads in the picture tube characteristics will not be
taken into account. In this condition the settings of the
white point control registers (subaddress 20H - 22H) and
the cathode drive level bits (CL3 - CL0 in subaddress
42H) are added to the settings of the RGB preset gain
registers (subaddress 23H - 25H).
A black level off-set can be made with respect to the level
which is generated by the black current stabilization
system. In this way different colour temperatures can be
obtained for the bright and the dark part of the picture. The
black level control is active on the Red and the Green
output signal. It is also possible to control the black level of
the Blue and the Green output signal (OFB bit = 1).
In the Vg2 adjustment mode (AVG = 1) the black current
stabilization system checks the output level of the 3
channels and indicates whether the black level of the
highest output is in a certain window (WBC-bit) or below or
above this window (HBC-bit). This indication can be read
from the status byte 01 and can be used for automatic
adjustment of the Vg2 voltage during the production of the
TV receiver. During this test the vertical scan remains
active so that the indication of the 2 bits can be made
visible on the TV screen.
The control circuit contains a beam current limiting circuit
and a peak white limiting circuit. The control is realised by
means of a reduction of the contrast and brightness control
settings. The way of control (first contrast and then
brightness or contrast and brightness in parallel) can be
chosen by means of the CBS bit (subaddress 44H). The
peak white level is adjustable via the I2C-bus.
106
CONFIDENTIAL

To prevent that the peak white limiting circuit reacts on the
high frequency content of the video signal a low-pass filter
is inserted in front of the peak detector. The circuit also
contains a soft-clipper which prevents that the high
frequency peaks in the output signal become too high. The
difference between the peak white limiting level and the
soft clipping level is adjustable via the I2C-bus in a few
steps.
UOCIII series
current ensures that the picture tube capacitance is
discharged. During the switch-off period the vertical
deflection can be placed in an overscan position so that
the discharge is not visible on the screen.
A wide blanking pulse can be activated in the RGB outputs
by means of the HBL bit in subaddress 43H. The timing of
this blanking can be adjusted by means of the bits WBF/R
bits in subaddress 26H.
During switch-off of the TV receiver a fixed beam current

is generated by the black current control circuit. This
I2C-BUS USER INTERFACE DESCRIPTION OF THE VIDEO PROCESSOR
The UOCIII series is fully controlled via the I2C-bus. Control is exercised by writing data to one or more internal registers.
Status information can be read from a set of info registers to enable the controlling microcontroller determine whether
any action is required.The device has an I2C-bus slave transceiver, in accordance with the fast-mode specification, with
a maximum speed of 400 kbits/s. Information concerning the I2C-bus can be found in brochure I2C-bus and how to use
it (order number 9398 393 40011). To avoid conflicts in a real application with other ICs providing similar or
complementary functions, there are two possible slave addresses available which can be selected by the SVM pin (pin
65).
Possible slave address
SVM PIN
SLAVE ADDRESS A6 TO A0
scavem application
1000101
tied to 5 volts
1000111
The device will not respond to a general call on the I2C-bus, i.e. when a slave address of 0000000 is sent by a master.
Write registers
Each address of the address space (see below) can only be written.
Correct operation is not guaranteed if registers in the range $FB to $FF will be addressed!
Overview address space
ADDRESS
WORDS
WORDLENGTH
DESCRIPTION
$00 to $29
42 words
1 byte
I2C addresses enabled and

usable
$2A to $2E
Not used
$2F to $4A
28 words
1 byte

usable
$4B to $FA
Not used
$FB to $FF
5 words
1 byte
I2C addresses enabled not

usable
Read registers
The output registers of the TV processor are only available via auto-increment mode, no address can be used and all
registers must be read.
2003 Nov 11
107
CONFIDENTIAL

UOCIII series
DESCRIPTION OF THE I2C-BUS SUBADDRESSES

Table 45 Inputs TV processor
FUNCTION
SUBADDR
(HEX)
Spare
Spare
Spare
Volume control (L)
Volume control R (2)
Horizontal shift (HS)
Horizontal parallelogram
Horizontal bow
Vertical linearity
Vertical scroll
EW width (EW) (1)
EW parabola/width (PW) (1)
EW upper corner parabola(1)
EW lower corner parabola(1)
EW trapezium (TC) (1)
Vertical slope (VS)
Vertical amplitude (VA)
S-correction (SC)
Vertical shift (VSH)
Vertical zoom (VX)
Off-set IF demodulator
AGC take-over
Spare
Black level offset R
Black level offset G
Peaking
White limiting
Brightness
Saturation
Contrast
Base-band tint control
Spare
White point R
White point G
White point B
PGR - Preset Gain Red
PGG - Preset Gain Green
PGB - Preset Gain Blue
Timing of wide blanking (1)
Hue for NTSC
IF Preset Value 1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
2003 Nov 11
DATA BYTE
D7
D6
0
0
0
0
0
0
0
A6
0
A6
0
0
0
0
0
0
VL1
VL0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PF1
PF0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LPG
A6
0
A6
0
A6
WBF3 WBF2
0
0
0
EPVI
D5
D4
D3
POR
D2
0
0
0
0
0
0
0
0
0
0
0
0
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
0
0
0
0
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
SOC1 SOC0
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
0
0
0
0
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
A5
A4
A3
A2
WBF1 WBF0 WBR3 WBR2
A5
A4
A3
A2
A5
A4
A3
A2
108
CONFIDENTIAL
D1
D0
Value
0
0
0
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
0
A1
A1
A1
A1
A1
A1
A1
A1
0
A1
A1
A1
A1
A1
A1
WBR1
A1
A1
0
0
0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
0
A0
A0
A0
A0
A0
A0
A0
A0
0
A0
A0
A0
A0
A0
A0
WBR0
A0
A0
00
00
00
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
00
20
20
20
08
20
20
20
20
00
00
00
00
00
00
00
88
00
00

FUNCTION
IF Preset Value 2
Spare
Spare
Spare
Spare
Spare
Vision IF 0
Vision IF 1
Vision IF 2
Sound 0
Sound 1
Sound 2
Sound 3
Audio selection 0
Audio selection 1
Video selection 0
Video selection 1
Video selection 2
Colour decoder 0
Colour decoder 1
Synchronisation 0
Synchronisation 1
Synchronisation 2
Deflection 0
Deflection 1 / Control 0
Control 1
Control 2
Control 3
Control 4
Control 5
Peaking
SVM 0
SVM 1
Miscellaneous 1
Miscellaneous 2
UOCIII series
DATA BYTE
SUBADDR
(HEX)
D7
D6
D5
D4
D3
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
0
0
0
0
0
0
0
0
CMSS
0
AGN
0
0
0
0
CS1A
0
0
CM3
SBO1
SDC
WBI
0
VSD
DEFL
INTF
IE3
GAM
BKS
OFB
0
0
DSS
0
0
0
0
0
0
0
0
IFD
STM
VA1
NRR
AM
0
FMS
HPVC
E2D(3)
CS1B
0
0
CM2
SBO0
HP2
RED
VGM1
OSVE
SVMA
EGL
IE2
TFR
BSD
HCT
0
CRA0
0
DISG
0
A5
0
0
0
0
0
IFA
AGCM
VA0
0
SM1
AVLE
AVLM
SPT
SAS2
CS1C
0
VDXEN
CM1
CHSE1
FOA
FSL
VGM0
DFL
MVK
SLG0
DINT
CLD
AAS
FINM
RPA1
SPR2
0
DDLE
0
A4
0
0
0
0
0
IFB
IFLF
VAI
DSG
SM0
QSS
0
0
SAS1
CS1D
CFA0
VDX
CM0
CHSE0
FOB
OSO
LED
XDT
0
AKB
YC
CBS
DSK
FIN
RPA0
SPR1
0
CSY
0
A3
0
0
0
0
0
IFC
GD
IFS
RDS
FMD
BPB
ESSIF
SMLS
SAS0
INA
CV2
YD3
MAT
CLO
POC
FORF
SSL
SBL
0
CL3
YUV2
OUV
WS1
SLG1
RPO1
SPR0
VMA1
SWO1
BPYD
POR
D2
D1
D0
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VSW
MOD
AFN
AGC1 AGC0
FFI
IFO2
IFO1
IFO0
MONO FMWS1 FMWS0
FMC
FMB
FMA
FMR
FMI
AVL(4)
CMCA BPB2 AMLOW
SO2
SO1
SO0
HPO2 HPO1
HPO0
INB
INC
IND
SVO1 SVO0
SYS
YD2
YD1
YD0
MUS
ACL
CB
DTR
BPS
FCO
STB
HTXT
VID
FORS
DL
NCIN
SD2
SD1
SD0
AVG
EVG
HCO(1)
0
FBC
EVB
CL2
CL1
CL0
YUV1 YUV0
HBL(1)
PWL
RBL
RGBL
WS0
BLS
TUV
BLBG
LLB
DSA
RPO0 COR1
COR0
SVM2 SVM1
SVM0
VMA0 SMD1
SMD0
CMB2 CMB1
CMB0
0
0
0
Value
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Note
1. These functions are only available when the East-West drive output is active (AVLE = 0).
2. This function is available only in the Stereo and AV Stereo versions.
3. Only available in the Mono versions
4. The AVL function can only be activated when a capacitor is connected to the EW output pin (AVLE = 1) or to the
subcarrier output pin (via the bits CMB2-CMB0).
2003 Nov 11
109
CONFIDENTIAL

UOCIII series
Table 46 Outputs TV-processor

DATA BYTE
FUNCTION
SUBADDR
D7
D6
D5
D4
D3
D2
D1
D0
00
POR
SID
LOCK
SL
CD3
CD2
CD1
CD0
01
XPR
NDF
FSI
IVW
WBC
HBC
BCF
COMB
02
SUP
AGC
IN3
IN2
SUPR
FMW
FML
03
IVWF
SN2
SN1
SN0
YCD
04
AFC7
AFC6
AFC5
AFC4
AFC3
AFC2
AFC1
AFC0
05
GLOK
RG6
RG5
RG4
RG3
RG2
RG1
RG0
06
PTW
GG6
GG5
GG4
GG3
GG2
GG1
GG0
07
BG6
BG5
BG4
BG3
BG2
BG1
BG0
08-09
Output status bytes
0A
DFL4
DFL3
DFL2
DFL1
DFL0
0B
DISC9
DISC8
DISC7
DISC6
DISC5
DISC4
DISC3
DISC2
0C-0F
Explanation input control data TV-processor
Table 50 Horizontal bow
Table 47 Volume control (L and R)

DAC SETTING
0
7F
DAC SETTING
CONTROL
screen top and bottom 1.0 s delayed

with respect to centre
20
no correction
3F
screen top and bottom 1.0 s

advanced with respect to centre
CONTROL
attenuation 70 dB
no attenuation
Table 48 Horizontal shift

DAC SETTING
CONTROL
2 s
20
3F
+2 s
Table 51 Upper/lower vertical linearity control
Table 49 Horizontal parallelogram

DAC SETTING
CONTROL
screen top 0.75 s delayed and

screen bottom 0.75 s advanced with
respect to centre
20
3F
2003 Nov 11
VL1
VL0
SETTING
full-screen vertical linearity (see

Table 52)
only lower vertical linearity
only upper vertical linearity
Table 52 Vertical linearity (VL1/VL0 setting 0/0)

DAC SETTING
no correction
screen top 0.75 s advanced and
screen bottom 0.75 s delayed with
respect to centre
CONTROL
ratio bottom/top of screen: 117%
20
no correction
3F
ratio bottom/top of screen: 85%
110
CONFIDENTIAL

Table 53 Vertical scroll (at zoom setting of 3FH,
percentage of nominal visible amplitude); note 1
DAC SETTING
UOCIII series
Table 59 Vertical amplitude
DAC SETTING
CONTROL
CONTROL
amplitude 80%
picture shift 18%
20
amplitude 100%
20
no picture shift
3F
amplitude 120%
3F
picture shift +18%

Table 60 S-correction
Note
DAC SETTING
1. The vertical scroll function is active only in the expand

mode of the vertical zoom, i.e at a DAC position which
is larger than 10H.
Table 54 EW width
DAC SETTING
0
3F
CONTROL
3F
correction 25%
CONTROL
shift 5%
20
no correction
3F
shift +5%
CONTROL
output current 0 A
Table 62 Vertical zoom
output current 440 A at top and

bottom of screen
DAC SETTING
Table 56 EW upper/lower corner parabola

DAC SETTING
CONTROL
output current +262 A (+55%)
11
output current 0 A
3F
output current 262 A (55%)
DAC SETTING
CONTROL
output current at top of screen 100 A

lower that at bottom
20
no correction
3F
output current at top of screen 100 A

higher than at bottom
amplitude 75%
19
amplitude 100%
3F
amplitude 138%
DAC SETTING
0
negative correction
20
no correction
3F
positive correction
1. This control is intended to correct for DC offset in the

IF-PLL to improve the S/N ratio of the intercarrier
sound signal.
Table 64 AGC take-over
DAC SETTING
CONTROL
correction 20%
20
no correction
3F
correction +20%
CONTROL
Note
Table 58 Vertical slope

DAC SETTING
CONTROL
Table 63 Offset IF demodulator
Table 57 EW trapezium
2003 Nov 11
no correction
DAC SETTING
output current 0 A
Table 55 EW parabola/width
3F
correction 10%
0E
Table 61 Vertical shift
output current 700 A
DAC SETTING
CONTROL
CONTROL
tuner take-over at IF input signal of

0.4 mV
3F
tuner take-over at IF input signal of

80 mV
111
CONFIDENTIAL

Table 70 Brightness control
Table 65 Black level offset R/V - G/U;

DAC SETTING
UOCIII series
CONTROL
DAC SETTING
CONTROL
100 mV (R/G), -50mV (U/V)
correction 0.4 V
20
no offset
20
no correction
3F
+100 mV (R/G), +50mV (U/V)
3F
correction +0.4 V
Note
Table 71 Saturation control
1. Offset DAC can be used for offset correction on RG or

on UV. The range for both cases is different.
DAC SETTING
0
Table 66 Peaking centre frequency and delay

CENTRE FREQUENCY
DELAY
CONTROL
colour off (52 dB)
17
saturation nominal
3F
saturation +300%
PF1
PF0
2.7 MHz
190 ns
3.1 MHz
160 ns
3.5 MHz
143 ns
DAC SETTING
4.0 MHz
125 ns
RGB amplitude 14 dB
20
RGB amplitude nominal
3F
RGB amplitude +6 dB
Table 72 Contrast control
Table 67 Peaking control (overshoot in direction black)

DAC SETTING
CONTROL
depeaking (overshoot 18%)
CONTROL
Table 73 Base-band tint control

DAC SETTING
0D
no peaking
3F
overshoot 75%
Table 68 Soft clipping level

VOLTAGE DIFFERENCE BETWEEN
SOFT CLIPPING AND PWL
CONTROL
30
20
3F
+30
SOC1
SOC0
0% above PWL level
SETTING
5% above PWL level
10% above PWL level
20
no correction
soft clipping off
3F
gain +3 dB
Table 69 Peak White Limiting; note 1

DAC SETTING
Table 74 White point R/G/B

CONTROL
gain 3 dB
Table 75 RGB gain preset; note 1
CONTROL
LPG
CONDITION
00
0.40 VBL-WH
normal operation
0F
0.60 VBL-WH
preset gain setting is loaded
Note
Note
1. CVBS/Y input signal at which the Peak White Limiting

is activated (max contrast setting). Nominal input
signal: 0.7 VBL-WH.
1. The gain of the RGB amplifiers is controlled by means

of 7-bit DACs. The value of the gain is dependent on
the setting of the White Point RGB registers
(subaddress 20H - 22H), the setting of the Cathode
drive level (CL3 - CL0 in subaddress 42H) and the
CCC loop control. During switch-on of the TV receiver
the preset value of the gain setting has to be loaded.
2003 Nov 11
112
CONFIDENTIAL

Table 76 Preset gain setting for R, G and B, note 1
SETTING
UOCIII series
Table 80 PLL demodulator frequency setting
CRT DRIVE VOLTAGE
IFD
IFA
IFB
IFC
IF FREQUENCY
45 VP-P
58.75 MHz
40
90 VP-P
45.75 MHz
7F
180 VP-P
38.90 MHz
38.00 MHz
33.40 MHz
43.008 MHz
33.90 MHz
b) The cathode drive setting (CL3-CL0) is set to 0
49.152 MHz
c) The contrast setting is 3 dB
external reference carrier
Note
1. These values are valid in the following condition:
a) The white point setting for the R, G and B channel
is set to 0
d) The gain of the RGB output amplifiers is 80
Table 81 Video mute

VSW
Table 77 Timing of wide blanking

WBF/R3-0
SETTING
3.5 / 7.8 s
0F
5.9 / 10.2 s
CONTROL
20
3F
+40
normal operation
IF-video signal switched off
MOD
40
Table 82 Modulation standard
Table 78 Hue control for NTSC

HUE
STATE
MODULATION
negative
positive
Table 83 AFC switch

AFN
Table 79 IF PLL oscillator preset value; note 1

EPVI
CONDITION
normal operation
preset value is loaded
MODE
normal operation
AFC not active
Table 84 Search tuning mode

STM
Note
1. During mix-down of DVB signals with an external
reference carrier (CMB2/CMB1/CMB0 = 1/0/0) the
frequency of the oscillator can be defined by means of
the settings of the IF Preset Value registers
(subaddress 28H and 29H).
MODE
normal operation
reduced sensitivity of video indent circuit
Table 85 Internal or external AGC mode

AGCM
MODE
internal mode of DVB AGC
external mode for DVB AGC
Table 86 Calibration of IF PLL demodulator

IFLF
2003 Nov 11
MODE
calibration system active
calibration system not active
113
CONFIDENTIAL

Table 87 Group delay on CVBS1 signal
GD
UOCIII series
Table 90 Selection of sync input signal for the video ident
circuit
CONDITION
CMSS
no group delay correction
group delay correction switched on
CONDITION
input from sync separator in IF ident circuit
input from main sync separator
Table 88 IF AGC speed

AGC1
AGC0
0.7 norm
Table 91 Video output signal amplitude
AGC SPEED
VA1
VA0
OUTPUT SIGNAL AMPLITUDE
norm
no correction
3 norm
amplitude 5%
6 norm
amplitude +5%
Table 92 System I output signal amplitude correction
Table 89 Fast filter IF-PLL

FFI
VAI
CONDITION
MODE
normal time constant
no correction
increased time constant
amplitude +12%
Table 93 IF sensitivity
IFS
IF SENSITIVITY
normal
reduced
Table 94 IF output selection, note 1

STEREO and AV STEREO versions MONO versions
IFO2 IFO1 IFO0
DESCRIPTION
PIN 43
PIN 44
PIN 43
mute
mute
mute
high ohmic output
IFOUT
mute
IFOUT
IF output without sound trap / group delay
IFOUT + sndtrap mute
IFOUT + sndtrap IF output with sound trap / group delay
DVBP / FMRO
DVBN / FMRO
DVBSE / FMRO DVB output or FM radio output
DVBSE / FMRO
mute
mute
DVBSE / FMRO
black DC
black DC
black DC
black level DC output
Note
1. The result of this setting of the IFO2-IFO0 bits is also dependent on the setting of the IF-PLL frequency (IFA-IFC in
subaddress 2FH) and the FMR bit (subaddress 34H). The following conditions are possible:
a) Analogue TV mode (required settings: FMR = 0 and IFA/IFB/IFC = 000/001/010/011/100/110). In this mode the
valid IFO2-IFO0 settings are: 000, 001, 010 and 111.
b) DVB mode (required settings: FMR = 0 and IFA/IFB/IFC = 101 or 111). In this mode the valid IFO2-IFO0 settings
are: 000, 011, 100, 110 and 111. The mixed-down DVB signals are now available at the outputs (DVBP/N
indicates a balanced output, DVPSE a single ended output).
c) FM radio mode (required settings: FMR = 1 and IFA/IFB/IFC = 101 or 111). The valid IFO2-IFO0 settings are the
same as for the DVB mode.
2003 Nov 11
114
CONFIDENTIAL

Table 95 No Red reduction during blue stretch
NRR
UOCIII series
Table 102 Sound mute
CONDITION
SM1
SM0
CONDITION
red reduction active
mute off
not active
sound enhancer; note 1
mute on
Table 96 Gain from audio inputs to audio outputs

Note
DSG
GAIN
0 dB
+6 dB
1. The sound enhancer is active only during FM sound. It

limits the noise which is generated by the digital
acquisition circuit. For AM sound only the positions
mute off and mute on should be used.
Table 97 Radio Data System (RDS)

Table 103FM demodulator at 10.7 MHz
RDS
CONDITION
not active
demodulated audio signal supplied to RDS

decoder
Table 98 Activate mono-FM demodulator (in stereo

versions)
MONO
0
1
FMD
MODE
frequency FM demodulator determined by the

bits FMA, FMB and FMC
frequency FM demodulator 10.7 MHz
Table 104Centre frequency FM demodulator/sound trap

FMC FMB FMA
MODE
FM DEMOD.
SOUND TRAP
mono-FM demodulator not active
5.5 MHz
5.5 MHz
mono-FM demodulator active
6.0 MHz
6.0 MHz
4.5 MHz
4.5 MHz
6.5 MHz
6.5 MHz
5.74 MHz
5.5 MHz
Table 99 Window select for FM demodulator

FMWS1 FMWS0
WINDOW
100 kHz
7.90 MHz
225 kHz
4.72 MHz
4.5 MHz
9.60 MHz
450 kHz
900 kHz
Table 105Enable AVL function on East-West output pin
Table 100 Gain FM demodulator

AGN
0
1
AVLE
MODE
normal operation
gain +6 dB
CONDITION
East-West functionality active
AVL functionality active
Table 106 Mode of Quasi Split Sound amplifier

Table 101Selection QSS out or AM out
AM
MODE
QSS output selected
AM output selected
2003 Nov 11
QSS
MODE
QSS amplifier not active, input of sound PLL

connected to vision IF amplifier output
QSS amplifier active, output connected to
QSSO or to input sound PLL (via FMI bit)
115
CONFIDENTIAL

Table 115 Bypass sound bandpass filter section 2
Table 107 Bypass of sound bandpass filter

BPB
UOCIII series
CONDITION
BPB2
MODE
normal operation
bandpass filter active
sound bandpass filter bypassed
bandpass filter bypassed
Table 116 Audio output signal for AM sound
Table 108 Auto Volume Levelling

AVL
MODE
AMLOW
CONDITION
not active
normal output signal amplitude
active
output signal amplitude reduced with 6 dB
Table 117 Head phone volume control
Table 109 FM radio function enabled

FMR
MODE
HPVC
CONDITION
TV mode
volume control not active
FM radio mode
volume control active
Table 118 Sync Performance Trick mode
Table 110 Connection of output of QSS amplifier

FMI
0
1
MODE
SPT
MODE
influence S/N detector on phi1 loop disabled
influence S/N detector on phi1 loop enabled
output connected to QSSO output

output connected to sound PLL circuit
Table 111 FM mono demodulator sensitivity

FMS
Table 119 Sound mute loudspeaker output
MODE
normal operation
reduced sensitivity
SMLS
Table 112 Maximum audio gain when AVL is active

AVLM
normal gain
maximum gain
Table 113 SSIF input pin selection

ESSIF
MODE
SSIF at pin 33
SSIF at pin 53
Table 114 Activate complete mono channel (in stereo

versions)
CMCA
normal operation
output muted
Table 120 Audio select for SCART/CINCH output, note 1
MODE
CONDITION
SO2
SO1
SO0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
AUDOUTSL/R
FM MONO / AM
AUDIOIN2
AUDIOIN3
AUDIOIN4
AUDIOIN5
fixed output of Audio DSP,
note 2
vol. contr. output Audio DSP,
note 2
mute
Note
MODE
stereo mode
1. These bits are only valid for stereo and AV stereo

versions
mono LF path only HP left
2. Only valid in versions with Audio DSP
2003 Nov 11
116
CONFIDENTIAL

Table 121 Selection of audio output signal on AUDEEM
pin, note 1 (Mono versions)
E2D
UOCIII series
Table 124 CVBS/PIP output
CS1A CS1B CS1C CS1D
MODE
SELECTED SIGNALS
mute
deemphasis (front-end audio available)
CVBS1 (internal from IF)
selected audio signal available
CVBS2
Note
Y2 + C3
1. This function can be activated only when the MOD bit

is 0.
CVBS3
Y3 + C3
CVBS4
Y4 + C4
CVBSX; note 1
YX + CX; note 1
Table 122 Audio select for Audio DSP input

SAS2
SAS1
SAS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SELECTION
FM MONO / AM
AUDIOIN2
AUDIOIN3
AUDIOIN4
AUDIOIN5
spare
spare
mute
Table 125 Video input selection
Table 123 Audio select; note 1

HPO2
HPO1
HPO0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
AUDOUTHPL/R
FM MONO / AM
AUDIOIN2
AUDIOIN3
AUDIOIN4
AUDIOIN5
fixed output of Audio DSP,
note 2
vol. contr. output Audio DSP,
note 2
mute
INA
INB
INC
IND
CVBS2
Y2/C3
CVBS3
Y3/C3
CVBS4
Y/C4
CVBSX; note 1
Y/CX; note 1
Notes for table 124 and 125

1. This command is valid only when the CVBSX (Y/CX)
function is activated via the YC-bit.
Table 126 Comb filter mode
CFA0
Note
1. The function of the HPO2/0 bits depends on the IC
version. For stereo versions with Audio DSP these bits
control the input signal selection for the Headphone
channel. For stereo versions without Audio DSP and
for mono versions they control the input signal
selection for the speaker output channel.
COMB FILTER
adaptive 4H/2H comb filter for PAL/NTSC
comb filter off
Table 127 CVBS2 input signal selection

CV2
2. Only valid in versions with Audio DSP
2003 Nov 11
SELECTED SIGNALS
MODE
CVBS2 input directly selected
CVBS2 input signal is supplied sound trap

and group delay correction circuit. The
selection of this signal is realised by means of
the CS1A-D and INA-D bits (setting 0001).
117
CONFIDENTIAL

Table 128 Function of IFVO/SVO/CVBSI pin
UOCIII series
Table 133 Colour decoder mode, note 1
SVO1
SVO0
PIN FUNCTION
wrong function, do not use
PAL/NTSC/SECAM
selected CVBS available at output
PAL/SECAM
pin used as CVBS input; note 1
PAL
wrong function, do not use
NTSC
SECAM
PAL/NTSC
PAL
NTSC
B
ABCD
CM3 CM2 CM1 CM0
Note
1. When this function is selected the setting of the CV2
bit is neglected. The signal is supplied to the sound
trap and group delay correction circuit. The selection
of this signal is realised by means of the CS1A-D and
INA-D bits (setting 0001).
Table 129 Active input for sync separator, note 1
SYS
MODE
sync coupled to YSYNC input
sync coupled to selected CVBS/Y input
Note
1. Sync coupled to the selected CVBS input should only
be used when the external RGB signal contains no
sync pulse.
Table 130 Control of coupling between vision IF amplifier
and synchronisation circuit
VDXEN
DECODER MODE
FREQ
PAL/NTSC/SECAM(2)
PAL/NTSC
PAL
NTSC
C
(2)
PAL/NTSC (Tri-Norma)
PAL/NTSC
PAL
NTSC
BCD
Note
1. The decoder frequencies for the various standards are
obtained from an internal clock generator which is
synchronised by a 24.576 MHz reference signal which
is obtained from the -Controller clock generator.
a) The nominal standard frequencies are:
MODE
coupling controlled by the input signal

selection bits (INA-IND)
coupling controlled by the VDX bit
b) A: 4.433619 MHz
c) B: 3.582056 MHz (PAL-N)
d) C: 3.575611 MHz (PAL-M)
e) D: 3.579545 MHz (NTSC-M)
Table 131 Coupling between vision IF amplifier and

synchronisation circuit
VDX
2. In the auto modes (CM3-CM0 setting 1000 and 1100)

PAL with frequency D and NTSC with frequencies B
and C are not possible.
MODE
the circuits are coupled
the circuits are not coupled
The nominal oscillator frequency may have a slightly

different value (see also Table 249)
Table 134 PAL-SECAM/NTSC matrix

Table 132 Y-delay adjustment
MAT
YD0 to YD3
FSC = 4.43 MHz
FSC = 3.58 MHz
YD3
YD3 220 ns +
YD3 280 ns +
YD2
YD2 110 ns +
YD2 140 ns +
YD1
YD1 55 ns +
YD1 70 ns +
YD0
YD0 30 ns
YD0 30 ns
2003 Nov 11
MATRIX POSITION
adapted to standard
PAL matrix
Table 135 NTSC matrix

MUS
MATRIX POSITION
Japanese matrix
USA matrix
118
CONFIDENTIAL

Table 136 Automatic colour limiting
ACL
UOCIII series
Table 143 Forced Colour-On
COLOUR LIMITING
FCO
CONDITION
not active
off
active
on
Table 137 Chroma bandpass centre frequency

CB
CENTRE FREQUENCY
FSC
1.1 FSC
Table 144 Setting duty cycle of horizontal drive signal,

note 1 on page 119
SDC
Table 138 SECAM B-Y black level offset adjustment

OFFSET
CONDITION
duty cycle 55:45
duty cycle 60:40
Note
SBO1
SBO0
+ 4 kHz
+ 1 kHz
1. The setting of the duty cycle of the horizontal drive

signal can only be adapted when the IC is in the
stand-by mode (STB = 0)
1 kHz
4 kHz
Table 145 Synchronization of OSD/TEXT display
-CONTROLLER COUPLED TO
HP2
Table 139 PAL/NTSC ident sensitivity (burst amplitude at

strong signal (typical value)
1 loop
2 loop
CHSE1
CHSE0
SENSITIVITY
34 dB
37 dB
FOA
FOB
41 dB
normal
46 dB
slow
OSD mode (very slow)
fast
Table 146 Phase 1 (1) time constant
Table 140 Centre frequency of cloche filter

CLO
MODE
CENTRE FREQUENCY
4.29 MHz
4.33 MHz
Table 147 Synchronization mode

POC
Table 141 Chroma trap mode

DTR
MODE
active
not active
MODE
Table 148 Stand-by
single chroma trap
dual chroma trap, more suppression but less

bandwidth
STB
Table 142 Bypass of chroma base-band delay line

BPS
DELAY LINE MODE
active
bypassed
2003 Nov 11
MODE
stand-by
normal
Table 149 Source of CSO signal for teletext decoder

HTXT
MODE
CSO derived from dedicated sync separator
CSO derived from main sync separator
119
CONFIDENTIAL

Table 150 Mode of 1 loop
UOCIII series
Table 157 Vertical divider mode
VID
MODE
NCIN
VERTICAL DIVIDER MODE
1 loop dependent on the video ident system
normal operation
1 loop only dependent on FOA/FOB or POC

bits
switched to search window
Table 158 Function of VGUARD/SWIO pin

Table 151 Increased wide blanking
WBI
MODE
VGM1
VGM0
FUNCTION
vertical guard
normal mode
wide blanking range adapted to Double

window mode
vertical guard combined with LED

drive output
switch output (0 - 5 V)
input port, detector output via NDF

bit
Table 152 Disable reference oscillator check in the SUP

output bit (see also Table 234)
RED
Table 159 Mode of LED driver / switch output
CONDITION
reference oscillator check enabled
LED
reference oscillator check disabled
LED drive off / switch output HIGH
LED drive on / switch output LOW
Table 153 Forced slicing level for vertical sync

FSL
Table 160 Slicing level sync separator
SLICING LEVEL
slicing level dependent on noise detector
fixed slicing level of 60%
SSL
Table 154 Switch-off in vertical overscan

OSO
Switch-off undefined
Switch-off in vertical overscan
SLICING LEVEL
50%
30%, direction top sync
Table 161 Source selection for video identification
MODE
MODE
Table 155 Forced field frequency

FORF
FORS
FIELD FREQUENCY
auto (60 Hz when line not in sync)
60 Hz
keep last detected field frequency
auto (50 Hz when line not in sync)
SD2
SD1
SD0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
VIDEO INPUT
selected input signal (via
INA-IND bits)
CVBS2
CVBS3/Y3
CVBS4/Y4
G/Y-2 (CVBS/Y-X)
G/Y-3
Table 162 Vertical scan disable

Table 156 Interlace
DL
VSD
STATUS
interlace
de-interlace
2003 Nov 11
SETTING
normal operation
vertical scan switched off
120
CONFIDENTIAL

Table 163 Black current measuring lines in overscan (for
vertical zoom setting < 1)
OSVE
UOCIII series
Table 170 Read-out deflection timer
DEFL
MODE
normal operation
measuring lines in overscan
MODE
read-out disabled
read-out enabled
Table 171 Scan Velocity Modulation output signal (1)

Table 164 Disable flash protection
DFL
SVMA
MODE
flash protection active
flash protection disabled
OUTPUT SIGNAL AMPLITUDE
600 mVP-P
1200 mVP-P
Note
Table 165 X-ray detection
1. Input signal: 1 MHz with an amplitude of 350 mVP-P
XDT
MODE
protection mode, when a too high EHT is

detected the receiver is switched to stand-by
and the XPR-bit is set to 1
Table 172 Macro Vision Keying

MVK
detection mode, the receiver is not switched

to stand-by and only the XPR-bit is set to 1
MODE
Macro vision keying not active
Macro Vision keying active
Table 173 Fixed beam current switch-off

Table 166Service blanking
SBL
FBC
SERVICE BLANKING MODE
off
on
MODE
switch-off with blanked RGB outputs
switch-off with fixed beam current
Table 174 Extended vertical blanking

Table 167 Adjustment Vg2 voltage
AVG
EVB
MODE
normal operation
Vg2 adjustment (WBC and HBC bits in output

byte 01 can be read)
SETTING
normal vertical blanking
extended vertical blanking in the upper and

lower part of the picture; see also Fig. 82
Table 175 Amplitude/polarity of YUV interface signal

Table 168 Enable vertical guard (RGB blanking)
EVG
INTF
VERTICAL GUARD MODE
not active
active
signal according to YPRPB standard; note 1
signal according to YUV standard; note 2
1. YPRPB input: (colour bar 100% saturation):

Y = +1.0 VP-P; PR = +0.7 VP-P; PB = +0.7 VP-P.
TRACKING MODE
EHT tracking only on vertical
EHT tracking on vertical and EW
2003 Nov 11
Note
Table 169 EHT tracking mode

HCO
INTERFACE SIGNAL AMPLITUDE
2. YUV input: (colour bar 75% saturation):

Y = 1.4 VP-P; U = 1.33 VP-P; V = 1.05 VP-P.
121
CONFIDENTIAL

Table 176 Enable gain loop in the CCC system
EGL
UOCIII series
Table 179 Cathode drive level
MODE
CL3 - CL0
CONTROL
control loop not active
gain 3 dB
control loop active
nominal value
gain +3 dB
Table 177 Selection high current in CCC system

Table 180 Enable fast blanking of RGB/YPRPB-3 input
SLG1
SLG0
MODE
current level 220 A
IE3
current level 150 A
not active
current level 280 A
active
current level 190 A
FAST BLANKING
Table 181 Enable fast blanking of RGB/YPRPB-2 input

Table 178 Black current stabilization
AKB
IE2
MODE
active
not active
FAST BLANKING
not active
active
Table 182 Enable digital interface

DINT
MODE
not active
active
Table 183 RGB/YUV/YPRPB switching options

YC
YUV2 YUV1 YUV0
RGB/YUV/YPRPB-2 INPUT OR
YUV/YPRPB INTERFACE OR
CVBS (Y/C) INPUT
RGB/YPRPB-3 INPUT
INPUT WITH
HIGHEST
PRIORITY (5)
0
0
0
0
0
0
0
0
1
0
1
0
RGB with fast insertion

RGB with fast insertion; note 1

RGB-3
interface; note 2
YUV with fast insertion; notes 1 + 3 YUV-2
0
0
0
0
0
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0

YPRPB input; note 4
YPRPB input; note 4
YPRPB input; note 4
YPRPB input; note 4
YPRPB input; note 4
YPRPB input; notes 1+ 4

YPRPB input; notes 1 + 4
RGB with fast insertion; note 1
interface; note 2
YUV with fast insertion; notes 1 + 3
CVBS-X or Y/C-X input
CVBS-X or Y/C-X input
RGB-3
YPRPB-3
RGB-2
YUV-2
RGB-3
YPRPB-3
Notes
1. In this position the V output is changed to general purpose switch output (SWO1). This output is controlled by the
SWO1 bit in subaddress 4AH.
2. The amplitude and polarity of the input and output signals are determined by the setting of the INTF bit
3. YUV input: (colour bar 75% saturation): Y = 1.4 VP-P; U = 1.33 VP-P; V = 1.05 VP-P.
4. YPRPB input: (colour bar 100% saturation): Y = +1.0 VP-P; PR = +0.7 VP-P; PB = +0.7 VP-P.
5. When both inputs are activated (by means of IE2/IE3 or fast blanking) the input with the highest priority is dependent
on the selected option.
2003 Nov 11
122
CONFIDENTIAL

Table 192 Blanking of RGB outputs
Table 184 RGB blanking mode

HBL
UOCIII series
MODE
RGBL
CONDITION
normal blanking (horizontal flyback)
normal operation
wide blanking
RGB outputs blanked continuously
Table 193 Black stretch
Table 185 Gamma control

GAM
CONDITION
BKS
BLACK STRETCH
not active
off
active
on
Table 186 DC transfer ratio of luminance signal

TFR
Table 194 Black Stretch Depth (A-A in Fig. 72)
TRANSFER RATIO
BSD
MODE
no black level shift due to video content
15 IRE
black level shift of 10 IRE for complete white

picture
30 IRE
Table 195 Black area to switch off the black stretch

Table 187 Delay of clamp pulse
CLD
AAS
DELAY
normal timing
extra delay of 400 ns
MODE
10% back ground needed
20% back ground needed
Table 196 Dynamic skin control on/off

Table 188 Control sequence of beam current limiting
CBS
MODE
0
1
normal operation (contrast brightness)

control on contrast and brightness in parallel
Table 189 Off-set control on UV input signals

OUV
DSK
off-set control on R/G output signals
off-set control on U/V input signals
Table 190 Peak White limiting

PWL
0
peak white limiting circuit not active
peak white limiting circuit active
RBL
RGB BLANKING
not active
active
2003 Nov 11
off
on
EXPANSION (1)
APL (2)
WS1
WS0
0%
6%
17%
8%
25%
12%
28%
Note
MODE
Table 191 RGB blanking
Table 197 Gamma control and white stretch settings
MODE
MODE
1. This figure indicates the maximum increase of the gain

in the lower part of the characteristic (slope of the
curve, see Fig. 74).
2. The APL (Average Picture Level) figure indicates the
average luminance level at which the white stretch
characteristic starts shifting from maximum stretching
to the linear curve. At an increase of the APL of about
13% the curve is linear (see also Fig. 75).
123
CONFIDENTIAL

Table 205 Low level of beam current limiter
Table 198 Blue stretch

BLS
UOCIII series
LLB
BLUE STRETCH MODE
CONDITION
off
internal bias current of BCL pin switched off
on
internal bias current of BCL pin of 0.5 mA

switched on
Table 199 Tint control on UV signals

TUV
Table 206 Dynamic skin tone angle
MODE
not active
active
DSA
CONDITION
117
123
Table 200 Black level offset on Blue channel

OFB
Table 207 Ratio pre- and aftershoot
MODE
offset control on Red channel
RPA1
RPA0
offset control on Blue channel
1:1
1.5 : 1
2:1
Table 201 High contrast in Text mode

HCT
MODE
Table 208 Ratio of positive and negative peaks
normal operation
RGB output signal increased with 3 dB
Table 202 Fast insertion mode

FINM
MODE
normal operation
fast insertion active behind the digital

interface
MODE
normal mode
selected input forced on
RPO1
RPO0
0
0
1
1
0
1
0
1
RATIO
1:1
1 : 1.3
1 : 1.7
1 : 0.7
Table 209 Video dependent coring (peaking)
Table 203 Forced mode of RGB/YUV/YPRPB inputs

FIN
RATIO
COR1
COR0
SETTING
off
coring active between 0 and 20 IRE
Table 210 Coring on SVM

Table 204 Blanking of blue and green output
BLBG
CRA0
CONDITION
normal operation
blanking of the blue and green channel
2003 Nov 11
SETTING
8%
15%
124
CONFIDENTIAL

Table 214 Scan Velocity Modulation mode
Table 211 Parabola on SVM output; note 1

SPR2 SPR1 SPR0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
UOCIII series
SETTING AT POSITIONS A, B
AND C (dB)
A
0
0
3
0
3
0
6
0
3
0
0
3
3
3
0
3
0
3
0
6
0
VMA0
0
0
1
1
0
1
0
1
off
SVM on video
SVM on teletext or OSD
SVM on video or OSD (fast

switching)
MODE
normal gain
gain increased with 6 dB
DDLE
MODE
control loop 2.5 V internally
control loop 2.5 V externally
1. The 1.8 V supply voltage is derived from the internally

generated 2.5 V supply rail by means of an emitter
follower. The control loop of this 2.5 V supply can be
closed taking into account the spread of this emitter
follower (DDLE = 1). In this way a very stable 1.8 V
supply is guaranteed. It is also possible to stabilise the
2.5 V supply by means of an internal control loop
(DDLE = 0).
SETTING
off
0.9 VP-P
1.3 VP-P
1.8 VP-P
Table 217 Soft start-up mode

DSS
Note
1. The output signal amplitudes are specified for an input
signal amplitude that is 50% of the nominal value.
2003 Nov 11
Note
Table 213 Amplitude of SVM output, note 1

VMA1
Table 216 Stabilization of the 1.8 V supply voltage; note 1
DELAY SETTING
SVM2 100 ns +
SVM1 50 ns +
SVM0 25 ns
SVM2
SVM1
SVM0
MODE
DISG
Table 212 Delay of RGB output to SVM output

SVM0 to SVM2
SMD0
Table 215 Gain selection of DISCO
Note
1. The Scan Velocity Modulation output can be made
depend on the horizontal position on the screen. The
positions A, B and C are indicated in Fig. 77 on page
231.
SMD1
MODE
normal operation
soft start-up disabled
125
CONFIDENTIAL

Table 218 Condition flyback input pin (FBISO)
CSY
UOCIII series
Table 221 Y-delay bypass mode (note 1)
BPYD
CONDITION
CONDITION
normal flyback input
Y-delay bypassed
composite H/V timing output
Y-delay enabled
Note
Table 219 Output switch (SWO1)

SWO1
1. This mode can only be activated in the YC-mode

(INA=1).
CONDITION
output is LOW
output is HIGH
Table 220 Condition AVL/SWO/SSIF/REFO/IFREFI

CMB2 CMB1 CMB0
0
CONDITION
AVL and
SIF to FM mono demodulator
SIF to stereo demodulator
output voltage 2.1 V + subcarrier

(REFO)
SWO output voltage low (<0.8 V)
SWO output voltage high (>4.5 V)
external reference carrier for DVB

mix-down (REFIN)
SSIF to digital stereo decoder.

SSIF to FM mono demodulator.
SSIF to digital stereo decoder.

SIF to FM mono demodulator.
SSIF to FM mono demodulator.

SIF to digital stereo decoder.
2003 Nov 11
126
CONFIDENTIAL

Explanation output control data TV-processor
UOCIII series
Table 227 X-ray protection
Table 222 Power-on-reset

POR
XPR
MODE
normal
power-down
no video signal identified
video signal identified
locked
overvoltage detected
VERTICAL OUTPUT STAGE
OK
failure
FSI
INDICATION
not locked
Table 229 Field frequency indication
Table 224 IF-PLL lock indication
no overvoltage detected
NDF
CONDITION
LOCK
Table 228 Output vertical guard
Table 223 Video input signal identification

SID
OVERVOLTAGE
FREQUENCY
50 Hz
60 Hz
Table 230 Condition vertical divider, note 1

Table 225 Phase 1 (1) lock indication
SL
IVW
INDICATION
not locked
locked
VERTICAL WINDOW INDICATION
vertical sync pulse not in narrow window
15 succeeding sync pulses in narrow window
Note
1. More information is given in note 61 on page 214
Table 226Colour decoder mode, note 1

CD3 CD2 CD1 CD0
STANDARD
Table 231 Indication black current stabilization; note 1
no colour standard identified
NTSC with freq. A
PAL with freq. A
NTSC with freq. B
PAL with freq. B
NTSC with freq. C
Note
PAL with freq. C
NTSC with freq. D
1. This function is valid only during the adjustment of the

Vg2 voltage (AVG = 1)
PAL with freq. D
SECAM
WBC
HBC
CONDITION
outside window; current too low
outside window; current too high
in window
Table 232 Condition black current loop

BCF
CONDITION
Note
black current loop is stabilised
1. The values for the various frequencies can be found in

the note of table 133.
black current loop is not stabilised
Table 233 Comb filter mode

COMB
2003 Nov 11
MODE
comb filter not active
comb filter active
127
CONFIDENTIAL

Table 234 Supply voltage and reference oscillator
indication
SUP
UOCIII series
Table 240 Indication FM-PLL in/out lock
FML
CONDITION
supply voltage (5 Volt) not present or

reference oscillator not OK
supply voltage (5 Volt) present and reference

oscillator OK, note 1
FM-PLL out of lock
FM-PLL locked
IVWF
1. When RED = 1 only the supply voltage condition is

checked.
AGC
VERTICAL WINDOW INDICATION
vertical sync pulse not in narrow window
7 succeeding sync pulses in narrow window
Note
Table 235 Indication tuner AGC
1. More information is given in note 61 on page 214
CONDITION
tuner gain control active
no gain control of tuner
Table 242 Signal-to-Noise ratio of the demodulated CVBS

signal (IFVO)
Table 236 Indication RGB-3 input condition

IN3
1
Table 241 Condition vertical divider, note 1
Note
CONDITION
RGB INSERTION
SN2
SN1
SN0
CONDITION
S/N 18 dB
S/N 18 dB and 25 dB
no
S/N 25 dB and 28 dB
yes
S/N 28 dB and 31 dB
S/N 31 dB and 37 dB
Table 237 Indication RGB-2 input condition

IN2
RGB INSERTION
no
yes
supply voltage OK
supply voltage too high
Table 239 Indication FM-PLL in/out window

CONDITION
FM-PLL in window
FM-PLL out of window
2003 Nov 11
S/N 37 dB and 40 dB
S/N 40 dB and 43 dB
S/N 43 dB
YCD
SUPPLY VOLTAGE PROTECTION
FMW
0
1
Table 243 Output of Y/C detector; note 1
Table 238 Protection of 1.8 V supply voltage

SUPR
1
1
CONDITION
CVBS signal at input
Y/C signal at input
Note
1. The Y/C detector is only active for the CVBS(Y)3/C3,
CVBS(Y)4/C4 and CVBS(Y)x/Cx inputs and not for the
CVBS(Y)2/C3 input.
128
CONFIDENTIAL

Table 244 AFC output (two-complement notation); 25 kHz
per step
OUTPUT
0
UOCIII series
Table 246 Indication picture tube warm
PTW
FREQUENCY DEVIATION
no frequency deviation
3C
deviation: +1.5 MHz or more
C4
deviation: 1.5 MHz or more
gain loop not yet stabilised
gain loop stabilised
cathode current below selected current
cathode current selected current
RG6 - RG0
GG6 - GG0
BG6 - BG0
CONDITION
Table 247 Read-out CCC registers, see note on Table 76
Table 245 Indication CCC gain loop

GLOK
CONDITION
CRT DRIVE VOLTAGE
45 VP-P
40
90 VP-P
7F
180 VP-P
Table 248 Deflection timer read-out

DFL4 DFL3 DFL2 DFL1 DFL0
STATE
CONDITION
standby
POR situation
standby
Only standby supply is present
standby
Standby supply is present and SUP bit = 1, note 1
slow start
Slow start of horizontal output is active when SUP bit = 1
slow start
Slow start of horizontal output is active when SUP bit = 0
soft stop
Soft stop of horizontal output is active
operational
Slow start of horizontal output is ended, device is operational
Note
1. IF and sound are operational
2003 Nov 11
129
CONFIDENTIAL

Table 249 Subcarrier oscillator frequency, note 1.
DECODER FREQUENCY
DISC9-DISC2
00000000
-750
-750
-750
-750
10000000
nom.
nom.
nom.
nom.
11111111
+750
+750
+750
+750
Note
1. The nominal decoder frequencies are obtained from
an internal clock generator which is synchronised by a
24.576 MHz reference signal from the -controller
clock. These frequencies can have a small offset from
the standard subcarrier frequencies.
The nominal frequencies are:
a) A: 4.433625 MHz
b) B: 3.582000 MHz (PAL-N)
c) C: 3.575625 MHz (PAL-M)
d) D: 3.579563 MHz (NTSC-M)
2003 Nov 11
130
CONFIDENTIAL
UOCIII series

GENERAL DESCRIPTION OF THE TV SOUND
PROCESSOR
The TV Sound Processor is a digital TV sound processor
for analog multi-channel sound systems in TV sets. It is
based on a 24 bit DSP and designed to support several
applications.
A new easy-to-use control concept was implemented for
easiest configuration programming of the very complex
functionality of the TV Sound Processor. Pre-defined
setups are available for all implemented sound processing
modes. A loudspeaker switching concept allows it to adapt
the pre-defined setups to the specific loudspeaker
application.The built-in intelligence for pre-defined
standards and Auto Standard Detection (ASD) allows an
easy setup of the demodulator and decoder part.
The control concept for the audio processor is based on
the following new features:
Pre-defined setups for the sound processing modes like
Dolby Pro Logic and Virtual Dolby Surround (422,
423)
Flexible configuration of audio outputs to the
loudspeaker configuration with an additional output
crossbar
Master volume function
The control concept for the demodulator and decoder
(DEMDEC) is based on the following new features:
Easy demodulator setup for all implemented standards
with Demodulator and Decoder Easy Programming
(DDEP) for a pre-selected standard or combined with
Auto Standard Detection (ASD) for automatic detection
of a transmitted standard
Automatic decoder configuration and signal routing
depending on the selected or detected standard
FM overmodulation adaptation option to avoid clipping
and distortion
UOCIII series
Supported standards
The multistandard capability of the TV Sound Processor
covers all terrestrial TV sound standards, FM Radio and
satellite FM.
The AM sound of L/L' standard is normally demodulated in
the 1st sound IF. The resulting AF signal has to be entered
into the mono audio input of the TV Sound Processor. A
second possibility is to use the AM demodulator in the
DEMDEC part, however this may result in limited
performance.
Korea has a stereo sound system similar to Europe. It is
supported by the TV Sound Processor. Differences
include deviation, modulation contents and identification. It
is based on M standard.
Other features of the DEMDEC are:
M/BTSC and N standards supported
M/Japan (EIAJ) supported
FM Radio stereo decoding
Alignment-free, fully digital system
For BTSC full dbx performance
SAP demodulation (without dbx) simultaneously with
stereo decoding, or mono plus SAP with dbx
Line/pilot frequency selectable from 15.734 kHz and
15.625 kHz (or automatic detection / auto search)
High selectivity for pilot detection, high robustness
against high-frequent audio components
Pilot lock indicator
SAP detector
Separate noise detectors for stereo and SAP with
adjustable threshold levels, hysteresis, and automute
function
An overview of the supported standards and sound
systems and their key parameters is given in the following
tables.
The analog multi-channel sound systems (A2, A2+ and
A2*) are sometimes also named 2CS (2 carrier systems).
2003 Nov 11
131
CONFIDENTIAL

UOCIII series
ANALOG 2-CARRIER SYSTEMS

Table 250 Frequency modulation
STANDARD
SOUND
SYSTEM
CARRIER
FREQUENCY
(MHz)
FM DEVIATION
(kHz)
NOM./MAX./OVER
mono
4.5
15/25/50
M
M
A2+
4.5/4.724
15/25/50
B/G
A2
5.5/5.742
27/50/80
mono
6.0
27/50/80
D/K (1)
A2*
6.5/6.258
27/50/80
D/K (2)
A2*
6.5/6.742
27/50/80
D/K (3)
A2*
6.5/5.742
27/50/80
MODULATION
SC1
mono
1 (L
2
1 (L
2
+ R)
+ R)
15/75
2(L
R)
15/75 (Korea)
15/50
15/50
+ R)
15/50
+ R)
15/50
+ R)
15/50
mono
1 (L
2
1 (L
2
1 (L
2
SC2
BANDWIDTH/
DE-EMPHASIS
(kHz/s)
Table 251 Identification for A2 systems

PARAMETER
A2/A2*
A2+ (KOREA)
Pilot frequency
54.6875 kHz = 3.5 line frequency
55.0699 kHz = 3.5 line frequency
Stereo identification
frequency
line frequency
117.5 Hz = ------------------------------------133
line frequency
149.9 Hz = ------------------------------------105
Dual identification frequency
line frequency
274.1 Hz = ------------------------------------57
line frequency
276.0 Hz = ------------------------------------57
AM modulation depth
50%
50%
2-CARRIER SYSTEMS WITH NICAM

Table 252 NICAM standards
SC1
MODULATION
STANDARD FREQUENCY
TYPE
(MHz)
B/G
5.5
FM
SC2
ROLL-OFF NICAM
DEVIATION (MHz) DE-EMPHASIS
(%)
CODING
INDEX
NICAM
(kHz)
(%)
NOM./MAX.
NOM./MAX.
/OVER
27/50/80
5.85
J17
40
note 1
6.0
FM
27/50/80
6.552
J17
100
note 1
D/K
6.5
FM
27/50/80
5.85
J17
40
note 1
6.5
AM
54/100
5.85
J17
40
note 1
Notes
1. See 'EBU specification' or equivalent specification.
2003 Nov 11
132
CONFIDENTIAL

UOCIII series
SATELLITE SYSTEMS
An important specification for satellite TV reception is the Astra specification. The TV Sound Processor is suited for the
reception of Astra and other satellite signals.
Table 253 FM satellite sound
CARRIER TYPE
CARRIER
FREQUENCY
(MHz)
MODULATION
INDEX
MAXIMUM
FM DEVIATION
(kHz)
MODULATION
BANDWIDTH/
DE-EMPHASIS
(kHz/s)
Main
6.50(1)
0.26
85
mono
15/50(1)
15/adaptive(3)
Sub
7.02/7.20
0.15
50
m/st/d(2)
Sub
7.38/7.56
0.15
50
m/st/d(2)
15/adaptive(3)
Sub
7.74/7.92
0.15
50
m/st/d(2)
15/adaptive(3)
Sub
8.10/8.28
0.15
50
m/st/d(2)
15/adaptive(3)
Notes
1. For other satellite systems, frequencies of, for example, 5.80, 6.60 or 6.65 MHz can also be received. A de-emphasis
of 60 s, or in accordance with J17, is available.
2. m/st/d = mono or stereo or dual language sound.
3. Adaptive de-emphasis = compatible to transmitter specification.
2003 Nov 11
133
CONFIDENTIAL

UOCIII series
BTSC/SAP, JAPAN (EIAJ) AND FM RADIO SYSTEMS

Table 254 Frequency modulation
SOUND
SYSTEM
CARRIER
FREQUENCY
(MHz)
FM DEVIATION
(kHz)
NOM./MAX./OVER
MODULATION
SC1
BANDWIDTH/
DE-EMPHASIS
(kHz/s)
mono
4.5
15/25/50
mono
15/75
BTSC
4.5
50 max
MPX (FM/AM)
14/n.a.*
SAP
5fh=78,67kHz
15 max
SAP (FM)
8/n.a.*
Japan
4.5
15/25/50
MPX (FM/FM)
15/50
FM Radio
stereo
4.5...10.7
40/75/150
MPX (FM/AM)
15/75 or 15/50
STANDARD
*: not applicable due to dbx noise reduction
Table 255 Identification for BTSC/SAP, Japan (EIAJ) and FM Radio systems
PARAMETER
2003 Nov 11
PILOT TONE FREQUENCY
BTSC
1fh=15.734 kHz
Japan/(EIAJ)
3.5fh= 55,069 kHz
FM Radio
19kHz
134
CONFIDENTIAL

UOCIII series
FUNCTIONAL DESCRIPTION SOUND PROCESSOR

The UOCIII TV Sound Concept
The UOCIII sound concept is implemented over the video processor and TCG-microcontroller.
Fig. 41 is showing this concept.
Only relevant blocks, functions and signal flows for sound are given. For details of the application see UOCIII application
notes.
analogue crossbar
AUDIO IN 5
-3dB
AUDIO IN 4
AUDOUT
S L,R
-3dB
AUDIO IN 3
Audio
ADC
-3dB
AUDIO IN 2
DAC1
DAC1
PROC
3dB/
9dB
-3dB
Videoproc.
part
FM
RF1
TUNER
SIF
IN
+ SAW
filters
VIF
IN
Dig.Controller
part
AM
QSS
or
VIF
SSIF
SSIF
SSIF
SW
AGC
ADC
DEM
DEC
Dig. Output Crossbar
FMMONO/AM
Digital
Input
Crossbar
LS
PROC
HW/
DSP
AUX
audio
contr.
DAC2
3dB/
9dB
AUDOUT
HP L,R
3dB/
9dB
AUDOUT
LS L,R
I2S proc./interface
SSIF
I2S
IN/out
I2S OUT
I2SDI1/O
I2SDO2
I2SDO1
(only relevant blocks, functions and signal flow for sound are shown)
Fig.41 UOCIII Sound Concept
The tuner receives a RF signal and converts it to IF. Via appropriate SAW filters the SIF signal is delivered to the QSS
stage of the video processor and if channels according to standard L/L are received also to the AM demodulator. The
Quasi Split Sound demodulation generates the SSIF or intercarrier signal. By the SSIF switch it is possible to choose
between the internally derived intercarrier and an external second SIF (2NDSIF EXT), e.g. an intercarrier coming from a
PIP frontend. In other applications a 10.7 MHz radio IF or satellite FM may be connected to this input. The selected SSIF
passes some anti alias filtering, is amplified in an AGC amplifier (SSIF AGC) and is then converted from analogue to
digital (SSIF ADC).
The audio signal out of the AM demodulator is connected to the analogue crossbar at the video processor. All other inputs
to this multiplexer/audio switch come from external, either from a PIP frontend or SCART/CINCH (AUD IN x) or the DAC
output signals from the digital controller. The audio AD converters are digitising the audio signals foreseen for further
digital processing. One stereo output (AUDOUT S) is available for connections to SCART/CINCH sockets.
2003 Nov 11
135
CONFIDENTIAL

The sound part on the digital controller consists of the
demodulator/decoder (DEMDEC), a digital input crossbar,
the digital audio processing for the loudspeaker and DAC
channels, the I2S processing and interfacing, a digital
output crossbar as well as the DA conversion.
An auxiliary audio control (volume control, AUX audio
contr.) is available on the video processor. Here it is
applied to the headphone channel.
The part of the concept located in the digital controller will
be described in the next chapters.
UOCIII series
Functional Overview Of the digital controller sound
part
The digital controller sound part consists of the SSIF ADC,
audio ADCs, DEMDEC HW, the sound DSP core, audio
DACs and I2S interface hardware as shown in fig. 42. The
DEMDEC part of the Sound DSP is used for the decoder
and partly demodulator tasks. The AUDIO part provides
the sound features, from the level adjust unit up to the
output crossbar. Audio DACs and I2S hardware are
converting the processed signals to analogue or digital
audio.
Beeper
(L+R)/2
DAC2
L/A
Audio Control
BMT
DAFO1
Dolby
Pro Logic
VDS
Main Channel Processing

DAFO2
SW Channel Processing
SAP
A_ADC1
AUD
ADC
A_ADC2
Noise/
Silence
Generator
I2S1L IN
I2S
AUX1/I2S1 Channel Processing

AUX2/I2S2 Channel Processing
DAC2
OUTL
DAC2
OUTR
DAC1
OUTL
DAC1
OUTR
AUX3/DAC1 Channel Processing

I2S1 OUT
I2S
proc
I2S
IN
Surround Channel Processing
Digital Output Crossbar
AUD
ADC
IN
Digital Input Crossbar
Centre Channel Processing
DAC1
MONO
DAC1L
R/B
DAC1R
SSIF
ADC
DEMDEC
SSIF
dig.
SSIF
DEMDEC
Hardware
Sound DSP
(*)
Audio Monitor
I2S1R IN
I2S2 OUT
I2S3 OUT
(*)
(*) : connected to one pin that can be used alternatively as I2S IN or I2S3 OUT
Fig.42 Overview of the UOCIII Sound Functions on the digital controller
The SSIF signal is applied to the SSIF ADC for conversion

and is then fed to the DEMDEC hardware processing
mainly for demodulation but also some decoding tasks.
Remaining decoding is done in the DEMDEC block of the
Sound DSP. The DEMDEC processing will be described in
the next chapter.
2003 Nov 11
The audio signals (AUD ADC IN) from the analogue

crossbar pass the audio ADC and are fed directly into the
AUDIO part of the Sound DSP like the I2S signals, which
is coming from I2S processing hardware. After level adjust
all signals from the DEMDEC and the I2S input are
available at the digital input crossbar. A special input is
136
CONFIDENTIAL

provided for the Noise/Silence Generator needed for
Dolby Pro Logic processing.
The loudspeaker signal processing is performed in the
main, SW (subwoofer), centre and surround channels
according to the signal type received. Channels AUX1 and
AUX2 are provided for I2S signal processing and channel
AUX3 is dedicated to DAC1 signal handling.
All channel processing delivers signals to the digital output
crossbar, which offers the facility to connect each of the
channel signals to the appropriate DACs, or to the I2S
outputs.
In standard TV applications the main channel signal (L, R)
will be connected to the DAC2 for reproduction at the
speakers. With multichannel signals centre, surround or
subwoofer channels may be passed to the I2S outputs
where external DACs may be applied. By this it is possible
to build Dolby Normal/Wide, Dolby Phantom Centre or
Dolby 3 Stereo set-ups and also a VDS423 application.
Details of the audio processing will be described in
following chapters.
Demodulator and decoder
INTRODUCTION
The TV sound processor provides an easy-to-use
programming interface and built-in intelligence for the
demodulator and decoder part.
The sound demodulator is able to search for sound
carriers and react to transmission mode changes
autonomously, without interaction of the micro controller
software.
It is possible for a typical terrestrial TV application to set up
the entire demodulator with transmission of few control
words.
The control interface still allows access to every detail,
called demodulator expert mode, for special applications
such as satellite TV, more elaborated search algorithms
etc.
The new TV Sound Processor Demodulator and
Decoder Easy Programming (DDEP) interface provides
three possible approaches to setup the demodulator and
decoder parts:
UOCIII series
MIXER
The digitized 2nd SIF input signal is fed to the mixers,
which mix one or both input sound carriers down to zero IF.
The mixer frequency is derived by the standard setting
(Easy Programming) or in the Demodulator and Decoder
Expert Mode (DDXM) by a 24-bit control word for each
carrier. For NICAM demodulation, a feedback signal is
added to the control word of the second carrier mixer to
establish a carrier-frequency loop.
FM AND AM DEMODULATION
An FM or AM input signal is fed via a band-limiting filter to
a one of two demodulators that can be used for either FM
or AM demodulation. Four filters with different bandwidth
are available. The output signal of the first demodulator
can be used for further demodulation of multiplex signals
used in the BTSC, EIAJ and FM Radio standards.
FM IDENTIFICATION
The identification of the FM sound mode is performed by
AM synchronous demodulation of the pilot signal and
narrow-band detection of the identification frequencies.
The result is available via the control bus interface. A
selection can be made for three different modes that
represent different trade-offs between speed and reliability
of identification. The mode is set by DDEP (for FM
two-carrier standards) or via expert mode. DDEP also
performs automatic FM de-matrix control in dependence
on the identification.
FM/AM DECODING
A high-pass filter suppresses DC offsets from the FM / AM
demodulators due to carrier frequency offsets and
supplies the monitor/peak function with DC values and an
un-filtered signal, e.g. for the purpose of carrier detection.
The audio bandwidth is approx. 15 kHz.
The de-emphasis function offers fixed settings for the
supported standards (50 s, 60 s, 75 s and J17).
An adaptive de-emphasis is available for Wegener-Panda
1 encoded programs.
Auto Standard Detection (ASD)
A matrix performs the de-matrixing of the A2 stereo, dual

and mono signals to obtain the left (L) and right (R) or
language A and B signals.
Static Standard Selection (SSS)
FM PILOT CARRIER PRESENT DETECTOR
Demodulator and Decoder Expert Mode (DDXM)
2003 Nov 11
The TV Sound Processor provides FM A2 standard pilot

carrier detection.
137
CONFIDENTIAL

NICAM DEMODULATION
The NICAM signal is transmitted via DQPSK modulation at
a bit rate of 728 kBit/s. The NICAM demodulator performs
DQPSK demodulation and feeds the resulting bit stream
and clock signal to the NICAM decoder.
A timing loop controls the sample rate conversion circuitry
to lock the sampling rate to the symbol timing of the
NICAM data.
NICAM DECODER
The NICAM decoder performs all decoding functions in
accordance with the EBU NICAM 728 specification. After
locking to the frame alignment word, the data is de
scrambled by applying the defined pseudo-random binary
sequence; the NICAM decoder will then synchronize to the
periodic frame flag bit C0.
The status of the NICAM decoder can be read out from the
NICAM status register by the user (see the control-bus
register description). The OSB bit indicates that the
decoder has locked to the NICAM data. The VDSP bit
indicates that the decoder has locked to the NICAM data
and that the data is valid sound data. The C4 bit indicates
that the sound conveyed by the FM mono channel is
identical to the sound conveyed by the NICAM channel.
The error byte contains the number of sound sample
errors, resulting from parity checking, that occurred in the
past 128 ms period. The Bit Error Rate (BER) can be
calculated using the following equation;
bit errors
5
BER = ----------------------- error byte 1.74 10
total bits
During NICAM mode a switchable J17 de-emphasis is
supplied.
NICAM AUTO-MUTE
If the Auto Standard Detection (ASD) or the Static
Standard Detection (SSS) feature is activated the
following auto mute function is in effect.
If NICAM B/G, I, D/K is received, the auto-mute is enabled
and the signal quality becomes poor, the built-in control
automatically switches the output signal (DEC output) to
FM channel 1. The automatic switching depends on the
NICAM bit error rate. The auto-mute function can be
disabled via the control bus.
This function is enabled by setting bit NIC_AMUTE to 0.
Upper and lower error limits may be defined by writing
appropriate values to the corresponding control bits
(NICLOERRLIM and NICUPERRLIM). When the number
of errors in a 128 ms period exceeds the upper error limit
the auto-mute function will switch the output sound from
NICAM to whatever sound is on the first sound carrier (FM
2003 Nov 11
UOCIII series
or AM). When the error count is smaller than the lower
error limit the NICAM sound is restored.
The auto-mute function can be disabled by setting bit
NIC_AMUTE to 1. In this condition clicks become audible
when the error count increases; the user will hear a signal
of degrading quality.
For NICAM L applications, it is recommended to
demodulate AM sound in the first sound IF. The
demodulated AM is provided by the internal IF processor.
For applications with external IF processing the external
demodulated AM signal can be connected to the
SCART/Mono input of the TV Sound Processor. By setting
the EXTAM bit, the auto-mute function will switch to the
audio ADC input signal named EXTAM instead of
switching to the first sound carrier. The ADC source
selector should be set to internal AM mono signal or to the
external SCART/mono input, where the AM sound signal
should be connected.
BTSC STEREO DECODER
The FM demodulated composite signal is fed into the MPX
demodulator for synchronous AM demodulation of the sub
carrier. The demodulator includes a pilot detector and pilot
cancellation circuit. The main channel (baseband part,
encoded (L + R)/2) signal passes a 75 s fixed
de-emphasis filter, while the compressed sub channel
signal goes through the dbx decoder. Both signals are fed
to the stereo dematrix to obtain the L and R signals.
SAP DEMODULATOR
The composite signal is fed to the FM sub channel
demodulator and detector circuit. A noise detector can be
used to mute the SAP output in the event of insufficient
signal conditions. The SAP identification signal can be
read by the control bus.
dbx DECODER
The circuit includes the noise reduction system in
accordance with the BTSC system specification and
conforms to the standard of quality defined by THAT
Corporation
JAPAN (EIAJ) DECODER
The above mentioned FM sub channel demodulator,
together with a matching low pass filter, is used to decode
the EIAJ multiplex signal. The resulting main and sub
channel signals then pass through the similar blocks as in
FM A2 mode, that is DC notch filtering, fixed deemphasis
(75 s) and dematrix.
138
CONFIDENTIAL

FM RADIO DEMODULATOR
The above mentioned MPX demodulator can also be used
to decode a FM Radio input signal with a 19 kHz pilot tone.
A freely selectable intermediate frequency (IF) between
4.5 and 10.7 MHz can be applied to the SIF input. Both the
European and North American modes (pre-emphasis 75
s and 50 s, respectively) are supported.
EASY PROGRAMMING
For a complete description of DDEP and application hints
refer to the technical report HSIS/TR0107.
Overview
DEMDEC Easy Programming (short DDEP) is the name of
the high-level control interface to the DEMDEC DSP of the
TV sound processor. Its main intention is to make the
development of system control software for the DEMDEC
as simple as possible, while optimally exploiting the
available hardware and DSP resources.
The functionality of DDEP is divided into three main areas:
1. Demodulator and decoder configuration with optional
standard and second carrier / subcarrier search;
2. Decoding, signal routing and switching for simple
handling of broadcast sound signal types, plus
encoding of the main status register;
3. FM overmodulation adaptation: optional adaptive
reduction of levels and filter widening in case of
overmodulation, in order to avoid distortions due to
clipping or overflow.
The DDEP software controls both the demodulator
hardware and the real-time signal processing software
running on the same DSP, e.g. by changing filter
coefficients, pointers etc., often depending on status
information generated by hardware or software.
Most functions act like "background processes": small
code sections are executed at a reduced rate (for instance
every 32th sample at 32 kHz = 1000 times per second), in
order to accommodate a large amount of program code
without consuming too much of the available processing
power of the DSP. A "control timeslot" is reserved in the
DSP software in which both control register decoding and
background processing is performed.
DDEP in short
DDEP can operate in one of two modes, which differ only
in the type of standard handling. Additionally, a few options
are available to the user.
2003 Nov 11
UOCIII series
In ASD (Auto Standard Detection) mode, an automatic TV
sound standard and carrier search is performed at a
channel switch, following preferences determined by the
user or the system controller, such that a standard
detection and identification (stereo / dual) result is
obtained as fast as the hardware permits. If only the stereo
system within a standard changes later, the search
procedure adapts (e.g. B/G A2 to B/G NICAM or vice
versa).
The SSS (Static Standard Selection) mode requires the
user to select the sound standard (incl. stereo system) by
means of a standard code (e.g. code 4 denotes "B/G A2",
the European analog FM two-carrier standard) and no
searching is done. This mode is like a subset of the ASD
mode in that it acts similarly as the ASD mode if the
standard detection has found the selected standard.
However, in SSS mode the decoder never changes to a
different standard, and the user must supply settings that
ASD selects by its own expertise (IDENT speed for A2
standards and line frequency for BTSC). The SSS mode
can be used to enforce a certain sound standard in case
ASD was unable to find a sound carrier and is needed to
select FM Radio decoding. The ASD routines operate as if
using the SSS mode to select a certain standard.
In both of these modes, the DDEP system handles the
other signal processing and settings automatically without
a need for further interaction, and also allows the same
options:
1. It is possible not to use the default NICAM
configuration for a detected or selected standard, but
supply other settings via the NICAM configuration
register.
2. The default thresholds and hysteresis sizes for
noise-based automute and SAP detection can be
overruled.
3. The optional overmodulation adaptation may be used
in ASD as well as in SSS mode.
4. A pre-scaling of the EXTAM signal is usually needed
to obtain a correct level.
5. As NICAM sound often seems softer than the FM
sound, an additional level adjust for this signal path is
possible.
6. Levels of the DEMDEC output signals may be
changed individually if a level other than the nominal
-15 dBFS (with nominal modulation degrees) is
desired, all signal levels can be adjusted before the
first digital crossbar.
139
CONFIDENTIAL

DDEP can be switched off completely, allowing user
access to all low-level settings. All automatism are then
disabled. This so called "DEMDEC expert mode" ("manual
mode") requires detailed knowledge and understanding of
the involved hardware and software and will be explained
in a later report. A satellite TV application unfortunately
requires the expert mode since satellite sound is not
supported by DDEP. As usual for this application, all
configurations like carrier frequencies and deemphasis
types must be supplied by the set user or have to be
pre-programmed.
UOCIII series
Note that DDEP does not include handling the SIF
frontend (input selection, AGC etc.) since this is
application dependent.
Fig.43 sketches the handling of the two different control
register sets for DDEP and expert mode and their
translation into software and hardware settings.
All central DDEP functions are controlled by writing a
single register, the DDEPR register is located in the XRAM
(data memory) of the DSP and accessible via the PI bus
interface (I2C).
DDEP control
registers
ASD search
procedures
SSS mode
expert mode
control registers
Overmod.
Adaptation
(export mode only)
standard
dependent
low-level control routines, internal variables, hardware registers
(pointers, coefficients etc.)
(detectors)
real time signal processing software
Fig.43 Control Flow
2003 Nov 11
140
CONFIDENTIAL

DEMDEC hardware blocks
UOCIII series
The dedicated demodulator and decoder hardware
delivers "raw" signals that cannot be used without further
processing in the DEMDEC realtime software. Each signal
comes in with a sample rate of n*32 kHz.
Due to the high bandwidth and computational

requirements, the actual demodulation of the sound
carrier(s) is implemented in dedicated digital hardware.
These are
Sample rate for the audio processing and DEMDEC is 32

kHz.
1. a SSIF frontend with AGC and high-speed ADC;
Figure 44 shows the described hardware blocks and their

connection to the DSP. The hardware is usually controlled
by the DDEP software, or by the controller via the expert
mode.
2. two FM / AM demodulator channels with

programmable mixer frequencies and four different
filter bandwidths;
3. a NICAM demodulator and decoder for all NICAM
standards;
4. an identification circuit for all standards;
5. an additional "BSJ" ("BTSC, SAP, Japan") block
provides MPX demodulation (for BTSC and FM
Radio), FM subchannel demodulation plus matching
filter (for SAP and the Japanese EIAJ standard), and a
noise detector.
analog
SSIF
AGC
A/D
mixer
ch. 1
decimation
filters
FM / AM
demodulator
#1
4 fs
MPX
demodulator
(24.576 MHz)
clock
generation
noise
detector
EIAJ lowpass
FM sub
channel
demodulator
FM
2 fs
AM
BSJ block
mixer
ch. 2
decimation
filters
FM / AM
demodulator
#2
FM
Identification
(Europe / Korea /
Japan)
control signal for

carrier tracking
NICAM
demod. &
decoder
clock
control
Fig.44 Demodulator & Decoder Block Diagram
2003 Nov 11
141
CONFIDENTIAL
1 fs
EPICS7A
DSP
Input
Registers (DIO)

Signal processing in DSP software
The output signals of the above-mentioned hardware
blocks (next to signal from other sources like ADC or I2S)
read in by the DSP, processed, decoded, and forwarded to
the digital input crossbar for further processing (volume,
tone control, effects etc.). Fig.45 shows this signal flow in
a simplified structure.
The signals from the analogue sound carriers are passing
through several filters like down-sampling and
deemphasis, noise reduction processing (Wegener-Panda
/ dbx expanders), and dematrixing. For the NICAM signal
only a J17 deemphasis is needed. The decoded signals
are available at the DEMDEC outputs (identical to inputs
of the digital input crossbar). The first (topmost) pair of
output channels, called DEC (from DECoder), is intended
to carry the stereo or bilingual (dual) signal; an extra
MONO channel always contains the mono signal from
the first sound carrier (always FM or AM), or the main
channel (baseband, [L+R]/2) of the MPX typestandards
BTSC, FM Radio and EIAJ. (This channel may contain
different audio contents in case of NICAM.) Another signal
channel named SAP transports a SAP signal if detected
during a BTSC reception. An external AM signal should
be used for standard L since the internal digital AM
demodulator does usually not achieve the S/N
performance of an analogue demodulator operating on the
first sound IF. This signal may be available via an ADC
input. If standard L is active, DDEP can feed this signal to
the MONO output of the DEMDEC (and to the DEC as well
if no NICAM is detected), or alternatively use the internal
AM demodulator output.
2003 Nov 11
UOCIII series
By means of this signal routing, the processing paths in the
audio backend do not need to select a specific source
depending on the currently activesound standard as it was
required on earlier Philips stereo decoders (FM/AM,
NICAM source). For every audio processing path, the
controller can select the DEC, MONO etc. output like any
other signal source (ADC, I2S input,..). The information
about the signal type (mono, stereo, dual) on the DEC
channels is available by two status bits. This also allows
the audio backend to implement a smart matrix which
selects one of the two languages in dual mode, or stereo
in other cases.
The MONO output can be selected in case that stereo/dual
is not wanted, which a two-channel output to another
destination is still possible. A special case is a NICAM
transmission with independent contents of analogue and
NICAM sound carriers (indicated by status flag RSSF=0)
when the mono channel carries a different signal than the
NICAM channels.
Internal scalings are applied in DDEP mode such that all
outputs signals have a level of -15 dBFS for nominal
modulation degrees (e.g. 54% full scale sine wave = 27
kHz FM deviation of a B/G FM carrier). Additional level
adjustments can be performed at the digital crossbar in the
audio DSP. In export mode, the internal scalings, switches
etc. must be controlled via the expert mode registers.
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UOCIII series
MONOSEL
4x
DIO
lowpass,
dec. by 2
lowpass,
dec. by 2
DC notch,
deemph.
lowpass,
dec. by 2
lowpass,
dec. by 2
DC notch,
deemph.
ch. 1
scaling
4x
DIO
ch. 2
DECPATH
MONO
FM
dematrix
FM / AM / BTSC
lowpass,
dec. by 2
lowpass,
dec. by 2
output level
adjust
ADC (L)
75 s
deem.
lowpass,
dec. by 2
lowpass,
dec. by 2
DC
notch
DC
notch
dbx
DECSEL
EIAJ main
2x
DIO
decimation
by 2 &
equalizer
DC notch,
deemph.
2x
DIO
decimation
by 2 &
equalizer
DC notch,
deemph.
DEC
compromise
lowpass
ordbx
FM subch.
DIO
DIO
NICAM (J17)
deemphasis
NICAM
Fig.45 Signal processing modules
2003 Nov 11
143
CONFIDENTIAL
SAP

UOCIII series
Audio Processor
The functional overview of Audio part of the Sound DSP is shown in Fig.46
S
MSel
Noise/
Silence
Gen.
C
Ba/Tr
Loudn
S
Ba/Tr
SUB
Master Volume
L,R Trim
SUB
EcoSUB
MAIN
C
Eql
L,R
SM
DAFO2
to DAC2
Beeper
SUB
SM
C
SM
S
SM
Silence
AUX1,2
2 equal channels for I2S
AUX3
Audio Monitor
AUX1,2
Vol/Trim
AUX1,2
AUX3
Vol/Trim
AUX3
SM
BBE or DBB or DVB can be used
DAFO1
C
MSel
S IN
BBE
C
DPL,423
S
DPL
C IN
Loudn
Ps. Hall
/Matrix
C,S
Passiv
e
Matrix
Main
Eql
DVB or DBB in L,R or SUB
L,R
423,422
AUX3 AUX1,2
Digital Input Crossbar ( SSel, Matrix )
C,S
VDS423/422
or
TruSurround
Bass Management
L,R
(L+R)/2
DPL
MAIN
Ba/Tr
(L-R)/2
L,R DPL
EPS or
ESS or
3D Sound
S Delay
L,R M/ST
AVL
MAIN
L,R
(L+R)/2
MAIN MSel
Level adj.
IIS IN
ADC (L, R)
DEC (L,R from DEMDEC)
MONO (from DEMDEC)
SAP (from DEMDEC )
I2S1L,R
OUT
I2S2L,R
OUT
SM
DAC1
L,R
DPL , VDS
are trademarks of Dolby Labs
TruSurround
, 3D Sound
are trademarks of SRS
Labs
BBE is a trademark of BBE Sound Inc.
Fig.46 Audio Backend Operation of UOCIII (DSP functions)
The processing of the loudspeaker channels (MAIN, SW,

C, S), the auxiliary channels AUX1 to AUX3 is nested
between the digital input crossbar and the digital output
crossbar.
The Noise/Silence Generator is a special source. It is

needed as noise source for Dolby Pro Logic speaker
trim compliant to the Dolby requirements for a noise
sequencer
Inputs to the digital input crossbar are the sources
The digital input crossbar provides source select and

matrixing for the channels MAIN (L, R), AUX1 to AUX3, but
only source select for centre (C), surround (S) because
these are mono channels.
- DEC, with the four lines L/A, R/B, Mono, SAP,

- A_ADC 1,2, with L/A, R/B coming from the audio ADC,
- I2S 1 IN, from the I2S input.
All these signals pass the level adjust before entering the
crossbar. That adjust is needed to level the source signals
if they deviate from nominal setting.
2003 Nov 11
Although the selectors are all of the same type not all
facilities will be used in normal applications of UOCIII. E.g.
the output of the centre and surround selectors can be
permanently connected to the Noise/Silence Generator.
The AUX channels need not to be switched to
Noise/Silence.
144
CONFIDENTIAL

Setting of the digital matrix depends on the type of input
signal. The type may be known from the identification in
the demodulator/decoder as stereo, dual language or
mono. So the switching can be made dependent from the
identification. For dual language the preference for
language A or B can be set when automatrix is selected.
In this case the matrix provides the language according to
the preference selected by the end-user.
If an external audio source (ADC, I2S) is chosen the signal
type is unknown or can only be seen from the label of a
tape etc. Thus the end-user needs to get a selection facility
in this case. It should include the choice between
stereo/dual language (AB), mono (from stereo by (A+B)/2,
also called forced mono), sound A or B and a swap (BA)
for stereo if the source has interchanged L and R.
The processing channels are dedicated to loudspeakers
(MAIN, SW, C, S), to I2S OUT (AUX1, AUX2) or DAC1
(AUX3). AUX1 to AUX3 offer only volume and balance
control (Vol/Bal) and softmute (SM).
UOCIII series
functions provided can be used according to these signal
types. Some of them are dedicated to specific modes
leading to constraints. The AVL and Pseudo Hall/Matrix
((L+R)/2, (L-R)/2) can only be used with stereo or mono
signals, VDS only with DPL decoded signals. Extended
Pseudo Stereo (EPS) or Extended Spatial Stereo (ESS)
can be selected, but for DPL it has to be switched off to
meet the Dolby requirements. Other selections depend on
the speaker system, whether the set is equipped with 5
speakers (L, R, SW, C, S) (only possible when external
DACs are applied) from which all are used or maybe the
surround speaker is disconnected or with just 2 speakers
(L, R). Also important is the speaker size/bandwidth.
Some of the functions are set by SNDMODE according to
the Sound Mode Table. The rest needs to be controlled by
individual settings.
SOUND MODES OF THE LOUDSPEAKER CHANNELS
Appropriate sound modes are defined in the table 256:
In the loudspeaker channels we can process mono,

normal stereo or Dolby Pro Logic encoded signals. The
Table 256 Sound Mode Table

FUNCTION
Sound Mode
M/ST
- Mono/Stereo in case of mono or stereo source signals
M/ST Hall
- Mono/Stereo with pseudo Hall in case of mono or stereo source signals
M/ST Matrix
- Mono/Stereo with pseudo Matrix in case of mono or stereo source signals
DPL N/W (normal centre)
- DPL normal/wide in case of DPL decoded source signals
DPL PH (phantom centre)
- DPL Phantom Centre in case of DPL decoded source signals
DPL 3ST (3 stereo)
- DPL 3 Stereo in case of DPL decoded source signals
VDS423
- DPL+VDS(423) in case of Virtual Dolby Surround 423
VDS422
- DPL+VDS(422) in case of Virtual Dolby Surround 422
SRS TruSurround
- Passive matrix + TruSurround virtualizer (422)
DPL NSEQ
- DPL speaker level Trim (noise sequencing)
The Sound Mode sets explicitly the functions AVL, DPL, VDS, Main MSel, C MSel, S MSel, Pseudo Hall/Matrix and it
provides a specific setting for noise sequencing.
The table 257 shows the setting of these functions for the loudspeaker channels by Sound Mode control. All other
functions have to be set by direct control via the related registers and bits.
2003 Nov 11
145
CONFIDENTIAL

UOCIII series
Table 257 Sound Mode Settings

SETTING BY SOUND MODE OF FUNCTIONS
SOUND
MODE
M/ST
M/ST Hall
M/ST
Matrix
DPL N/W
(normal
centre)
DPL PH
(phantom
centre)
AVL
active
(note 1)
active
(note 1)
active
NOISE
PSEUDO
VIRTUALI
MSEL.
/SILENCE
HALL
ZER
MAIN
GEN.
/MATRIX
not active active
not active connected to not active
DPL
(note 2)
not active not active
not active not active
(note 1)
not active DPL N/W not active
not active DPL PH
not active
not active
not active
not active
not active
MSEL.
CENTRE
MSEL.
SURROUND
connected to connected to
L,R M/ST
CIN
connected to Pseudo
Hall active
L,R M/ST
connected to Pseudo
Matrix
L,R M/ST
active
connected to not active
L,R DPL
CDPL,423
L,R DPL
CDPL,423
(L+R)/2
(L+R)/2
SIN
(L+R)/2
(L-R)/2
SDPL
SDPL
(silence)
DPL 3ST
(3 stereo)
not active DPL 3ST not active
VDS423
VDS422
SRS
TruSurround
not active not active not active
DPL NSEQ not active not active active
not active
VDS423
VDS422
(note 3)
L,R DPL
CDPL,423
(silence)
L,R 423,422
CDPL,423
(silence)
L,R 423,422
CDPL,423
SDPL
SDPL
SDPL
(silence)
(silence)
TruSurrou connected to not active

nd (422)
L,R 423,422
CDPL,423
not active
(silence)
(silence)
L,R M/ST
CIN
SDPL
SIN
Notes
1. AVL active means that the set maker can use all facilities by direct control via related registers and bits
2. the noise/silence generator is active, MSel Centre is connected to CIN and MSel Surround is connected to SIN to
give the set maker the facility to build a noise sequencer application of his choice with the M/ST sound mode.
3. (silence) means that the signal carries silence, no audio or noise.
2003 Nov 11
146
CONFIDENTIAL

UOCIII series
DESCRIPTION OF THE FUNCTIONS
Noise Sequencer for DPL
Level Adjust
The set maker has to provide a program to build a Noise

Sequencer with the components available in the UOCIII.
The procedure is described in the Dolby Licensee
Information Manual: Dolby Surround Pro Logic, issue
6. All channels L, C, R, S (only possible when external
DACs are applied) can be connected to the noise source
of the noise/silence generator and by use of the soft-mute
(SM) the noise can be cycled. It is recommended to mute
the sub-woofer output, while the noise sequence is active.
Level adjust in a range from +15dB to 15dB is provided

for input signals from the demodulator/decoder (DEC),
ADC and I2S. A step of 16 is defined as mute.
Digital Input Crossbar

The digital input crossbar can connect any input with every
output channel for source selection. It also includes a
digital matrix for each stereo output. For input signals A
and B this matrix can provide at the output AA, AB, BA, BB,
(A+B)/2 and (A-B)/2. The specific modes Auto Language
A and Auto Language B take care that either language A
or B is selected automatically when dual language is
detected by the TV sound processor.
AVL
The AVL reduces the audio input signal in the MAIN
channel (L, R) to a selectable maximum output level if it
exceeds this level at the input of the stage.
A detector creates the control signal from L and R. The
AVL provides a short attack time and decay times of 20ms,
2s, 4s, 8s and 16s. A weighting filter can be chosen in the
control signal generation. The advantage is that bass
signals and high frequency components have less impact
on control.
The Dolby Pro Logic Function (DPL)

The Dolby Pro Logic Decoder is compliant to the
Dolby Licensee Information Manual: Dolby Surround
Pro Logic, Issue 6.
If the MAIN channel signal L, R is Dolby encoded the
decoder can generate appropriate L, R, C and S signals.
Auto Balance is always provided. The selection of DPL
normal/wide, Phantom Centre, 3 Stereo delivers output
signals according to the Dolby requirements. Outputs not
used in a specific mode carry digital Silence .
Surround delay is adjustable between 15ms and 30ms.
2003 Nov 11
Virtual Dolby Surround

Virtual Dolby Surround gives a surround sound
impression with use of only two speakers (VDS422) or
three speakers (VDS423, only possible when external
DACs are applied). Input to VDS are the L, R, C and S
outputs of the DPL decoder. The surround signal S is
virtualised and redirected in both cases to the left and right
channel whereas the centre signal is redirected to L, R
only when VDS422 is selected. In VDS423 a centre
channel is provided.
The intensity of the effect can be controlled.
SRS TruSurround
TruSurround is a virtualizer giving a surround sound effect
with only two speakers (422). It can be used alternatively
to VDS. TruSurround makes use of a passive matrix which
delivers internally L, R, C and S signals. The virtualizer
then generates a new L, R stereo signal from it to achieve
a surround sound effect.
Pseudo Hall/Matrix
Because Dolby Pro Logic encoded signals are
transmitted not very often a Pseudo Hall and Pseudo
Matrix function is provided.
In case of Pseudo Hall the sum signal (L+R)/2 is passed to
the centre and to the surround channel whereas for
Pseudo Matrix the centre channel carries (L+R)/2 and the
surround channel (L-R)/2. The surround signal is delayed
by 30ms in both cases.
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CONFIDENTIAL

I-Mono or Extended Pseudo Stereo (EPS)
The Incredible Mono module (I-Mono) generates two
channels from one mono input signal. When the sound of
the mono input signal is processed, the listener gets the
impression that the sound is essentially a stereo signal.
The pseudo stereo effect is adjustable. Additionally the
user can switch this function ON or OFF.
I-Stereo or Extended Spatial Stereo (ESS)

The I-Stereo module is a Stereo Expander. The listener
gets the impression of a sound reproduced by two virtual
speakers, positioned at a larger distance between each
other than between the actual speakers. So, the stereo
image is expanded by this widening sound effect.
The stereo widening effect is adjustable. Additionally this
feature can be switched ON or OFF.
SRS 3D Stereo
At high volume the resulting loudness curve is flat,

because there is no need to boost high and low
frequencies at high sound pressure level. The loudness
boost becomes active, if the input volume is reduced below
the (adjustable) no attack threshold. The resulting gain
depends on the actual input volume level. Within a range
of 30dB below the no attack threshold the loudness
function gives an increasing boost of low and high
frequencies. If the input volume is reduced more than
30dB below the no attack threshold level then the
maximum loudness gain is reached and the loudness
curve for 30dB remains active. The maximum loudness
gain is +18dB at 20 Hz and + 4.5dB at 16 kHz.
The frequency where gain is not affected by the loudness
function is called no attack frequency. This no attack
frequency can be adjusted to 500 Hz or 1 kHz. This results
in different loudness curves, but the maximum gain at 20
Hz and 16 kHz remains the same.
Loudness is applied in the L, R and C channels.
3D Stereo retrieves the spatial information from any stereo

signal. It produces a larger sweet spot. A centre control
and a space control is provided.
Bass/Treble
Bass and treble functions are implemented in all four main
signal paths (L, R, C, S). The user is able to attenuate or
boost the bass and high frequency signals independently
within a range of -16dB to +15dB. The external resolution
(under user control) is defined to 1dB steps, whereas the
internal resolution (not under user control, 1/32dB steps) is
used to avoid pop noise. The internally used 1/32dB per
step leads to a maximum speed of amplitude change,
which is defined to 15.625dB/s. The corner frequency of
the bass function is fixed to 40 Hz and for the treble
function fixed to 12 kHz.
Loudness
The human ear listening curves (Fletcher-Munson
loudness contours) show, that the ears of a human are
less sensitive for low and high frequencies at low sound
pressure level (volume level). In general a loudness
function can be used to compensate the human ear
sensitivity loss at low volume levels.
Within a volume range of 30dB the loudness gain varies
with the total gain value of the volume stage. The loudness
curves are automatically adjusted to the volume level,
where the allowed input volume steps can be 1/8dB or
even smaller to avoid step-noise.
2003 Nov 11
UOCIII series
BBE
The BBE sound process offers 2 primary functions. First
it compensates the time delay over frequency of the
loudspeaker. Secondly it provides a dynamic, program
driven augmentation at the high and low frequency range.
Together it restores the transients of the studio signals.
This improves the brilliance and clarity of sound. When
BBE is selected either DUB or DBE function is disabled.
Bass-ManagemenT (BMT)
Every DPL sound IC, which has to be licensed by Dolby
Laboratories, must include a Bass ManagemenT (BMT,
also called bass redirection). The UOCIII (TDA120xxH)
bass redirection fulfils the different configuration modes
required by Dolby Laboratories.
In general the bass redirection is used to redirect the low
frequency components of the audio signal to loudspeakers
which are able to cope with such power-full low signals
(large speakers). In audio equipment all speakers may be
large, but in TV sets either the L and R speakers are large
or a sub-woofer is applied. Thus a bass redirection can be
done to the L and R large speakers or to the sub-woofer.
The low frequency components are cut out of the audio
signals, which are directed to satellite loudspeakers (small
speakers); on the other hand, the high frequency
components are cut out of the audio signals, which are
redirected to the sub-woofer.
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CONFIDENTIAL

The corner frequency of the high and complementary low
pass filters can be selected, to allow specific adjustments
with respect to the used TV set loudspeakers. The corner
frequency of the LP / HP- filters is adjustable within a range
from 50 Hz to 400 Hz. There are 16 different corner
frequencies to choose from: 50Hz, 60Hz, 70Hz, 80Hz,
90Hz, 100Hz, 110Hz, 120Hz, 130Hz, 140Hz, 150Hz,
200Hz, 250Hz, 300Hz, 350Hz and 400Hz.
The bass redirection (BMT) covers three different
configuration modes:
As the bass redirection stage will be also used in other
applications including Dolby Digital the Dolby Digital
implementation of BMT is used within UOCIII as a basis.
BMT1 covers the bass management described as
configuration 1 (see Dolby Digital Specification Issue 3,
Figure 4-21 Configuration 1). The BMT1 mode is used to
redirect the low frequency components of all three front
channels (left, right and centre) to a separate sub-woofer
loudspeaker. As mentioned within the Dolby specification
for Dolby Pro Logic, the surround channel is not
redirected. This can be done because surround is already
frequency band limited from 200 Hz to 7 kHz. If UOCIII is
used in non-Dolby stereo in the pseudo hall (M/ST Hall) or
pseudo matrix mode (M/ST Matrix), then also the surround
channel is filtered and redirected.
2003 Nov 11
UOCIII series
BMT2 is equivalent to the bass management described as
configuration 2 (see Dolby Digital Specification Issue 3,
Figure 4-22 Configuration 2). The BMT2 mode is used to
redirect the low frequency components of the centre
channel to the full-range main loudspeakers (large left and
right speakers). Additionally a separate sub-woofer
loudspeaker can be used in this configuration. Like in
BMT1 mode the surround channel is not redirected if
UOCIII is used in non-Dolby stereo in the pseudo hall
(M/ST Hall) or pseudo matrix mode (M/ST Matrix), then
also the surround channel is filtered and redirected.
The BMTOFF mode is used if no redirection of the low
frequency components is needed, in case of all three front
loudspeakers (left, right and centre) are large
loudspeakers.
There is an option to switch off the low path filter, which is
located in the sub-woofer output path. This non-processed
sub-woofer mode can be used with BMT1 and BMT2, and
gives the possibility to use an external sub-woofer filter.
As recommended by Dolby Laboratories, the UOCIII
always uses the HP-filter located in the surround channel
when DPL is active.
The figure 47 gives a general overview about the UOCIII
bass redirection (BMT).
149
CONFIDENTIAL

UOCIII series
BMT1, single woofer system with improved

filtering : small speakers for L, R, C, S; extra SW(subwoofer)
BMT2 , normal center mode with bass splitter (DPL) : large speakers for L, R; small speaker C, S ; SW optional
BMOFF , wide center mode (DPL) : large speakers for L, R, C ; small speaker S
BMT1 BMT2 BMOFF

gain/dB
b1
b2
b3
a1
R
a2
C
a3
-10dB
b4
a4
-10
-10
-10
-10
-100
-100
-100
-4.5
-4.5
-100
-100
-100
-100
-100
-100
S1
S2
b
a
a
b
b
a
HP
HP
HP
HP
flat
flat
HP
HP
flat
flat
flat
flat
filter
b1
b2
b3
b4
LP
b
S1
b
a
a1
a2
a3
a4
a4*
S2
1)
SW
LP
a
*) If DPL is active a4* is used.

1) LP filter can be switched flat, to allow
the use of external sub-woofer filtering.
Overview of the Hercules Bass-Redirection
Fig.47 Overview of the UOCIII Bass-Redirection
Equaliser
A graphic equaliser is implemented in the L, R and C
channel. It provides five bands at 100, 300 1000, 3000 and
8000 Hz. For every band the gain is adjustable from -12 dB
to +12 dB in steps of 1 dB.
Dynamic Ultra Bass (DUB) or Dynamic Bass Boost

(DBB)
In general the DUB function is used in TV-Sets with small
speakers that cannot reproduce deep bass signals. The
effect is caused by producing harmonics of the low
frequency content. It gives the impression of deep bass
reproduction although the fundamentals are missing. The
level of harmonics added to the original signal is made
dependent from the total signal level at the output. This
dynamic behaviour allows a strong amplification of the
harmonics for small volume signals, but only small
amplification for high volume signals. Maximum gain and
the target output level could be set.
2003 Nov 11
The acoustical behaviour of this feature has to be tuned to

the TV internal loudspeaker set. Therefore a certain set of
filter coefficients has to be found for each used TV set.
This is done by use of the loudspeaker characteristics as
well as by listening tests. This coefficient set has to be
loaded into the UOCIII once after power on reset. A method
to calculate the coefficients will be available.
DUB is normally applied to the left and right speakers.
Alternatively it can be provided with different coefficients to
the sub-woofer signal to enhance the bass reproduction.
When using DUB it is not possible to apply DBE or BBE.
Dynamic Bass Enhancement (DBE) or Dynamic Virtual

Bass (DVB)
The DBE function is used in TV-sets equipped with large
speakers or sub-woofer system. This feature produces a
level depending bass boost. The dynamic behaviour
allows a strong bass amplification for small volume
signals, but only small bass amplification for high volume
150
CONFIDENTIAL

UOCIII series
signals. Q-factor of the boosting filter, maximum gain and

the target output level can be set.
input signal of the stage is multiplied with zero. So the

output carries digital silence.
This function has to be tuned to the speakers used within

a certain TV-set. The coefficients for the filters as well as
the parameters for the bass boost control have to be
stored into the UOCIII once after power on reset. A method
to find the best coefficients and parameters for a certain
TV-set will be available.
Each channel has an independent soft mute stage.

Additionally a MAINMUTE is available that provides a
common mute of the left and right signal of the main
channel. It overrules when it is activated the MAINLMUTE
and MAINRMUTE settings.
DBE is applied to the left and right speakers or

alternatively with different coefficients to the sub-woofer.
When using DBE it is not possible to provide DUB or
BBE.
EcoSUB (Economic Subwoofer Mode)

EcoSUB (Economic Subwoofer Mode) allows to drive a
subwoofer without an additional power amplifier. The
subwoofer signal will be added differentially to MAIN L, R.
By the use of some passive filter components the
subwoofer can be driven differentially by the MAIN L, R
power amplifier. This mode should be combined with the
Bass Redirection in Configuration 1.
Master Volume and Trim
Beeper
The beeper is a sine wave generator for frequencies from
200Hz to 12.5kHz at a sample rate of 32kHz. The level can
be set between 0dBFS and 83dBFS. A Mute/off step is
available. The signal is mixed into the left and right
channels for the main loudspeakers.
If the beeper is not used it needs to be set to the Mute/off
state.
Mono Signal (L+R)/2

The L and R signals of the MAIN channel are added at the
end of the channel giving (L+R)/2. This signal can be
provided to outputs for specific applications.
Audio Monitor
Master volume control is applied to all speaker channels in

a range from 24dB to 83dB gain. Step width is 1/8 dB. A
mute step is available. Trim can be set in 1dB steps with
internal resolution (not under user control) of 1/8 dB. The
range is the same as for volume control. Maximum speed
of change is 62.5dB/s.
The three-stage gain element per channel is controlled via
the common master volume register and the respective
trim registers. The requested gain values are added
internally. Total gain is limited to +24dB.
Volume and Balance

Stereo channels have separate gain elements in the left
and right branch. In the MAIN channel the L, R trims are
used. Shift to the right is done by attenuation of the L trim,
shift to the left by attenuation of the R trim.
In the AUX channels the same is performed by use of
volume left and right.
The audio monitor is able to monitor the level of the sum

(A+B)/2, the left or right signal of all input channels of the
digital input crossbar. A special setting is the (A-B)/2 mode
in the digital matrix that offers the possibility to identify a
signal as a mono or stereo signal. Additionally a variety of
test points in the DEMDEC and audio processing are
selectable.
The audio monitor provides three different modes:
Last sample: in this mode the level of the last sample
from the selected input is stored in the monitor register,
Peak detection: in this mode the peak level after the last
read command is stored in the monitor register,
Quasi peak detection: a quasi peak detector with an
attack time of 4ms and a decay time of 1s is applied.
If the monitor is used for mono/stereo detection the quasi
peak mode should be selected.
This needs to be programmed by the set maker.
The read transfer rate via control bus is limited to about

15kHz.
Soft Mute
When soft mute is activated/disabled the gain is

reduced/increased any 2ms by one of totally 32 steps
according to a cosine function. Thus it takes 64ms from
maximum gain to mute or vice versa. When muted the
The digital output crossbar provides 10 selectors one out

of 12. That means each of the outputs e.g. DAFO1 or
I2S1L can be connected to each of the inputs e.g. MAIN L
or C etc. By this the setmaker is free to assign the outputs
2003 Nov 11
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CONFIDENTIAL

UOCIII series
DAFO1 to DAFO2 and I2S1L, I2S1R, I2S2L, I2S2R to any

of the L, R, SW, C, S speakers or other destinations
according to his specific application.
"Static Volume Mode" - In this mode the master volume +

trim gain is limited to a maximum gain of -30dB. The trim
and the volume/balance in the Aux1-3 are not affected.
The channels AUX1 to AUX2 may be connected to the I2S

outputs. Channel AUX3 normally has to be passed to
output DAC1. Each output can also be connected to a
silence signal from the NOISE/SILENCE Generator.
"Static Control Mode" - In this mode the bass, treble and

equaliser gain is limited to a maximum of +8dB. The
Volume plus Trim setting is limited to -1dB.
Auxiliary Channels
The channels AUX1 to AUX3 have volume/balance
processing and soft mute and can be assigned to outputs
I2S1, I2S2 or DAC1 respectively.
Clip Management
The clip management is a feature that should prevent
automatically internal clipping. Internal clipping can take
place if in combination bass, treble or equaliser settings
introduce large amplification of the signal. To prevent
clipping different strategic ways are possible. Therefore 4
different modes are defined.
"Dynamic Control Mode" - In this mode the master volume

and trim gain is limited to +3dB. If the master volume plus
trim setting exceeds -12dB the bass and treble are
reduced until the sum of amplification of bass and treble
plus master volume and trim is less then +3dB. If master
volume and trim is in the controlrange between -12dB and
+3dB every 1dB more master volume plus trim results in
1dB less bass and treble.
"Dynamic Volume Mode" - In the dynamic volume mode
the main left and right signal is measured. If the internal
signal exceeds a limit of -3dBFS for a longer time, the
master volume is reduced automatically until the
measured signal is lower -3dBFS.
Table 258 Clip Management

CLIP MANAGEMENT MODE
Static Volume Mode
Static Control Mode
Dynamic Control Mode
Dynamic Volume Mode
MASTER VOLUME + TRIM

limited to -30dB
limited to -1dB
limited to +3dB
Reduced / limited until the signal
is smaller or equal -3dBFS
BASS
TREBLE
LOUDNESS
not affected
not affected
not affected
limited to +8dB limited to +8dB none attack level 0dB
see Fig. 48
none attack level 0dB
not affected
not affected
none attack level 0dB
Bass/Treble
active
+15dB
-12dB Master Volume

+Trim
+10dB
-7dB Master Volume

+Trim
+5dB
-2dB Master Volume

+Trim
0dB
+3dB Master Volume

+Trim
-16dB
-16dB
0dB
+15dB
Bass/Treble
selected
Hercules Clip Management/ Dynamic Control Mode
Fig.48 Clip management / Dynamic Control Mode
Power On / Reset Condition of the Sound DSP

After a power on or reset all DSP-RAM cells will be cleared. Afterwards all module defined memory spaces will be initialised
and the Control-Register values will be set to the default value. This value is called 'Default@INIT' in the control table.
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ANALOG AUDIO PROCESSING
UOCIII series
The following is only applicable for Japanese LSB justified
formats:
Audio DAC
The input circuitry is limited in handling the number of

SCK pulses per WS level. The maximum allowed
number of bitclocks per WS is 64(per mono audio word
32 bitclocks). Also the number of bitclocks during the low
and high phase of WS must be equal or more than the
selected format (24 bits).
The TV Sound Processor contains four single DACs. Each

of the low-noise high-dynamic range DACs consists of a
switched resistor architecture with interpolation filter and
noise shaper at the input that runs at an oversampling
frequency of 128fs. The outputs are fed into the
videoprocessor.
Audio ADC
TV Sound Processor contains two single audio ADCs. This
single ADC consists of one bitstream 3rd-order
sigma-delta audio ADC and a high -order decimation filter.
Input is supplied from the videoprocessor.
When the output is enabled, the serial audio data can be

taken from pin SDO. Depending on the signal source,
switch and matrix positions, the output can be either mono,
stereo or dual language sound on either output.
All inputs and the output work with the same sampling
frequency FS, formats and word sizes.
The number of significant bits is 24. The number of
significant bits on the output is 24.
DIGITAL AUDIO INTERFACE

General Description
The TV Sound Processor provides a digital stereo input
interface and two stereo output interfaces.
I2S-bus master input interfaces for one stereo channel at
a sampling rate of Fs=32kHz.
I2S-bus master output interfaces for two stereo channels
at a sampling rate of Fs=32kHz.
Three serial audio formats are supported at the Audio multi
channel I2S interface:
Philips IIS format
Sony IIS format
Japanese LSB justified format 24-bits
The differences of the formats are illustrated in the figures
49, 50 and 51.
In the Philips and Sony formats the left audio channel of a
stereo sample pair is output first and is placed on the serial
data line (SDI for input, SDO for output) when the word
select line (WS) is LOW. Data is written at the trailing edge
of SCK and read at the leading edge of SCK. The most
significant bit is sent first.
The serial data inputs are active at all times, independent

of the serial data outputs being on or off. When the serial
data outputs are off (either after power-up or via the
appropriate I2C-bus command) serial data and clocks WS
and SCK from a separate digital audio source can be fed
into the TV Sound Processor, be processed and output in
accordance with internal selector positions, provided that
the following criteria are met:
The number of bitclock (SCK) pulses may vary in the
application. When the applied word length is smaller than
24 bits, the LSB bits will be set to 0 internally. When the
applied word length exceeds 24 bits, the LSBs are
skipped.
The word select output is clocked with the audio sample
frequency at 32 kHz. The serial clock output (SCK) is
clocked at a frequency of 2.048 MHz. This means, that
there are 64 clock pulses per pair of stereo output
samples, or 32 clock pulses per sample. Depending again
on the signal source, the number of significant bits on the
serial data output SDO is 24. The SCK and WS clocks will
be generated by the TV Sound Processor, which is the
I2S-bus master.
In the Japanese LSB justified format the right audio

channel of a stereo sample pair is output first. The most
significant bit is sent first but data is LSB aligned to the
falling edge of the word select line (WS).
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UOCIII series
Possible Formats
PHILIPS IIS-FORMAT
SCK
SD
WS
MSB
LSB
MSB
LSB
24.Left
24.Right
MSB first / MSB justified / Justification bit is one bitclock delayed
: position fixed.
Fig.49 Philips IIS-Format

SONY IIS-FORMAT
SCK
SD
WS
MSB
LSB
MSB
LSB
24.Left
24.Right
: position fixed.
MSB first / MSB justified

Fig.50 Sony IIS-Format
JAPANESE FORMAT
SCK
SD
WS
MSB
LSB
MSB
24.Left
24.Right
: position fixed.
MSB first / LSB justified

Fig.51 Japanese Format
2003 Nov 11
LSB
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UOCIII series
I2C-BUS USER INTERFACE DESCRIPTION

Introduction
The UOCIII series is fully controlled via the I2C-bus. Control is exercised by writing data to one or more internal registers.
Status information can be read from a set of info registers to enable the controlling microcontroller determine whether
any action is required.
The TV sound processor has an own I2C-bus slave transceiver, which is independent from microcontroller I2C interface.
The specification of this I2C interface is according to the fast-mode specification, with a maximum speed of 400 kbits/s.
Information concerning the I2C-bus can be found in brochure I2C-bus and how to use it (order number
9398 393 40011). One slave address is available (see Table 259).
Table 259 Slave address
SLAVE ADDRESS A6 TO A0
1011000
In standby mode the clock for the soundpart will be switched off and the soundpart of UOCIII is not functional. So it cannot
be addressed via I2C.
The device will not respond to a general call on the I2C-bus, i.e. when a slave address of 0000000 is sent by a master.
Each address of the address space (see below) will be acknowledged, but in case of an illegal address the following data
will not be acknowledged and the transmission will be aborted. Sound function is not guaranteed if not released registers
are addressed!
Overview address space
The TV sound processor has 64k addresses, a space of 52 XRAM addresses is available for controlling purpose. These
registers are fully DSP software controlled. Other address space is used by internal processing and cannot be used via
I2C.
Here the overview, which addresses are available.
Table 260 Overview full address range
ADDRESS
WORDS
WORDLENGTH
Description
$0000 to $0033
52 words
3 bytes

usable
$0034 to $003F
12 words
3 bytes
I2C addresses enabled but

reserved. Not usable
$0040 to $FFFF
always disabled
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UOCIII series
Power-up state
Demodulator outputs are muted
At power-up or after a sleep awake the device is in the

following state:
IIS outputs are disabled
All outputs muted
Monitoring of carrier 1 FM demodulator output.
Beeper off
No sound carrier frequency loaded
All volumes are set to 0 dB and all outputs are muted.
After power-up a device initialization has to be performed

via the I2C-bus to put the UOCIII series into the proper
mode of operation. All reserved bits (i.e. not defined for this
IC) must be set to zero for the I2C protocol, to assure
compatibility to other ICs of the family.
All tone control (bass, treble, equalizer..) settings are

flat.
Overview Control Register Table
Source selectors of all audio channels are set to DEC

output.
The cluster name gives additional information in which

context the register will be used.
General-purpose I/O pins ready for input (HIGH)

All level adjusts are set to 0 dB (flat).
All effects (incredible sound, DPL, AVL) are off.

Table 261 Overview UOCIII I2C SSD Control Register Table
Read/
Write
Address
Register
Cluster
$001
INF_DEV_STA_REG
INFO
$002
INF_NIC_STA_REG
INFO
$003
INF_NIC_ADD_REG
INFO
$004
INF_LEV_MON_REG
INFO
$005
INF_MPX_LEVEL_REG
INFO
$006
INF_DC1_REG
INFO
$007
INF_SUBMAGN_REG
INFO
$008
INF_NOISELEVEL_REG
INFO
$009
INF_REVISION_ID_REG
INFO
W/R
$00A
DEM_CFG_REG
DEMDEC
W/R
$00B
DEM_CA1_REG
DEMDEC
W/R
$00C
DEM_CA2_REG
DEMDEC
W/R
$00D
DEM_MPXCFG_REG
DEMDEC
W/R
$00E
DEM_FMSUBCFG_REG
DEMDEC
W/R
$00F
DEM_OUT_CFG_REG
DEMDEC
W/R
$010
MAGDET_THR_REG
DEMDEC
W/R
$011
NMUTE_FMA2_SAP_REG
DEMDEC
W/R
$012
NMUTE_MPX_REG
DEMDEC
W/R
$013
NMUTE_EIAJ_REG
DEMDEC
W/R
$014
NICAM_CFG_REG
DEMDEC
W/R
$015
DDEP_CONTROL_REG
DEMDEC
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UOCIII series
Read/
Write
Address
Register
Cluster
W/R
$016
LEV_ADJ_DEM_REG
LEVEL ADJUST
W/R
$017
LEV_ADJ_IO_REG
LEVEL ADJUST
W/R
$018
ASW_MA_C_S_REG
AUDIO SWITCHING
W/R
$019
ASW_A1_A2_A3_REG
AUDIO SWITCHING
W/R
$01A
ASW_DAFO1_2_REG
AUDIO SWITCHING
W/R
$01B
ASW_DAC_I2S_OCO_REG
AUDIO SWITCHING
W/R
$01C
ASW_MUT_CON_REG
AUDIO SWITCHING
W/R
$01D
SOU_APP_MOD_REG
SOUND PROCESSING MODE
W/R
$01E
SOU_EFF_REG
SOUND EFFECTS
W/R
$01F
MAIN_SOU_EFF_REG
SOUND EFFECTS
W/R
$020
DBE_COEF_DOWNL_REG
SOUND EFFECTS
W/R
$021
DUB_COEF_DOWNL_REG
SOUND EFFECTS
W/R
$022
DOL_CON_REG
SOUND EFFECTS
W/R
$023
MASTER_VOL_REG
SOUND
W/R
$024
MAI_VOL_REG
SOUND
W/R
$025
SW_C_S_VOL_REG
SOUND
W/R
$026
AUX1_VOL_REG
SOUND
W/R
$027
AUX2_VOL_REG
SOUND
W/R
$028
AUX3_VOL_REG
SOUND
W/R
$029
MAI_TON_CON_REG
SOUND
W/R
$02A
CENTER_TON_CON_REG
SOUND
W/R
$02B
SUR_TON_CON_REG
SOUND
W/R
$02C
EQMAIN1_TON_CON_REG
SOUND
W/R
$02D
EQMAIN2_TON_CON_REG
SOUND
W/R
$02E
EQCENTER1_TON_CON_REG
SOUND
W/R
$02F
EQCENTER2_TON_CON_REG
SOUND
W/R
$030
MON_SEL_REG
MONITOR
W/R
$031
GEN_CTRL_REG
GENERAL CONTROL
W/R
$032
DCXO_CTRL_REG
DEMDEC
W/R
$033
DDEP_OPTIONS1_REG
DEMDEC
Slave receiver mode

As a slave receiver, the UOCIII series provides 42 XRAM registers for storing commands and data. Each register contains
up to 24 bit and can be accessed via so-called subaddresses. A subaddress is 16 bit long and can be thought of as a
pointer to an internal memory location. Due to the I2C-protocol subaddresses and data are transferred bytewise, so a
subaddress needs 2 and a data word 3 byte packets
Not used bits must be set to 0!!
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UOCIII series
2 modes are possible:

autoincrement: only first address must be transmitted from the master, following addresses will be internally calculated
by incrementing the start address
not autoincrement: every single address must be provided by the master
Table 262 Format for a transmission employing auto-increment of subaddresses

S
SLAVE
ADDR
A SUBADDR1 A SUBADDR0 A DATA...
A DATA...
A DATA...
DATA...
A P
Note
1. DATA...: n data bytes with auto-increment of subaddresses. 3 bytes are 1 dataword. After 3 bytes a new dataword
starts
Table 263 Explanation of previous table
BIT
FUNCTION
START condition
SLAVE ADDRESS
7-bit device address
data direction bit (write to device)
acknowledge by slave
SUBADDR1
Byte 1 (MSB) of write register address
SUBADDR0
Byte 0 (LSB) of write register address
DATA2
Byte2 (MSB) of data word to be written into register
DATA1
Byte1 of data word to be written into register
DATA0
Byte0 (LSB) of data word to be written into register
STOP condition
It is allowed to send more than one data word per transmission to the UOCIII series. In this event, the subaddress is
automatically incremented after each data word, resulting in storing the sequence of data words at successive register
locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte is acknowledged with
A (acknowledge) if address is valid and data byte is properly stored, otherwise a NA (not acknowledge) occurs and aborts
the transmission.
There is no wrap-around of subaddresses.
Commands and data are processed as soon as a data word has been completely received. If the transmission is
terminated (STOP condition) before all bytes of a word have been received, the incomplete data for that function are
ignored.
Data patterns sent to the various subaddresses are not checked for being illegal or not at that address.
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UOCIII series
Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. The last operation will
not then be executed.
For each address the data word starts with the most significant byte->most significant bit.
Slave transmitter mode
As a slave transmitter, the UOCIII series provides 9 registers with status information and data. These registers can be
accessed by means of subaddresses.
Besides these read registers all write registers are readable too.
The autoincrement mode is also applicable.
Table 264 General format for reading data from the SSD part of the UOCIII series
S
SLAVE ADDR
DATA2
SUBADDR1
SUBADDR0
Sr
DATA1
DATA0
NAm
SLAVE ADDR
Table 265Explanation of previous table

BIT
FUNCTION
START condition
SLAVE ADDRESS
7-bit device address
data direction bit (write to device)
acknowledge by slave
SUBADDR1
Byte 1 (MSB) of read register address
SUBADDR0
Byte 0 (LSB) of read register address
Sr
repeated START condition
data direction bit (read from device)
DATA2
Byte2 (MSB) of data word to be read from register
DATA1
Byte1 of data word to be read from register
DATA0
Byte0 (LSB) of data word to be read from register
NAm
not acknowledge (by the master)
Am
acknowledge (by the master)
STOP condition
Reading of data can start at any valid subaddress. It is allowed to read more than 1 data word per transmission from the
UOCIII series. In this situation, the subaddress is automatically incremented after each data word, which results in
reading the sequence of data bytes from successive register locations, starting at SUBADDRESS.
Each data byte in a read sequence, except for the last one, is acknowledged with Am (acknowledge by the master).
If an attempt is made to read from a non-existing subaddress, the device will send a data pattern of all ones, i.e. FF in
hexadecimal notation.
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UOCIII series
Detailed Control Register Table

Each absolute HEX address is mapped to one register name. The register name gives some information in mnemo like
manner. The cluster name is omitted as column but occurs as header in the column REGISTER in the detailed table,
(see overview table). Not mentioned bit indices are reserved and must be zero.
Table 266 Detailed SSD I2C read + write control register table
ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
Data bits
Reset
value
DETAILLED INFO($= HEX values)
INFO
$001
INF_DEV_STA_REG
2003 Nov 11
STDRES
[4..0]
standard detection result (ASD mode), or selected

standard in SSS mode
0 = failed to find any standard
1 = B/G (still searching, SC2 not (yet) found)
2 = D/K (still searching, SC2 not (yet) found)
3 = M (still searching, no ident or pilot found)
4 = B/G A2
5 = B/G NICAM
6 = D/K A2 (1)
7 = D/K A2 (2)
8 = D/K A2 (3)
9 = D/K NICAM
10 = L NICAM
11 = I NICAM
12 = M Korea
13 = M BTSC
14 = M EIAJ
15 = FM Radio, IF = 10.7 MHz, 50 us deemphasis
17 = FM Radio, selectable IF, 50 us deemphasis
31 = still searching for a standard (can occur only
during a few milliseconds)
GST
[5]
general stereo flag (ident source determined by

currently detected or selected standard)
$0 = No stereo mode
$1 = Stereo mode detected
GDU
[6]
general dual flag

$0 = No dual mode
$1 = Dual mode detected
APILOT
[7]
A2 or EIAJ pilot tone detected

$0 = False
$1 = True
ADU
[8]
A2 or EIAJ ident dual flag

$0 = False
$1 = True
AST
[9]
A2 or EIAJ ident stereo flag

$0 = False
$1 = True
AAMUT
[10]
SC2 (if A2 mode) or EIAJ subchannel muted due

to noise
$0 = False
$1 = True
160
CONFIDENTIAL

ABS.
ADDR.
HEX
$002
REGISTER
INF_NIC_STA_REG
2003 Nov 11
R/W
Bitfield Name
Data bits
UOCIII series
Reset
value
BPILOT
[11]
BTSC or FM radio pilot tone detected (stereo indicator)

$0 = False
$1 = True
SAPDET
[12]
SAP carrier detected

$0 = False
$1 = True
BAMUT
[13]
BTSC stereo muted due to noise (if noise detector

enabled)
$0 = False
$1 = True
SAMUT
[14]
SAP muted due to noise (if noise detector

enabled)
$0 = False
$1 = True
VDSP_C
[15]
NICAM decoder VDSP flag

$0 = DATA or undefined format
$1 = SOUND
NICST_C
[16]
NICAM decoder stereo flag

$0 = False
$1 = True
NICDU_C
[17]
NICAM decoder dual flag

$0 = False
$1 = True
NAMUT
[18]
NICAM automute flag

$0 = not muted
$1 = muted (fallback to analog sound carrier)
RSSF
[19]
NICAM reserve sound switching flag (=C4), see

NICAM specification
$0 = analog sound carrier conveys different contents than NICAM carrier
$1 = analog sound carrier conveys same contents
as NICAM carrier (M1 if DUAL)
INITSTAT
[20]
initialization status (set to 0 upon read access)

$0 = no reset performed
$1 = reset has been applied to DSP and init routine has been executed
[23..21]
reserved
ERR_OUT
[7..0]
NICAM error counter: number of parity errors

found in the last 128ms period
CFC
[8]
NICAM ConFiguration Change

$0 = No configuration change
$1 = Configuration change at the 16 frame (CO)
boundary
CO_LOCKED
[9]
NICAM frame and CO synchronization

$0 = Audio output from NICAM part is digital
silence
$1 = Device has both frame and CO (16 frames)
synchronization
NACB
[13..10]
NICAM application control bits (see C1..C4 in

NICAM transmission)
VDSP
[14]
Identification of NICAM sound

$0 = DATA or undefined format
$1 = SOUND
161
CONFIDENTIAL

ABS.
ADDR.
HEX
$003
REGISTER
INF_NIC_ADD_REG
R/W
Bitfield Name
Data bits
UOCIII series
Reset
value
NICST
[15]
NICAM stereo flag

$0 = No NICAM stereo mode (= Mono mode if
NICDU = $0)
$1 = NICAM stereo mode
NICDU
[16]
NICAM dual mono mode

$0 = No NICAM dual mono mode (= Mono mode if
NICST = $0)
$1 = NICAM dual mono mode
reserved
[23..17]
ADW
[10..0]
NICAM additional data word (11 bit per frame)
[16..11]
reserved, must be written as 0
DCXOCAPS
[23..17]
DCXO capacitor bank control signal (not yet implemented in PICASSO-100 N1)
$004
INF_LEV_MON_REG
MONLEVEL
[23..0]
monitor level
$005
INF_MPX_LEVEL_REG
[5..0]
reserved
MPXPLEV
[23..6]
MPX pilot level
$006
INF_DC1_REG
SC1_DC
[23..0]
DC offset from FM demodulator channel 1
$007
INF_SUBMAGN_REG
SUBMAGN
[23..0]
magnitude of FM subchannel
$008
INF_NOISELEVEL_REG R
NDETCH_STAT [0]
status noise detector channel

0 = channel 1
1 = channel 2
NDETPB_STAT [1]
status noise detector passband

0 = low (2.5 fh)
1 = high (7.5 fh)
NOISELEVEL
$009
INF_REVISION_ID_RE
G
2003 Nov 11
[23..2]
noise detector output
MAJOR_VERSI [3..0]
ON_NR
major version number.
MINOR_VERSI [7..4]
ON_NR
minor version number.

incremented number means: control interface may
have extensions for additional functions or functionality may have changed slightly; driver update
recommended.
PATCH_LEVEL [11..8]
patch level number.

incremented number indicates bugfixes of the
embedded software without any change of control
interface or functionality.
no driver update needed.
DEVICE_TYPE [15..12]
device type ID (internal use)
ROM_ID
ROM identification code. Unique number for every

ROM code ever released.
[23..16]
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CONFIDENTIAL

ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
Data bits
UOCIII series
Reset
value
DEMDEC
$00A
DEM_CFG_REG
2003 Nov 11
R/W
DECPATH
[2..0]
$0
decoder path selection

$0 = FM A2
$1 = FM SAT with adaptive deemphasis
$2= FM Radio
$3 = NICAM + FM mono
$4 = BTSC stereo + SAP with 150 us demphasis
$5= BTSC mono + SAP with dbx
$6 = EIAJ stereo
$7= BTSC stereo flat & SAP flat (test mode)
FMDEEM
[5..3]
$0
fixed deemphasis for analog sound signals (not

NICAM, not BTSC)
$0 = 50 us (Europe)
$1 = 60 us
$2 = 75 us (M standard)
$3 = J17
$4 = OFF (flat)
CH2MOD
[7..6]
$0
operating mode of demodulator channel 2

$0 = FM mode
$1 = AM mode
$2 = NICAM
$3 = not used
CH1MOD
[8]
$0
operating mode of demodulator channel 1

$0 = FM mode
$1 = AM mode
INITLPF
[9]
$0
initialize loop filters in demodulator

$0 = mormal operation
$1 = initialize (reset states to 0)
[10]
$0
FILTBW_M
[12..11]
$0
FM/AM demodulator filter bandwidth

$0 = narrow
$1 = extra wide (only ch. 1 active)
$2 = medium
$3 = wide
IDMOD_M
[14..13]
$0
FM ident speed
$0 = slow
$1 = medium
$2 = fast
$3 = off (reset)
IDAREA
[16..15]
$0
Area/regional code for FM-ident: Europe, Korea,

Japan
$0 = Europe
$1 = Korea
$2 = Japan
$3 = Japan
BPILCAN
[17]
$0
MPX pilot cancellation

$0 = False
$1 = True
FM_MPX
[18]
$0
input from demodulator hardware at 4*fs

$0 = FM / AM output
$1 = MPX demodulator output (for BTSC and FM
RADIO)
163
CONFIDENTIAL

ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
Data bits
UOCIII series
Reset
value
ID_DC_LEVEL
[20..19]
$0
DC level for IDENT pilot detection

$0 = Level > 3
$1 = Level > 4
$2 = Level > 5
$3 = Level > 6
ID_BYBPF
[21]
$0
bypass bandpass filter level detector

$0 = off
$1 = on (reduced IDENT sensitivity)
ID_PGAIN
[22]
$00
IDENT pilot bandpass gain

$0 = no gain
$1 = +6 dB gain for EIAJ
[23]
$0
$00B
DEM_CA1_REG
R/W
CARRIER1
[23..0]
$000000 sound carrier 1 (mixer 1) frequency

$5DC000 = 4.5 MHz
$729555 = 5.5 MHz
$7D0000 = 6.0 MHz
$876AAB= 6.5 MHz
$DEEAAB = 10.7 MHz
$00C
DEM_CA2_REG
R/W
CARRIER2
[23..0]
$000000 sound carrier 2 (mixer 2) frequency

$626AAB = 4.724 MHz
$77A100 = 5.742 MHz
$825F00 = 6.258 MHz
$79E000 = 5.85 MHz
$888000 = 6.552 MHz
$8C7665 = 6.742 MHz
$5DC000 = 4.5 MHz
$729555 = 5.5 MHz
$00D
DEM_MPXCFG_REG
R/W
[0]
$0
MPX_PLL_BW
[1]
$0
MPX demodulator pilot PLL bandwidth

$0 = 5Hz (default)
$1 = 10Hz
MPX_FREQ
[23..2]
$000000 MPX pilot frequency

$29F54 =15734 Hz (standard NTSC line frequency)
$29AAA = 15625 Hz (PAL line frequency)
$32AAA = 19000 Hz (FM radio)
FMSUB_BW
[0]
$000000 FM subchannel and EIAJ MAIN filter bandwidth

$0 = narrow
$1 = wide
EIAJ_DELAY
[2..1]
$000000 delay fine adjustment in MAIN path for EIAJ stereo
NDETCH
[3]
$000000 noise detector channel

$0 = channel 1
$1 = channel 2
NDETPB
[4]
$000000 noise detector passband

$0 = low (2.5 fh)
$1 = high (7.5 fh)
[7..5]
$0
$00E
$00F
DEM_FMSUBCFG_REG R/W
DEM_OUT_CFG_REG
2003 Nov 11
R/W
FMSUB_FREQ [23..8]
$000000 FM subchannel frequency (SAP or Japan)

$3437 = 5 fh for SAP
$14FB = 2 fh for EIAJ
DECSEL
$0
[1..0]
source for DEC output

$0 = MONO output
$1 = FM dematrix output
$2 = NICAM decoder output
164
CONFIDENTIAL

ABS.
ADDR.
HEX
$010
$011
$012
REGISTER
MAGDET_THR_REG
NMUTE_FMA2_SAP_R
EG
NMUTE_MPX_REG
2003 Nov 11
R/W
R/W
R/W
R/W
Bitfield Name
Data bits
UOCIII series
Reset
value
FMDEMAT
[4..2]
$0
FM dematrix
$0 = mono CH1
$1 = mono CH2
$2 = dual (identity matrix)
$3 = stereo Europe
$4 = stereo M standards (BTSC, Korea, Japan)
and FM Radio
MONOSEL
[5]
$0
source for MONO output

$0 = demod. channel 1
$1 = ADC ch.1 = left (external demodulator)
MUTE_DEC_M [6]
ONO
$1
mute DEC and MONO outputs (softmute)

$0 = no mute
$1 = mute
MUTE_SAP
[7]
$1
mute SAP output (softmute)

$0 = no mute
$1 = mute
[9..8]
$0
FM_SCALE
[11..10]
$0
scaling of FM and FM A2 signals

$0 = 27 kHz nominal FM deviation (Europe)
$1 = 15 kHz nominal FM deviation (M standards)
$2 = 0 dB gain (BTSC, EIAJ, FM Radio)
ANLG_SCALE
[23..12]
$400
expert mode: internal scaling coefficient for all

analog demodulator signals. 1024 means 0 dB.
MPX_PILOT_T
HR_UP
[3..0]
$3
upper threshold for MPX pilot detection (BTSC, FM

RADIO) in dB below nominal level
MPX_PILOT_T
HR_LO
[7..4]
$9
lower threshold for MPX pilot detection (BTSC, FM

RADIO) in dB below nominal level
SAP_CAR_TH
R_UP
[11..8]
$3
upper threshold for SAP carrier detection in dB

below nominal level
SAP_CAR_TH
R_LO
[15..12]
$6
lower threshold for SAP carrier detection in dB

below nominal level
[17..16]
$0
ASD_SC1_THR [22..18]
$0
threshold for detection of first sound carrier (SC1)

during ASD first step, relative to -30 dBFS. -16 prevents ASD "failure" to produce output regardless of
carrier level.
[23]
$0
NMUTE_SAP_
THR
[4..0]
$0
noise threshold for automute of SAP (-16 means

automute off)
NMUTE_SAP_
HYST
[8..5]
$4
hysteresis size [dB] for automute of SAP
NMUTE_SC2_
THR
[13..9]
$0
noise threshold for automute of SC2 in FM A2

standards (-16 means automute off)
NMUTE_SC2_
HYST
[17..14]
$4
hysteresis size [dB] for automute of SC2 in FM A2

standards
[23..18]
$0
NMUTE_BTSC [4..0]
_THR
$0
noise threshold for automute of BTSC stereo carrier (-16 means automute off)
NMUTE_BTSC [8..5]
_HYST
$4
hysteresis size [dB] for automute of BTSC stereo
NMUTE_FMRA [13..9]
_THR
$0
noise threshold for automute of FM RADIO stereo

carrier (-16 means automute off)
165
CONFIDENTIAL

ABS.
ADDR.
HEX
$013
$014
REGISTER
NMUTE_EIAJ_REG
NICAM_CFG_REG
R/W
R/W
R/W
Bitfield Name
DDEP_CONTROL_REG R/W
2003 Nov 11
Reset
value
Data bits
NMUTE_FMRA [17..14]
_HYST
$4
hysteresis size [dB] for automute of FM RADIO

stereo
$0
NMUTE_EIAJ_ [4..0]
THR
$0
noise threshold for automute of EIAJ FM subcarrier (-16 means automute off)
NMUTE_EIAJ_ [8..5]
HYST
$4
hysteresis size [dB] for automute of EIAJ FM subcarrier
EIAJ_CAR_TH
R_UP
[12..9]
upper threshold for EIAJ SUB carrier detection in

dB below nominal level
EIAJ_CAR_TH
R_LO
[16..13]
12
lower threshold for EIAJ SUB carrier detection in

dB below nominal level
EIAJ_CAR_DE
TECT
[17]
enable EIAJ SUB carrier detector

0 = sub carrier detector disabled
1 = sub carrier detector enabled
[23..18]
[23..18]
$0
ONLY_RELATE [0]
D
$0
reproduce only related NICAM on DEC output

(DDEP only)
$0 = false (NICAM whenever possible)
$1 = true (NICAM suppressed if RSSF=0)
[1]
$0
EXTAM
[2]
$0
fall back source in case of automute in standard L

(DDEP only)
$0 = channel 1 output (AM)
$1 = ADC output (external AM demodulator)
NICDEEM
[3]
$0
NICAM deemphasis (J17) (all modes)

$0 = ON
$1 = OFF
NIC_AMUTE
[4]
$0
NICAM auto mute function depending on bit error

rate (DDEP only)
$0 = ON
$1 = OFF
$64
NICAM lower error limit (DDEP only)
NICLOERRLIM [12..5]
$015
UOCIII series
NICUPERRLIM [20..13]
$C8
NICAM upper error limit (DDEP only)
[23..21]
$0
EPMODE
[1..0]
$0
DEMDEC Easy Programming (DDEP) mode

$0 = 'AUTOSTANDARD' (ASD). STDSEL[4:0]
defines the set of 'allowed' standards.
$1 = 'STATIC STANDARD SELECT' (SSS). STDSEL[4:0] contains standard code.
$2 = Reserved
$3 = DEMDEC expert mode (fully manual mode)
166
CONFIDENTIAL

ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
STDSEL
Data bits
[6..2]
UOCIII series
Reset
value
$0

Bits multiplexed for ASD and SSS modes.
In ASD mode (EPMODE=0): flags for allowed
standards B/G | D/K | L/L' | I | M (LSB to MSB).
In SSS mode (EPMODE=1): standard code as
defined in status register STDRES, e.g. code 4
selects B/G A2.
For details please consult the documentation.
4 = B/G A2
5 = B/G NICAM
6 = D/K A2 (1)
7 = D/K A2 (2)
8 = D/K A2 (3)
9 = D/K NICAM
10 = L NICAM / L'
11 = I NICAM
12 = M Korea
13 = M BTSC
14 = M EIAJ
2003 Nov 11
REST
[7]
$0
RESTART decoder and initialize DEMDEC after

channel switch, if changed from 0 to 1.
OVMADAPT
[8]
$1
FM overmodulation adaptation (avoids distortion,

filter bandwidth and gain is chosen adaptively)
$0 = disabled
$1 = enabled (recommended)
DDMUTE
[9]
$0
mute DEMDEC output signals (softmute)

$0 = no mute
$1 = mute
FILTBW
[11..10]
$0
FM/AM demodulator filter bandwidth (like

FILTBW_M). NOT effective if BTSC, EIAJ, FMRADIO active, or if OVMADAPT=1
$0 = narrow (recommended)
$2 = medium
$3 = wide
$1 = extra wide (only ch. 1 active)
IDMOD
[13..12]
$0
FM ident speed in SSS mode (otherwise not effective)

$0 = slow
$1 = medium
$2 = fast
$3 = off (reset)
[14]
$0
[15]
$0
SAPDBX
[16]
$0
SAP decompression mode

$0 = dbx used for BTSC stereo decoding, fixed
compromise deemphasis for SAP (recommended)
$1 = dbx used for SAP, BTSC stereo forced to
mono
FHPAL
[17]
$0
line frequency for BTSC decoding

$0 = NTSC line frequency (15.734 kHz) used in
SSS, or preferred in ASD mode
$1 = PAL line frequency (15.625 kHz) used in
SSS, or preferred in ASD mode
167
CONFIDENTIAL

ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
Data bits
UOCIII series
Reset
value
OVMTHR
[19..18]
$1
overmodulation level threshold relative to nominal

(applies if OVMADAPT=1)
$0 = +3 dB = -12 dBFS
$1 = +6 dB = - 9 dBFS (recommended)
$2 = +9 dB = -6 dBFS
$3 = +12 dB= -3 dBFS
[23..20]
$00
DECLEV
[4..0]
$00
level adjust DEC ( +15..-15dB)(-16 = MUTE)
MONOLEV
[9..5]
$00
level adjust MONO ( +15..-15dB)(-16 = MUTE)
NICLEV
[14..10]
$00
extra gain for NICAM ( +15..-15dB)(-16 = MUTE)"
SAPLEV
[19..15]
$00
Level adjust SAP ( +15..-15dB)(-16 = MUTE)
[23..20]
$0
ADCLEV
[4..0]
$00
level adjust ADC ( +15..-15dB)(-16 = MUTE)
IISLEV
[9..5]
$00
level adjust IIS ( +15..-15dB)(-16 = MUTE)
[23..10]
$00
MAINSS
[4..0]
$00
SIGNAL SOURCE MAIN

$00 = DEC
$01 = MONO
$02 = SAP
$03 = ADC
$04 = IIS
$05 = Noise Generator
$06 = Silence Generator
MAINDM
[7..5]
$0
DIGITAL MATRIX MAIN

$0 = AB [Stereo] (automatrix off)
$1 = (A+B)/2 [Mono] (automatrix off)
$2 = AA [Lang. A] (automatrix off)
$3 = BB [Lang. B] (automatrix off)
$4 = BA [Swap] (automatrix off)
$5 = not used
$6 = Language A (automatrix on)
$7 = Language B (automatrix on)
CENTERSS
[12..8]
$06
SIGNAL SOURCE CENTER

$00 = DEC
$01 = MONO
$02 = SAP
$03 = ADC
$04 = IIS
LEVEL ADJUST
$016
$017
LEV_ADJ_DEM_REG
LEV_ADJ_IO_REG
R/W
R/W
AUDIO SWITCHING
$018
ASW_MA_C_S_REG
2003 Nov 11
R/W
168
CONFIDENTIAL

ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
Data bits
SURROUNDSS [17..13]
$019
ASW_A1_A2_A3_REG
2003 Nov 11
R/W
UOCIII series
Reset
value
$06

SIGNAL SOURCE SURROUND
$00 = DEC
$01 = MONO
$02 = SAP
$03 = ADC
$04 = IIS
[23..18]
$00
AUX1SS
[4..0]
$00
SIGNAL SOURCE AUX1

$00 = DEC
$01 = MONO
$02 = SAP
$03 = ADC
$04 = IIS
AUX1DM
[7..5]
$0
DIGITAL MATRIX AUX1

$5 = not used
AUX2SS
[12..8]
$00
SIGNAL SOURCE AUX2

$00 = DEC
$01 = MONO
$02 = SAP
$03 = ADC
$04 = IIS
AUX2DM
[15..13]
$0
DIGITAL MATRIX AUX2

$5 = not used
AUX3SS
[20..16]
$0
SIGNAL SOURCE AUX3

$00 = DEC
$01 = MONO
$02 = SAP
$03 = ADC
$04 = IIS
169
CONFIDENTIAL

ABS.
ADDR.
HEX
$01A
$01B
REGISTER
ASW_DAFO1_2_REG
R/W
R/W
ASW_DAC_I2S_OCO_R R/W
EG
2003 Nov 11
Bitfield Name
Data bits
UOCIII series
Reset
value
AUX3DM
[23..21]
$0
DIGITAL MATRIX AUX3

$5 = not used
ASAFO1
[3..0]
$0
OUTPUT SELECTION for DAFO1 to DAC2L

$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
$C = digital silence
ASAFO2
[7..4]
$1
OUTPUT SELECTION for DAFO2 to DAC2R

$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
[23..8]
$0
ASDAC1L
[3..0]
$0
OUTPUT SELECTION for DAC1L

$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
170
CONFIDENTIAL

ABS.
ADDR.
HEX
2003 Nov 11
REGISTER
R/W
Bitfield Name
Data bits
UOCIII series
Reset
value
ASDAC1R
[7..4]
$1
OUTPUT SELECTION for DAC1R

$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
ASI2S1L
[11..8]
$0
OUTPUT SELECTION for I2S1L

$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
ASI2S1R
[15..12]
$1
OUTPUT SELECTION for I2S1R

$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
ASI2S2L
[19..16]
$0
OUTPUT SELECTION for I2S2L

$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
171
CONFIDENTIAL

ABS.
ADDR.
HEX
$01C
REGISTER
ASW_MUT_CON_REG
2003 Nov 11
R/W
R/W
Bitfield Name
Data bits
UOCIII series
Reset
value
ASI2S2R
[23..20]
$1
OUTPUT SELECTION for I2S2R

$0 = MAIN/L
$1 = MAIN/R
$2 = SUBWOOFER
$3 = CENTER
$4 = SURROUND
$5 = AUX1/L
$6 = AUX1/R
$7 = AUX2/L
$8 = AUX2/R
$9 = AUX3/L
$A = AUX3/R
$B = MAIN SUM
MAINMUT
[0]
$1
Softmute MAIN/L,R output

$0 = OFF
$1 = ON
MAINLMUT
[1]
$0
Softmute MAIN/L output

$0 = OFF
$1 = ON
MAINRMUT
[2]
$0
Softmute MAIN/R output

$0 = OFF
$1 = ON
SUBWMUT
[3]
$1
Softmute SUBWOOFER output

$0 = OFF
$1 = ON
CENTERMUT
[4]
$1
Softmute CENTER output

$0 = OFF
$1 = ON
SURROUNDMUT
[5]
$1
Softmute SURROUND output

$0 = OFF
$1 = ON
AUX1MUT
[6]
$1
Softmute AUX1 output

$0 = OFF
$1 = ON
AUX2MUT
[7]
$1

$0 = OFF
$1 = ON
AUX3MUT
[8]
$1

$0 = OFF
$1 = ON
[23..9]
$0
172
CONFIDENTIAL

ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
Data bits
UOCIII series
Reset
value
SOUND PROCESSING
MODE
$01D
SOU_APP_MOD_REG
R/W
EXEMODTAB
[0]
$0
Execute 'Mode Table'

After a transition from '0' to '1' the selected 'Mode
Table' is executed once. Afterwards it should be
cleared again.
(If ControlMode='0')
SNDMOD
[5..1]
$00
Sound Modes
$0 = Mono/Stereo (default)
$1 = Mono/Stereo (HALL)
$2 = Mono/Stereo (MATRIX)
$3 = DPL (normal Centre)
$4 = DPL (3 Stereo)
$5 = DPL (Phantom Centre)
$6 = VDS422
$7 = VDS423
$8 = SRS TruSurround (DPL)
$9 = Noise Sequencing
$A = SRS TruSurround (Passive Matrix)
CLIPMANAGE
[8..6]
$0
Clip Management
$0 = Clip management OFF (default)
$1 = Static Volume Mode
$2 = Static Control Mode
$3 = Dynamic Control Mode
$4 = Dynamic Volume Mode
$5 = Reserved
$6 = Reserved
$7 = Reserved
MAINSUBCTRL [9]
$0
Main/Subwoofer signal output control

$0 = Normal Subwoofer Mode
$1 = Economic Subwoofer Mode
EQBYPASS
[10]
$0
EQ enable for Main and Center channel

$0 = EQ bypass off
$1 = EQ bypass on
[23..11]
$0
$0
BBE Contour value
SOUND EFFECTS
$01E
SOU_EFF_REG
R/W
BBECONTOUR [3..0]
$0 = Min. bass boost

$F = Max. bass boost
BBEPROCESS [7..4]
$0
BBE Process value

$0 = Min. process
$F = Max. process
MAINLOUD
2003 Nov 11
[8]
$0
MAIN loudness
$0 = OFF
$1 = ON
173
CONFIDENTIAL

ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
Data bits
UOCIII series
Reset
value
MAINLONA
[11..9]
$0
MAIN loudness none attack volume level

$0 = -15dB Volume
$1 = -12dB Volume
$2 = -9dB Volume
$3 = -6dB Volume
$4 = -3dB Volume
$5 = 0dB Volume
$6 = +3dB Volume
$7 = +6dB Volume
MAINLOCH
[13..12]
$0
MAIN loudness filter characteristic (bass/treble in

dB)
$0 = standard (500Hz)
$1 = extra bass (1000Hz)
bass: 20 Hz -> max. 18.3 dB
treble: 16 kHz -> max. 4.3 dB
$01F
MAIN_SOU_EFF_REG
2003 Nov 11
R/W
BASSFEATURECTRL
[16..14]
$0
DBE, DUB and BBE control

$0 = DBE, DUB and BBE Off
$1 = DBE main channel On
$2 = DUB main channel On
$3 = DBE subwoofer channel On
$4 = DUB subwoofer channel On
$5 = BBE On
[23..17]
$0
SOMOCTRL
[1..0]
$0
Spatializer sound effect

0 = OFF
1 = I-Stereo
2 = I-Mono
3 = 3D Sound
INSOEF
[4..2]
$3
I-Mono or I-Stereo Effect: Min..Max (6 steps)

$0 = 1 (Min)
$1 = 2
$2 = 3
$3 = 4
$4 = 5
$5 = 6 (Max)
AVLMOD
[7..5]
$0
AVL mode
$0 = OFF
$1 = very short decay (20 ms)
$2 = short decay (2 sec)
$3 = medium decay (4 sec)
$4 = long decay (8 sec)
$5 = very long decay (16 sec)
AVLWEIGHT
[8]
$1
AVL weighting filter

$0 = OFF
$1 = ON (recommended)
AVLLEV
[12..9]
$7
AVL reference level (16 steps: -6,-8,... -36 dBFS)

$2 = high threshold (-10 dBFS), small reduction
("daytime mode")
$7 = medium threshold (-20 dBFS), medium
reduction ("evening mode")
$C = low threshold (-30 dBFS), strong reduction
("night mode")
174
CONFIDENTIAL

ABS.
ADDR.
HEX
$020
$021
$022
REGISTER
R/W
DBE_COEF_DOWNL_R R/W
EG
DUB_COEF_DOWNL_R R/W
EG
DOL_CON_REG
R/W
Bitfield Name
Data bits
UOCIII series
Reset
value
SRS3DCENTE
R
[16..13]
$1
SRS 3D Sound Center

$0 = -9dB
$1 = -14dB
$2 = -15dB
$3 = -16dB
$4 = -17dB
$5 = -18dB
$6 = -19dB
$7 = -20dB
$8 = -21dB
$9 = -22dB
$A = -23dB
$B = -24dB
$C = -25dB
$D = -26dB
$E = -27dB
$F = off
SRS3DSPACE
[20..17]
$0
SRS 3D Sound Space

$0 = -4dB
$1 = -5dB
$2 = -6dB
$3 = -7dB
$4 = -8dB
$5 = -9dB
$6 = -10dB
$7 = -11dB
$8 = -12dB
$9 = -13dB
$A = -14dB
$B = -15dB
$C = -16dB
$D = -17dB
$E = -18dB
$F = off
SRS3DBYPAS
S
[21]
$0
SRS 3D Sound bypass mode switch for test purpose

$0 = 3D Sound active
$1 = Bypass active
[23..22]
$0
DBEADR
[5..0]
$0
DBE coefficient address
[11..6]
$0
DBECOEF
[23..12]
$0
DBE coefficients
DUBADR
[7..0]
$0
DUB coefficient address
[11..8]
$0
DUBCOEF
[23..12]
$0
DUB coefficients
VDSMIXLEV
[2..0]
$0
VDS mix level: 0..100% (5 steps)

$0 = 0%
$1 = 20%
$2 = 40%
$3 = 60%
$4 = 80%
$5 = 100%
>$5 = reserved
2003 Nov 11
175
CONFIDENTIAL

ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
DPLDEL
Data bits
[7..3]
UOCIII series
Reset
value
$00

Dolby Prologic : Delayline values: 15..30 ms in 32
steps.
$00 = No delay
$01 = min. delay
$1F = max. delay
2003 Nov 11
BAMAMO
[9..8]
$0
Bass management mode

$0 = OFF (Wide Centre Mode)
$1 = TYP1 configuration (Normal Centre Mode)
$2 = TYP2 configuration (Normal Centre Mode)
BAMASUB
[10]
$0
Bass Management subwoofer filter control

$0 = Subwoofer filter Off
$1 = Subwoofer filter On
BAMAFC
[14..11]
$0
Bass management lowpass filtercharacteristics:

50 - 400Hz (in 4 Bit resolution)) cornerfrequency.
Highpass filter is 1/lowpass.
$0 = 50 Hz
$1 = 60 Hz
$2 = 70 Hz
$3 = 80 Hz
$4 = 90 Hz
$5 = 100 Hz
$6 = 110 Hz
$7 = 120 Hz
$8 = 130 Hz
$9 = 140 Hz
$A = 150 Hz
$B = 200 Hz
$C = 250 Hz
$D = 300 Hz
$E = 350 Hz
$F = 400 Hz
FLAT_7KHZ_FI [15]
LTER
$0
Dolby Surround ProLogic filter for test purpose

$0 = OFF
$1 = ON
B_TYPE_FLAT
[16]
$0
Dolby Surround ProLogic filter for test purpose

$0 = OFF
$1 = ON
ABALCFG
[17]
$1
Dolby Surround ProLogic autobalance for test purpose

$0 = OFF
$1 = ON
[22..18]
$00
DelayLineSwitch
[23]
$00
Shift the delay from the DLU to the XMEM

$0 = XMEM
$1 = DLU
176
CONFIDENTIAL

ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
Data bits
UOCIII series
Reset
value
SOUND
$023
MASTER_VOL_REG
R/W
MASTERVOL
[10..0]
$0
Master volume: (+24..-83.875dB, mute ), controls

MAIN, SW, C and S in 1/8dB steps
192 = +24.000 dB
191 = +23.875 dB
..
184 = +23.000 dB
..
0 = 0.000 dB
-1 = -0.125 dB
..
-671 = -83.875 dB
-672 = mute
BEEPVOL
[18..11]
$AC
Beeper volume: (0..-83dB, mute)

0 = 0 dB
-1 = -1 dB
..
-84 = mute
$024
MAI_VOL_REG
R/W
BEEPFREQ
[21..19]
$0
Beeper frequency: 200..12500 Hz

$0 = 200 Hz
$1 = 400 Hz
$2 = 1000 Hz
$3 = 2000 Hz
$4 = 3000 Hz
$5 = 5000 Hz
$6 = 8000 Hz
$7 = 12500 Hz
[23..22]
$0
MAINVOLL
[7..0]
$00
MAIN volume left: (+24..-83dB, mute)

24 = +24 dB
23 = +23 dB
..
-84 = mute
MAINVOLR
[15..8]
$00
MAIN volume right: (+24..-83dB, mute)

24 = +24 dB
23 = +23 dB
..
-84 = mute
$025
SW_C_S_VOL_REG
R/W
[23..16]
$00
SUBWVOL
[7..0]
$0
SUBWOOFER volume: (+24..-83dB, mute)

24 = +24 dB
23 = +23 dB
..
-84 = mute
2003 Nov 11
177
CONFIDENTIAL

ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
CENTERVOL
Data bits
[15..8]
UOCIII series
Reset
value
$0

CENTER volume: (+24..-83dB, mute)
24 = +24 dB
23 = +23 dB
..
-84 = mute
SURROUNDVOL
[23..16]
$0
SURROUND volume: (+24..-83dB, mute)

24 = +24 dB
23 = +23 dB
..
-84 = mute
$026
AUX1_VOL_REG
R/W
AUX1VOLL
[7..0]
$00
AUX1 volume left: (+24..-83dB, mute)

24 = +24 dB
23 = +23 dB
..
-84 = mute
AUX1VOLR
[15..8]
$00
AUX1 volume rigth: (+24..-83dB, mute)

24 = +24 dB
23 = +23 dB
..
-84 = mute
$027
AUX2_VOL_REG
R/W
[23..16]
$0
AUX2VOLL
[7..0]
$00

24 = +24 dB
23 = +23 dB
..
-84 = mute
AUX2VOLR
[15..8]
$00

24 = +24 dB
23 = +23 dB
..
-84 = mute
$028
AUX3_VOL_REG
R/W
[23..16]
$0
AUX3VOLL
[7..0]
$00

24 = +24 dB
23 = +23 dB
..
-84 = mute
AUX3VOLR
[15..8]
$00

24 = +24 dB
23 = +23 dB
..
-84 = mute
$029
MAI_TON_CON_REG
R/W
[23..16]
$0
MAINBASS
[4..0]
$00
MAIN bass: (+15..-16dB, 1 dB steps)

15 = +15 dB
..
-16 = -16 dB
2003 Nov 11
178
CONFIDENTIAL

ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
MAINTREB
Data bits
[9..5]
UOCIII series
Reset
value
$00

MAIN treble: (+15..-16dB, 1 dB steps)
15 = +15 dB
..
-16 = -16 dB
$02A
CENTER_TON_CON_R R/W
EG
[23..10]
CENTERBASS [4..0]
$0
$0
CENTERbass: (+15..-16dB, 1 dB steps)

15 = +15 dB
..
-16 = -16 dB
CENTERTREB [9..5]
$0
CENTERtreble: (+15..-16dB, 1 dB steps)

15 = +15 dB
..
-16 = -16 dB
$02B
SUR_TON_CON_REG
R/W
[23..10]
$0
SURROUNDBASS
[4..0]
$0
SURROUNDbass: (+15..-16dB, 1 dB steps)

15 = +15 dB
..
-16 = -16 dB
SURROUNDTREB
[9..5]
$0
SURROUNDtreble: (+15..-16dB, 1 dB steps)

15 = +15 dB
..
-16 = -16 dB
$02C
EQMAIN1_TON_CON_
REG
R/W
[23..10]
$0
EQCHM1
[4..0]
$0
Equalizer MAIN Channel Band 1 (100 Hz)

12 = +12dB
..
-12 = -12dB
EQCHM2
[9..5]
$0

12 = +12dB
..
-12 = -12dB
EQCHM3
[14..10]
$0

12 = +12dB
..
-12 = -12dB
$02D
EQMAIN2_TON_CON_
REG
R/W
[23..15]
$0
EQCHM4
[4..0]
$0

12 = +12dB
..
-12 = -12dB
EQCHM5
[9..5]
$0

12 = +12dB
..
-12 = -12dB
2003 Nov 11
[23..10]
$0
179
CONFIDENTIAL

ABS.
ADDR.
HEX
$02E
REGISTER
R/W
EQCENTER1_TON_CO R/W
N_REG
Bitfield Name
EQCHC1
Data bits
[4..0]
UOCIII series
Reset
value
$0

Equalizer CENTER Channel Band 1 (100 Hz)
12 = +12dB
..
-12 = -12dB
EQCHC2
[9..5]
$0

12 = +12dB
..
-12 = -12dB
EQCHC3
[14..10]
$0

12 = +12dB
..
-12 = -12dB
$02F
EQCENTER2_TON_CO R/W
N_REG
[23..15]
$0
EQCHC4
[4..0]
$0

12 = +12dB
..
-12 = -12dB
EQCHC5
[9..5]
$0

12 = +12dB
..
-12 = -12dB
[23..10]
$0
MON_SRC
[4..0]
$00
source for monitor function

$00 = FM,AM,MPX (1 fs) input
$01 = FM,AM,MPX (4 fs) input
$02 = FM/AM/BTSC/EIAJ DC
$03 = FM dematrix output (at DECSEL switch)
$04 = NICAM (at DECSEL switch)
$05 = MONO (at DECSEL switch)
$06 = DEC (at dig. input crossbar)
$07 = MONO (at dig. input crossbar)
$08 = SAP (at dig. input crossbar)
$09 = ADC (at dig. input crossbar)
$0A = IIS (at dig. input crossbar)
$0B = Noise / silence generator (at dig. input
crossbar)
$0C = MAIN (at dig. output crossbar)
$0D = SUBWOOFER (at dig. output crossbar)
$0E = CENTER (at dig. output crossbar)
$0F = SURROUND (at dig. output crossbar)
$10 = AUX1 (at dig. output crossbar)
$13 = MAIN SUM (at dig. output crossbar)
$14 = MAIN (after Bass Management)
$15 = SUBWOOFER (after Bass Management)
$16 = CENTER (after Bass Management)
$17 = SURROUND (after Bass Management)
MONITOR
$030
MON_SEL_REG
2003 Nov 11
R/W
180
CONFIDENTIAL

ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
UOCIII series
Reset
value
Data bits
MON_DET
[6..5]
$3
detection type for monitor function

$0 = random samples
$1 = absolute value peak detection
$2 = quasi peak detection
$3 = off / reset peak detector
MON_MAT
[9..7]
$0
matrix for monitor source

$0 = A
$1 = (A+B)/2
$2 = B
$3 = (A-B)/2 (2-ch. sources only)
[23..10]
$00
I2S_FORMAT
[1..0]
$0
IIS format control

$0 = Philips format
$1 = Sony format
$2 = Japanese 24 bit
$3 = Japanese 24 bit
DAC_DWA
[2]
$00
DAC: data weighted averaging

$0 = uni-directional, better THD at low levels
$1 = bi-directional
[23..3]
$00
NICLPINV
[0]
DCXO scaling control inverter

0 = not inverted
1 = inverted
NICLPSCALE
[3..1]
DCXO scaling control gain

0 = 1.0
1 = 0.125
2 = 0.250
3 = 0.375
4 = 0.500
5 = 0.625
6 = 0.750
7 = 0.875
NICLPLIM
[12..4]
511
DCXO scaling control limit (+/- limit), no clipping of

control signal if >= 256*scalefactor
GENERAL CONTROL
$031
GEN_CTRL_REG
R/W
DEMDEC
$032
$033
DCXO_CTRL_REG
R/W
DDEP_OPTIONS1_REG R/W
2003 Nov 11
NICLPCENTER [22..13]
DCXO scaling control center
[23]
[3..0]
IDMOD_SLOW [5..4]
_EUR
in ASD mode, IDMOD setting when European A2

standards (B/G, D/K) are detected
0 = slow
1 = medium
2 = fast
181
CONFIDENTIAL

ABS.
ADDR.
HEX
REGISTER
R/W
Bitfield Name
UOCIII series
Reset
value
Data bits
IDMOD_SLOW [7..6]
_KOR
in ASD mode, IDMOD setting when M Korea standard detected

0 = slow
1 = medium
2 = fast
IDMOD_SLOW [9..8]
_JAP
in ASD mode, IDMOD setting when EIAJ standard

detected
0 = slow
1 = medium
2 = fast
[18..10]
SAP_BW
[19]
SAP filter bandwidth selection

0 = narrow filter
1 = wide filter
[23..20]
Refresh cycle
Minimum refresh cycle period (worst case) can be calculated as follows:
Max 42 write registers with 3 datawords each. Each dataword consists of 8 databits + acknowledge bit. If auto increment
is applied 1 deviceaddress + 1 subaddress (2 Bytes) is additionally needed. So in total 43* 3 * 9 = 1161 Bits are needed
for one transfer. Assuming max. I2C speed (400 kbits/sec) a total time of 1/400k * 1161 = 2.9 msec is needed. So the
next transfer cycle (=refresh) cannot start earlier.
The following table is an extract of the full address range. Refresh procedure depends on automatic feature
(autostandard detection).
Table 267 Overview SSD I2C address range wrt. refresh cycle
Address
space
Refresh with DDEP mode
Refresh without DDEP
$0001-$0009
Read only
Read only
$000A-$000F
Yes
$0010-$0015
Yes
Yes
$0016-$0033
End refresh cycle
End refresh cycle
2003 Nov 11
182
CONFIDENTIAL

UOCIII series
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VP
supply voltage
5.5
VDDA
supply voltage (analogue)
0.5
3.6
VDDP
supply voltage (periphery)
0.5
3.6
VDDC
supply voltage (core)
0.5
1.95
VI
digital inputs
note 1
0.5
VDD+ 0.5 V
VO
digital outputs
note 1
0.5
VDD+ 0.5 V
IO
output current (each output)
10
mA
Tstg
storage temperature
25
+150
Tamb
operating ambient temperature
70
Tsol
soldering temperature
260
Tj
operating junction temperature
150
Ves
electrostatic handling
2000
+2000
+200
for 5 s
HBM; all pins; notes 2 and 3
MM; all pins; notes 2, 4 and 5 200

Notes
1. This maximum value has an absolute maximum of 5.5 V independent of VDD.
2. All pins are protected against ESD by means of internal clamping diodes.
3. Human Body Model (HBM): R = 1.5 k; C = 100 pF.
4. Machine Model (MM): R = 0 ; C = 200 pF.
5. All pins meet this requirement except pin 68 (VSScomb) which can handle a stress voltage of 150 V.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
thermal resistance from junction to ambient in free air (QFP-128)
VALUE
tbf
UNIT
K/W
QUALITY SPECIFICATION
In accordance with SNW-FQ-611E.
Latch-up
At an ambient temperature of 70 C all pins meet the following specification:
Itrigger 100 mA or 1.5VDD(max)
Itrigger 100 mA or 0.5VDD(max).
Note:
The SDA pin (pin 109 of the standard version or pin 20 of the face down version) does not meet this specification and
has a maximum trigger current of 20 mA. For the positive current it meets the requirement of 100 mA.
2003 Nov 11
183
CONFIDENTIAL

UOCIII series
CHARACTERISTICS OF MICRO-COMPUTER AND TEXT DECODER

VDD = 3.3 V 10%; VSS = 0 V; Tamb = 0 to +70 C; unless otherwise specified
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VM.1.1
supply voltage (VDDA)
3.0
3.3
3.6
VM.1.2
supply voltage (VDDP)
3.0
3.3
3.6
VM.1.3
supply voltage (VDDC)
1.65
1.8
1.95
VM.1.4
periphery supply current (IDDP)
note 1
mA
VM.1.5
core supply current (IDDC)
normal mode
440
tbf
mA
VM.1.6
supply current IDDA + IDDP
normal mode
28
tbf
mA
VM.1.7
stand-by mode
15
tbf
mA
VM.1.8
idle mode
tbf
mA
VM.1.9
power down mode
7.5
tbf
mA
Digital input/outputs
P0.0 TO P0.5, P1.0 TO P1.5, P2.0 TO P2.5 AND P3.0 TO P3.3
IO.1.1
low level input voltage
0.8
IO.1.2
high level input voltage
IO.1.3
hysteresis of Schmitt Trigger

input
0.4
IO.1.4
low level output voltage
IOL = 4 mA
0.4
IO.1.5
high level output voltage
open drain
3.3
IO.1.6
IOH = 4 mA; push pull
VDDE 0.4
IO.1.7
output rise time (push-pull only)

10% to 90%
load 40 pF
ns
IO.1.8
output fall time 10% to 90%
load 40 pF
ns
IO.1.9
load capacitance
100
pF
IO.1.10
capacitance of input pin
pF
2003 Nov 11
184
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
P1.6 AND P1.7 (OPEN DRAIN)

IO.2.1
low level input voltage (VIL)
0.8
IO.2.2
high level input voltage (VIH)
IO.2.3
hysteresis of Schmitt-trigger
input
0.4
IO.2.4
low level output voltage
0.4
IO.2.5
3.3
IO.2.6
P1.6; load 160 pF
180
ns
IO.2.7
P1.7; load 400 pF
140
ns
IO.2.8
bus load capacitance
400
pF
IO.2.9
capacitance of IO pin
pF
sink current 4 mA
Crystal oscillator
OSCIN; NOTE
X.1.1
resonator frequency
24.576
MHz
X.1.2
input capacitance (Ci)
tbf
pF
X.1.3
output capacitance (Co)
tbf
pF
X.1.4
Ri (crystal)
100
X1.5
maximum load capacitance
25
pF
Cx1 or Cx2 in Fig 52
Note
1. Peripheral current is dependent on external components and voltage levels on I/Os
2. The simplified circuit diagram of the oscillator is given in Fig.52.
A suitable crystal for this oscillator is the Saronix type 9922 520 20264.
2003 Nov 11
185
CONFIDENTIAL

UOCIII series
CHARACTERISTICS OF STEREO DECODER AND DIGITAL AUDIO PROCESSOR

VSIF(p-p) = 300 mV; AGCOFF = 0; AGCSLOW = 0; AGCLEV = 0; level and gain setting in accordance with note tbn;
VDD1,2,3 = 3.3 V;VDDA5 = 5.0 V; Tamb = 25 C; settings in accordance with B/G standard; FM deviation 50 kHz;
fmod = 1 kHz; FM sound parameters in accordance with system A2; NICAM in accordance with EBU specification; 1 k
measurement source resistance for AF inputs; unless otherwise specified;
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VSSC4
VDDC4
VDDA3
VDDA
GNDA
VDDA2
VDDC2
VSSC2
VDDC3
VSSC3
digital supply ground for

Audio-DAC
digital supply voltage for
Audio-DAC
analogue supply voltage for
Audio-DAC
Audio-ADC
analogue supply ground for
Audio-ADC
Audio-ADC
SIF-ADC
SIF-ADC
Audio-ADC
Audio-ADC
0.0
1.65
1.8
1.95
VREF_POS
3.3
3.6
-0.25
1.6
1.8
2.0
0.0
3.0
3.3
3.6
1.6
1.8
2.0
0.0
1.6
1.8
2.0
0.0
positive analog reference

voltage for SDAC LSL
negative analog reference
voltage for SDAC LSL+LSR
voltage for SDAC LSR+HPL
voltage for SDAC HPL+HPR
voltage for SDAC HPR
voltage for Audio-ADC
voltage for Audio-ADC
analog reference voltage for
Audio-ADC
0.8
3.3
3.6
0.0
0.8
3.3
3.6
0.0
0.8
3.3
3.6
3.0
3.3
3.6
0.0
References
VREF_POS
_LSL
VREF_NEG
_LSL+LSR
VREF_POS
_LSR+HPL
VREF_NEG
_HPL+HPR
VREF_POS
_HPR
VREFAD
_POS
VREFAD
_NEG
VREFAD
2003 Nov 11
VDDA2/2
186
CONFIDENTIAL

SYMBOL
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Demodulator performance;
THD + N
S/N
B3
total harmonic distortion plus

noise
signal-to-noise ratio
3 dB bandwidth
FR
frequency response
20 Hz to 14 kHz
cs(dual)
cs(stereo)
AM
dual signal channel separation

stereo channel separation
AM suppression for FM
S/NAM
AM demodulation
from FM source to any

output; Vo = 1 V (rms) with
low-pass filter
from NICAM source to any
output; Vo = 1 V (rms) with
low-pass filter
SC1 from FM source to any
output; Vo = 1 V (rms);
CCIR468; quasi peak
SC2 from FM source to any
output; Vo = 1 V (rms);
CCIR468; quasi peak
NICAM source;
Vo = 1 V (rms)
from FM source to any
output
from NICAM source to any
output
from FM or NICAM to any
output; fref = 1 kHz;
inclusive pre-emphasis and
de-emphasis
0.35
0.5
0.1
0.3
64
70
dB
60
66
dB
NICAM in accordance with

EBU specification; note tbn
14.5
15
kHz
14.5
15
kHz
dB
65
40
50
70
45
dB
dB
dB
45
dB
25
50
75
27
dBc
---------Hz
116.85
116.11
114.65
118.12
118.89
120.46
Hz
Hz
Hz
273.44
272.07
270.73
274.81
276.20
277.60
Hz
Hz
Hz
AM: 1 kHz,
30% modulation; reference:
1 kHz, 50 kHz deviation
2ndSIF level 100 mV (rms); 36
54% AM; 1 kHz AF;
CCIR468; quasi peak
IDENTIFICATION FOR FM SYSTEMS

modp
C/Np
fident
2003 Nov 11
pilot modulation for

identification
pilot sideband C/N for
identification start
identification window
B/G stereo
slow mode
medium mode
fast mode
B/G dual
slow mode
medium mode
fast mode
187
CONFIDENTIAL

SYMBOL
tident
PARAMETER
total identification time ON or
OFF
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
slow mode
medium mode
fast mode
2
1
0.5
s
s
s
output voltage at 0dBFS;

Vo = 1.0 V (rms); fi = 1 kHz;
bandwidth 20 Hz to 14 kHz;
output reference level
Vo = 1.0 V (rms); fi = 1 kHz;
CCIR468; RMS; from I2S to
D/A;
between any analog audio
signal pairs; fi = 1 kHz
between left and right of
any analog audio signal
pair
0.1
0.3
80
dB
70
dB
65
dB
Audio performance (D/A)

THD + N
total harmonic distortion plus

noise
S/N
ct
crosstalk attenuation
cs
channel separation
2003 Nov 11
188
CONFIDENTIAL

UOCIII series
CHARACTERISTICS OF TV-PROCESSOR
VP = 5 V; Tamb = 25 C; unless otherwise specified.
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
MAIN SUPPLY; NOTE 1
V.1.1
main supply voltage
V.1.2
digital supply voltage
V.1.3
audio supply voltage
note 2
note 3
4.7
5.0
5.3
3.0
3.3
3.6
4.7
8.0
8.4
V.1.4
main supply current (5 V)
190
mA
V.1.5
digital supply current (3.3 V)
mA
V.1.6
audio supply current (5.0/8.0 V)
0.5
mA
V.1.7
total power dissipation
980
mW
IF circuit
VISION IF AMPLIFIER INPUTS
input sensitivity (RMS value)
note 4
M.1.1
fi = 38.90 MHz
75
150
M.1.2
fi = 45.75 MHz
75
150
M.1.3
fi = 58.75 MHz
75
150
input resistance (differential)
note 5
note 5
M.1.4
M.1.5
input capacitance (differential)
pF
M.1.6
gain control range
64
dB
M.1.7
maximum input signal

(RMS value)
150
mV
PLL DEMODULATOR; NOTES 6 AND 7

M.2.1
Free-running frequency of VCO
PLL not locked, deviation

from nominal setting
500
+500
kHz
M.2.2
Catching range PLL
without SAW filter
MHz
M.2.3
delay time of identification
via LOCK bit
20
ms
VIDEO AMPLIFIER OUTPUT (IFOUT); NOTE 8

M.3.1
zero signal output level
M.3.2
negative modulation; note 9
3.6
positive modulation; note 9
1.4
M.3.3
top sync level
negative modulation
1.3
1.4
1.5
M.3.4
white level
positive modulation
3.4
M.3.5
difference in amplitude between

negative and positive modulation
15
M.3.6
video output impedance
50
M.3.7
internal bias current of NPN

emitter follower output transistor
1.0
mA
mA
MHz
M.3.8
maximum source current
M.3.9
bandwidth of demodulated
output signal
2003 Nov 11
at 3 dB
189
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VIDEO AMPLIFIER (CONTINUED)

M.3.10
differential gain
note 10
M.3.11
differential phase
notes 10 and 11
deg
M.3.12
video non-linearity
note 12
M.3.13
white spot clamp level
3.8
M.3.14
noise inverter clamping level
note 13
1.2
M.3.15
noise inverter insertion level

(identical to black level)
note 13
2.3
intermodulation
notes 11 and 14
Vo = 0.92 or 1.1 MHz
60
66
dB
Vo = 2.66 or 3.3 MHz
60
66
dB
Vo = 0.92 or 1.1 MHz
56
62
dB
Vo = 2.66 or 3.3 MHz
60
66
dB
M.3.16
blue
M.3.17
M.3.18
yellow
M.3.19
notes 11 and 15
M.3.20
weighted
56
60
dB
M.3.21
unweighted
49
53
dB
M.3.22
residual carrier signal
note 11
5.5
mV
M.3.23
residual 2nd harmonic of carrier note 11

signal
2.5
mV
VIDEO OUTPUT/INPUT (IFVO/SVO/CVBSI), CONTROLLED BY THE SVO1/SVO0 BITS; SEE NOTE 16

M.3.24
output signal amplitude

SVO1/SVO0 = 0/0 or 0/1
2.0
M.3.25
top sync level
SVO1/SVO0 = 0/0 or 0/1
0.5
M.3.26
output impedance
SVO1/SVO0 = 0/0 or 0/1
50
M.3.27
CVBS input voltage

SVO1/SVO0 = 1/0
1.0
1.4
M.3.28
input current
SVO1/SVO0 = 1/0
GROUP DELAY CORRECTION, SEE FIGURES 63 AND 64; NOTE 17

M.3.29
group delay sound trap only
at f=4.43MHz; sound trap

frequency 5.5 MHz
180
ns
M.3.30
group delay sound trap plus

group delay correction filter
at f=4.43MHz; sound trap

frequency 5.5 MHz
170
ns
-3 dB video bandwidth (sound

trap + group delay)
fSC1=4.5MHz
3.90
4.00
MHz
fSC1=5.5MHz
4.80
4.90
MHz
fSC1=6.0MHz
5.25
5.35
MHz
SOUND TRAP
M.3.31
fSC1=6.5MHz
M.3.32
2003 Nov 11
Attenuation at first sound carrier 4.5 and 5.5MHz

fSC1
6.0 and 6.5MHz
190
CONFIDENTIAL
5.70
5.80
MHz
30
36
dB
26
32
dB

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SOUND TRAP (CONTINUED)

M.3.33
Attenuation at second sound

carrier fSC2
f=4.726Mhz; fSC1=4.5MHz
21
27
dB
f=5.742MHz; fSC1=5.5MHz
21
27
dB
f=6.55Mhz; fSC1=6.0MHz
12
18
dB
18
24
dB
amplitude response at the colour f=3.58 MHz; fSC1=4.5 MHz

subcarrier frequency
f=4.43 MHz; fSC1=5.5 MHz
1.0
2.0
dB
1.0
2.0
dB
1.0
2.0
dB
1.0
2.0
dB
f=6.742MHz; fSC1=6.5MHz
M.3.34
IF AND TUNER AGC; NOTE 18
Timing of IF-AGC
M.4.1
modulated video interference
30% AM for 1 mV to 100 mV;

0 to 200 Hz (system B/G)
10
M.4.2
response time to IF input signal

amplitude increase of 52 dB
positive and negative

modulation
ms
M.4.3
response to an IF input signal

amplitude decrease of 52 dB
negative modulation
50
ms
positive modulation
100
ms
M.4.4
Tuner take-over adjustment (via
I2C-bus)
M.5.1
minimum starting level for tuner

take-over (RMS value)
0.4
0.8
mV
M.5.2
maximum starting level for tuner

take-over (RMS value)
50
150
mV
Tuner control output

M.6.1
max. tuner AGC output voltage
maximum tuner gain; note 5
M.6.2
output saturation voltage
minimum tuner gain; IO=2 mA
300
mV
M.6.3
maximum tuner AGC output

swing
1.0
mA
M.6.4
leakage current RF AGC
M.6.5
input signal variation for

complete tuner control
0.5
dB
AFC OUTPUT (VIA I2C-BUS); NOTE 19

M.7.1
AFC resolution
bits
M.7.2
window sensitivity
125
kHz
M.7.3
window sensitivity in large

window mode
275
kHz
10
ms
VIDEO IDENTIFICATION OUTPUT (VIA IFI BIT IN OUTPUT BYTE 00)

M.8.1
2003 Nov 11
delay time of identification after

the AGC has stabilized on a new
transmitter
191
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DVB IF, note 20

DVB IF AMPLIFIER INPUTS
VS.1.1
fi = 36/44 MHz
75
150
VS.1.2
note 5
VS.1.3
note 5
pF
VS.1.4
gain control range
64
dB
VS.1.5

(RMS value)
150
mV
43.008
MHz
I-MIXER, NOTE 21
VS.2.1
oscillator frequency; note
OFDM application
49.152
MHz
VS.2.2
maximum oscillator phase noise
106
dB
VS.2.5
lower limit passband
1.0
MHz
VS.2.11
VSB application
VS.2.6
upper limit passband
7.0
MHz
VS.2.7
passband ripple
0.5
dB
VS.2.8
stopband
29
MHz
VS.2.9
stopband attenuation
40
dB
EXTERNAL AGC CONTROL

VS.3.1
voltage range for full control of

the amplifier
VS.3.2
input impedance
MIXED DOWN OUTPUT SIGNAL

VS.4.1
output voltage (peak-to-peak

value)
VS.4.2
output impedance
25
VS.4.3
dc output level
2.0
QSS Sound IF circuit

SOUND IF AMPLIFIER
3 dB
Q.1.1
Q.1.3
Q.1.5
note 5
note 5
45
tbf
dBV
tbf
100
dBV
Q.1.6
pF
Q.1.7
gain control range
55
dB
Q.1.8
crosstalk attenuation between

SIF and VIF input
50
dB
2003 Nov 11
192
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SOUND IF INTERCARRIER OUTPUT; WITH AM = 0

Q.2.1
output signal amplitude (RMS

value)
Q.2.2
75
100
125
mV
bandwidth (-3 dB)
7.5
10
MHz
Q.2.3
residual IF sound carrier (RMS

value)
mV
Q.2.4
output resistance
300
Q.2.5
DC output voltage
2.0
Q.2.6
internal bias current of emitter

follower
1.0
mA
Q.2.7
maximum AC and DC sink

current
1.0
mA
Q.2.8
maximum AC and DC source

current
1.0
mA
Q.2.9
weighted S/N ratio (SC1/SC2). black picture

Ratio of PC/SC1 at vision IF
white picture
input of 40 dB or higher, note 22
6 kHz sinewave
(black-to-white modulation)
Q.2.10
Q.2.11
SC-1; sound carrier 2 off
53/48
58/55
dB
52/47
55/53
dB
44/42
48/46
dB
Q.2.12
250 kHz sine wave

(black-to-white modulation)
44/25
48/30
dB
Q.2.13
sound carrier subharmonics

(f=2.75 MHz 3 kHz)
45/44
51/50
dB
Q.2.14
sound carrier subharmonics

(f=2.87 MHz 3 kHz)
46/45
52/51
dB
AM SOUND OUTPUT; DEPENDING ON SETTING OF CMB0/CMB1 AND AM BITS

Q.3.1
AF output signal amplitude

(RMS value)
54% modulation
200
250
300
mV
Q.3.2
total harmonic distortion
54% modulation
1.0
2.0
Q.3.21
80% modulation
2.0
5.0
Q.3.3
AF bandwidth
3 dB
100
125
kHz
Q.3.4
weighted signal-to-noise ratio
54% modulation, weighted

with CCIR-1k filter, RMS SIF
level @ 80 dBV
45
dB
Q.3.5
DC output voltage
2.5
Q.3.6
power supply ripple rejection
20
dB
17
300
mVRMS
2nd Sound IF AGC circuit

2ND SOUND IF EXTERNAL INPUT, NOTE 23
Q.4.1
input voltage range
Q.4.2
input frequency range
note 24
4.5
10.7
MHz
Q.4.3
input resistance
note 5
25
Q.4.4
input capacitance
note 5
pF
2003 Nov 11
193
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
2ND SOUND IF AGC

Q.5.1
gain control range
24
dB
Q.5.2
charge current AGC pin
FM mode
12.5
Q.5.3
discharge current AGC pin
FM mode
50
Q.5.4
charge current AGC pin
AM mode
2.5
Q.5.5
AM mode
2.5
Q.5.6
overload condition
mA
26
30
dB
40
46
dB
mV
FM demodulator and audio pre-amplifier

FM-PLL DEMODULATOR
G.1.2
gain control range AGC amplifier
G.1.7
AM rejection
note 25
EXTERNAL SOUND IF INPUT (SSIF, WHEN SELECTED)

G.1.8
input limiting for lock-in of PLL

(RMS value)
G.1.9
input resistance
note 5
50
G.1.10
input capacitance
note 5
1.0
pF
notes 26 and 27
125
mV
DE-EMPHASIS OUTPUT
G.2.1
output signal amplitude (RMS

value)
G.2.2
output resistance
15
G.2.3
DC output voltage
2.5
G.2.31
signal-to-noise ratio (RMS value) note 28
50
dB
125
mV
AUDIO INPUT VIA DEEMPHASIS OUTPUT; NOTE 29

G.2.4
input signal amplitude (RMS

value)
G.2.5
input resistance
15
G.2.6
voltage gain between input and

output
dB
1.0
1.3
Vrms
Audio Selectors and Volume control

EXTERNAL AUDIO INPUTS; NOTE 30
A.1.1
A.1.11
maximum input voltage (RMS

value)
A.1.2
input resistance
A.1.3
gain from audio inputs to fixed

audio outputs (stereo versions)
A.1.41
5V audio supply
1.0
1.4
Vrms
24
32
DSG = 0
dB
DSG = 1
dB
gain from audio inputs to

AUDOUT output at maximum
volume (mono versions)
DSG = 0
dB
DSG = 1
12
dB
A.1.5
crosstalk between channels
5 V audio supply
tbf
dB
A.1.6
crosstalk between left and right
5 V audio supply
tbf
dB
A.1.31
A.1.4
2003 Nov 11
8V audio supply
194
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
FIXED AUDIO OUTPUTS (STEREO AND AV STEREO VERSIONS)

A.2.1
A.2.2
maximum output signal

amplitude (RMS value)
A.2.3
output impedance
A.2.4
A.2.5
A.2.6
A.2.7
frequency range
5V audio supply
1.0
Vrms
8V audio supply
2.0
Vrms
500
650
at +6 dBV
tbf
dB
at -54 dBV; A-weighted
tbf
dB
referred to +6dBV output

level; A-weighted
tbf
dB
20
15.000
Hz
5 V audio supply; note 31
250
350
450
mV
8 V audio supply; note 31
500
700
900
mV
500
2.2
ANALOGUE VOLUME CONTROLLED AUDIO OUTPUT(S)

A.3.1
A.3.11
controlled output signal

amplitude (RMS value)
A.3.2
output resistance
A.3.3
DC output voltage
5 V audio supply
8 V audio supply
3.3
A.3.4
note 32
0.5
A.3.5
power supply rejection
note 11
20
dB
A.3.31
A.3.6
internal signal-to-noise ratio
note 11 + 28 + 33
50
dB
A.3.7
external signal-to-noise ratio
note 11 + 33
60
dB
A.3.8
control range
see also Fig.53
70
dB
A.3.9
suppression of output signal

when mute is active
70
dB
A.3.10
DC shift output during muting
10
50
mV
ANALOGUE AUTOMATIC VOLUME LEVELLING; NOTE 34

A.4.1
gain at maximum boost
+6
dB
A.4.2
gain at minimum boost
-14
dB
A.4.3
charge (attack) current
mA
A.4.4
discharge (decay) current
200
nA
A.4.5
control voltage at maximum

boost
A.4.6
control voltage at minimum boost
2003 Nov 11
195
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CVBS, Y/C and RGB/YUV/YPRPB INPUTS

CVBS-Y/C SWITCH
1.0
1.4
50
dB
chrominance input voltage (burst note 5 and 37

amplitude)
0.3
1.0
chrominance input impedance
50
2.0
S.1.1
CVBS or Y input voltage

S.1.2
CVBS or Y input current
S.1.3
suppression of non-selected
CVBS input signal
S.1.4
S.1.5
note 35
notes 11 and 36
CVBS OUTPUT ON CVBSO

S.1.9

S.1.10
top sync level
0.5
S.1.11
output impedance
50
EXTERNAL RGB / YUV / YPBPR INPUT

S.2.1
RGB input signal amplitude for

an output signal of 1.2 V
(black-to-white) (peak-to-peak
value)
note 38
0.7
0.8
S.2.2
RGB input signal amplitude

before clipping occurs
note 11
1.0
S.2.3
Y input signal amplitude

1.4/1.0
2.0
S.2.4
U/PB input signal amplitude

1.33/
+0.7
2.0
S.2.5
V/PR input signal amplitude

input signal amplitude for an

output signal of 1.2 V
(black-to-white); when
activated via the YUV2-YUV0

bits; note 39
1.05/
+0.7
1.5
S.2.6
difference between black level of

internal and external signals at
the outputs
20
mV
S.2.7
input currents
no clamping; note 5
0.1
S.2.8
delay difference for the three

channels
note 11
20
ns
63 steps; see Fig.56
30
deg
BASE-BAND TINT CONTROL

S2.9
2003 Nov 11
tint control range
196
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
FAST INSERTION
S.3.1
input voltage
S.3.2
no insertion
0.4
insertion
0.9
S.3.3
maximum input pulse
insertion
5.0
S.3.4
delay time from RGB in to

RGB out
insertion; note 11
20
ns
S.3.5
delay difference between

insertion; note 11
insertion to RGB out and RGB in
to RGB out
20
ns
S.3.6
input impedance
500
S.3.7
suppression of internal RGB

signals
notes 11 and 36; insertion;

fi = 0 to 5 MHz
55
dB
S.3.8
suppression of external RGB

signals
notes 11 and 36; no

insertion; fi = 0 to 5 MHz
55
dB
YUV INTERFACE (COLOUR DIFFERENCE OUTPUT AND INPUT SIGNALS); NOTE 40

S.4.1
signal amplitude (RY)

INTF = 1, note 5
0.94
1.05
1.16
S.4.2
signal amplitude (BY)

INTF = 1, note 5
1.19
1.33
1.47
S.4.3
signal amplitude (PR)

INTF = 0, note 5
0.63
0.7
0.77
S.4.4
signal amplitude (PB)

INTF = 0, note 5
0.63
0.7
0.77
S.4.5
output impedance
500
YUV INTERFACE (LUMINANCE OUTPUT AND INPUT SIGNAL); NOTE 40

S.5.1

top sync-white, INTF=0
tbf
1.0
tbf
S.5.2

top sync-white, INTF=1
tbf
1.4
tbf
S.5.3
top sync level
INTF=0
1.5
S.5.4
top sync level
INTF=1
1.4
S.5.5
output impedance
INTF=0
250
S.5.6
output impedance
INTF=1
250
2003 Nov 11
197
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PAL / NTSC Comb Filter

LUMINANCE SIGNAL
F.1.1
luminance gain error
F.1.2
-3 dB luminance bandwidth
+1
dB
COMB mode, fSC = 4.43 MHz 6
MHz
F.1.3
COMB mode, fSC = 3.58 MHz 5
MHz
F.1.4
YC mode, fSC = 4.43 MHz
MHz
YC mode, fSC = 3.58 MHz
MHz
f = 4 x fSC
30
dB
F.1.7
f = 2 x fSC
30
dB
F.1.8
f = 1.33 x fSC
30
dB
F.1.9
f = fSC
40
dB
26
dB
suppression (comb depth) with fSC = 4.43 MHz; see Fig.70

respect to luminance band pass f = fSC
30
nearest to fSC
f = ((283.75-74)/283.75)x fSC
dB
10
dB
10
dB
dB
F.1.5
F.1.6
F.1.10
F.1.11
F.1.12
residues of clock frequencies in

the luminance signal (Vrms/1V)
COMB mode
cross talk suppression at vertical see note 41, vertical

transient black multi-burst
transition active video
(1V/V (p-p))
vertical blanking, see the
figures 68 and 69.
f = ((283.75+74)/283.75)x fSC
F.1.13
PAL-M; see Fig.70

F.1.14
f = fSC
30
F.1.15
f = ((227.25-59)/227.25)x fSC
10
dB
F.1.16
f = ((227.25+59)/227.25)x fSC
10
dB
PAL N; see Fig.70

F.1.17
f = fSC
dB
F.1.18
f = ((229.25-59)/229.25)x fSC
10
dB
F.1.19
f = ((229.25+59)/229.25)x fSC
10
dB
30
NTSC M, see Fig.70

F.1.20
f = fSC
30
dB
F.1.21
f = ((227.5-59)/227.5) x fSC
10
dB
F.1.22
f = ((227.5+59)/227.5) x fSC
10
dB
30
dB
NTSC 4.4 MHz, see Fig.70

F.1.23
f = fSC
F.1.24
f = ((281.75-74)/281.75) x fSC
10
dB
F.1.25
f = ((281.75+74)/281.75) x fSC
10
dB
+150
ns
Y DELAY ADJUSTMENT (VALID FOR PAL, NTSC AND SECAM)

F.1.26
2003 Nov 11
tuning range delay time
8 steps; note 42
198
CONFIDENTIAL
150

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CHROMINANCE SIGNAL
F.2.1
chrominance gain error
+1
dB
F.2.2
-3 dB chrominance bandwidth
COMB mode, around fSC,
1.5
MHz
F.2.3
chrominance signal-to-noise
ratio (0.7V/Vrms noise)
unweighted; fSC0.3fSC
56
dB
residues of clock frequencies in

the chrominance signal
(Vrms/0.7V)
COMB mode
f = 4 x fSC
30
dB
f = 2 x fSC
30
dB
F.2.6
f = 1.33 x fSC
40
dB
F.2.7
f = fSC
50
dB
26
dB
f = (284/283.75) x fSC
30
dB
f = ((284-74)/283.75) x fSC
30
dB
f = ((284+74)/283.75) x fSC
30
dB
F.2.4
F.2.5
F.2.8
F.2.9
F.2.10
F.2.11
cross talk suppression at vertical see note 43, vertical

transient no-colour colour
transition active video
(0.7V/V (p-p))
vertical blanking, see the
figures 68 and 69
suppression (comb depth) with
respect to chrominance band
pass at f = fSC
fSC = 4,43 MHz; see Fig.71
PAL M, see Fig.71

F.2.12
f = (227/227.25) x fSC
30
dB
F.2.13
f = ((227-59)/227.25) x fSC
30
dB
F.2.14
f = ((227+59)/227.25) x fSC
30
dB
PAL N, see Fig.71

F.2.15
f = (229/229.25) x fSC
30
dB
F.2.16
f = ((229-59)/229.25) x fSC
30
dB
F.2.17
f = ((229+59)/229.25) x fSC
30
dB
NTSC M, see Fig.71

F.2.18
f = (227/227.5) x fSC
30
dB
F.2.19
f = ((227-59)/227.5) x fSC
30
dB
F.2.20
f = ((227+59)/227.5) x fSC
30
dB
NTSC 4.4 MHz, see Fig.71

F.2.21
f = (282/281.75) x fSC
30
dB
F.2.22
f = ((282-74)/281.75) x fSC
30
dB
F.2.23
f = ((282+74)/281.75) x fSC
30
dB
2003 Nov 11
199
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Chrominance and Luminance filters

CHROMINANCE TRAP CIRCUIT; NOTE 44
fsc
MHz
3 dB
2.7
MHz
3 dB
3.3
MHz
colour subcarrier rejection
24
26
dB
trap frequency during SECAM

reception
4.3
MHz
MHz
MHz
F.3.1
trap frequency
F.3.2
Bandwidth at fSC = 3.58 MHz
F.3.3
Bandwidth at fSC = 4.43 MHz
F.3.4
F.3.5
CHROMINANCE BANDPASS CIRCUIT

F.4.1
centre frequency (CB = 0)
fsc
F.4.2
centre frequency (CB = 1)
1.1fsc
F.4.3
bandpass quality factor
4.26
4.29
4.31
MHz
241
268
295
kHz
CLOCHE FILTER
F.5.1
centre frequency
F.5.2
Bandwidth
CLO = 0
Picture Improvement Features

PEAKING CONTROL; NOTE 45
P.1.1
width of preshoot or overshoot
P.1.2
peaking signal compression

threshold
P.1.3
overshoot at maximum peaking
P.1.4
setting PF1/PF0 = 0/0
190
ns
160
ns
143
ns
125
ns
50
IRE
positive, direction white
45
negative
75
1.7
P.1.5
Ratio negative/positive
overshoot; note 46
P.1.6
peaking control curve
63 steps
see Fig.54
P.1.7
peaking centre frequency
2.7
MHz
P.1.8
3.1
MHz
P.1.9
3.5
MHz
P.1.10
4.0
MHz
10
IRE
CORING STAGE; NOTE 47

P.1.10
2003 Nov 11
coring range
200
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
BLACK LEVEL STRETCHER; NOTE 48

P.2.1
Maximum black level shift
BSD = 0
25
30
35
IRE
P.2.11
Maximum black level shift
BSD = 1
10
15
20
IRE
P.2.2
level shift at 100% peak white
IRE
P.2.3
IRE
P.2.4
BSD = 0
10
12
14
IRE
P.2.5
BSD = 1
IRE
DYNAMIC SKIN TONE (FLESH) CONTROL; NOTE 49

P.4.1
control angle
123
deg
P.4.32
correction range (angle)
45
deg
40
50
60
GAMMA CONTROL; NOTE 50

P.6.1
break point of characteristic
maximum white is 100%
P.6.2
maximum expansion
set by the bits WS1/WS0
12
P.6.3
mismatch for YIN = 100 IRE
at maximum expansion
+8
IRE
P.6.4
mismatch for YIN = 0 IRE
at maximum expansion
+4
IRE
BLUE STRETCH; NOTE 51

P.7.1
increase of small signal gain for

the blue channel
BLS = 1
20
P.7.2
decrease of small signal gain for BLS = 1

the red channel
20
10
IRE
1.5
DC TRANSFER RATIO OF LUMINANCE SIGNAL; NOTE 52

P.8.1
reduction of black level for white TFR = 1

picture (100 IRE)
SCAN VELOCITY MODULATION OUTPUT; NOTES 53 AND 54

P.9.1

(peak-to-peak value
VMA1/VMA0 = 1/1
P.9.11

(peak-to-peak value
VMA1/VMA0 = 1/1
1.8
P.9.2
delay of RGB output signal with

respect to SVM output
SVM2-SVM0 = 000, PF1-PF0

= 01 (peaking frequency of
3.1 MHz) and 50% input
signal amplitude
170
ns
P.9.3
coring range
CRA0 = 0
P.9.4
maximum DC-current through

the SVM output
VMA1/VMA0 = 0/0
100
2003 Nov 11
SMD1/SMD0 = 0/1
SMD1/SMD0 = 1/0
201
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Horizontal and vertical synchronization and drive circuits

SYNC VIDEO INPUT
H.1.1
sync pulse amplitude
note 5
50
300
350
mV
H.1.2
slicing level for horizontal sync
note 55
45
H.1.3
slicing level for vertical sync
note 55
35
HORIZONTAL OSCILLATOR
H.2.1
free running frequency
15625
Hz
H.2.2
spread free running frequency
H.2.3
frequency variation with respect VP = 8.0 V 10%; note 11

to the supply voltage
0.2
0.5
H.2.4
frequency variation with

temperature
Tamb = 0 to 70 C; note 11
80
Hz
0.8
1.1
kHz
0.5
0.8
kHz
FIRST CONTROL LOOP; NOTE 56

H.3.1
holding range PLL
H.3.2
catching range PLL
H.3.3
S/N ratio video input signal to

switch the time constant
24
dB
H.3.4
hysteresis at the switching point
dB
note 11
SECOND CONTROL LOOP

H.4.1
control sensitivity
150
s/s
H.4.2
control range from start of

horizontal output to flyback at
nominal shift position
19
H.4.3
horizontal shift range
H.4.4
control sensitivity for dynamic

compensation
13
s/V
H.4.5
Voltage to switch-on the flash

protection
4.0
H.4.6
Input current during protection
mA
H.4.7
control range parallelogram

correction
note 58
0.75
H.4.8
control range bow correction
note 58
1.0
63 steps
note 57
HORIZONTAL OUTPUT; NOTE 59

H.5.1
LOW level output voltage
0.3
H.5.2
maximum allowed output current
10
mA
H.5.3
maximum allowed output voltage
VP
H.5.4
duty factor
VOUT = LOW (TON); SDC = 0
55
H.5.41
duty factor
VOUT = LOW (TON); SDC = 1
60
H.5.5
switch-on time horizontal drive

pulse
1175
ms
H.5.6
switch-off time horizontal drive

pulse
43
ms
2003 Nov 11
IO = 10 mA
202
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
FLYBACK PULSE INPUT AND SANDCASTLE OUTPUT

H.6.1
required input current during

flyback pulse
note 5
100
300
H.6.2
output voltage
during burst key
4.5
5.0
5.5
during blanking
2.8
3.0
3.2
1.7
2.0
2.3
burst key pulse
3.3
3.5
3.7
vertical blanking, note 60
14/9.5
lines
4.8
5.0
5.2
tbf
Hz
H.6.3
clamped input voltage during

flyback
H.6.4
pulse width
H.6.5
H.6.6
delay of start of burst key to start

of sync
H.6.7
output voltage of H/V timing

signal
CSY = 1
VERTICAL OSCILLATOR; NOTE 61

H.7.1
free running frequency
50/60
H.7.2
locking range
45
64.5/72 Hz
H.7.3
divider value not locked
625/525
lines
H.7.4
locking range
434/488
722
lines/
frame
1.8
mA
VERTICAL RAMP GENERATOR

H.8.1
sawtooth amplitude
VS = 1FH;
C = 150 nF; R = 39 k
H.8.2
discharge current
H.8.3
charge current set by external

resistor
note 62
14
H.8.4
vertical slope
63 steps; see Fig. 88
20
+20
H.8.5
charge current increase
f = 60 Hz
19
H.8.6
LOW level of ramp
1.5
1.0
mA
VERTICAL DRIVE OUTPUTS

H.9.1
differential output current

VA = 1FH
H.9.2
common mode current
400
H.9.3
output voltage range
2.5
EHT TRACKING/OVERVOLTAGE PROTECTION

H.10.1
input voltage
1.2
2.8
H.10.2
scan modulation range
+5
H.10.3
vertical sensitivity
6.3
%/V
6.3
%/V
+120
120
3.9
H.10.4
EW sensitivity
H.10.5
EW equivalent output current
H.10.6
overvoltage detection level
2003 Nov 11
when switched-on
note 57
203
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DE-INTERLACE
H.11.1
first field delay
0.5H
EW WIDTH; NOTE 63
H.12.1
control range
100
65
H.12.2
equivalent output current
700
H.12.3
EW output voltage range
1.0
5.0
H.12.4
EW output current range
1200
EW PARABOLA/WIDTH
H.13.1
control range
23
H.13.2
EW=3FH; CP=11H; TC=1FH 0
460
EW UPPER/LOWER CORNER/PARABOLA
55
H.14.1
control range
H.14.2
PW=3FH; EW=3FH; TC=1FH 262
+55
+262
EW TRAPEZIUM
H.15.1
control range
+5
H.15.2
EW=1FH; CP=11H; PW=1FH 100
+100
VERTICAL AMPLITUDE
H.16.1
control range
80
120
H.16.2
equivalent differential vertical

drive output current
SC = 0EH
800
1200
+5
50
+50
10
25
85
117
VERTICAL SHIFT
H.17.1
control range
H.17.2
equivalent differential vertical

drive output current
S-CORRECTION
H.18.1
control range
VERTICAL LINEARITY
H.18.2
control range, ratio bottom/top of 63 steps; see Fig. 95;

screen (full screen linearity
VSH=1FH; SC=0;
setting)
VL1/VL0=0/0
VERTICAL ZOOM MODE (OUTPUT CURRENT VARIATION WITH RESPECT TO NOMINAL SCAN); NOTE 64
H.19.1
vertical expand factor
0.75
1.38
H.19.2
output current limiting and RGB

blanking
1.05
18
19
VERTICAL SCROLL
H.20.1
2003 Nov 11
Control range (percentage of

nominal visible picture
amplitude)
vertical zoom setting at 3FH
204
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Colour demodulation part

CHROMINANCE AMPLIFIER
D.1.1
ACC control range
D.1.2
change in amplitude of the

output signals over the ACC
range
D.1.3
threshold colour killer ON
D.1.4
hysteresis colour killer OFF
26
dB
dB
CHSE1/CHSE0 = 0/0
30
dB
strong signal conditions;

S/N 40 dB; note 11
+3
dB
noisy input signals; note 11
+1
dB
3.0
note 65
D.1.5
ACL CIRCUIT; NOTE 66
D.2.1
chrominance burst ratio at which

the ACL starts to operate
REFERENCE PART
Phase-locked loop
D.3.1
catching range
all standards
500
Hz
D.3.2
phase shift for a 400 Hz

deviation of the oscillator
frequency
note 11
deg
D.5.1
hue control range
35
40
deg
D.5.2
hue variation for 10% VP
note 11
deg
D.5.3
hue variation with temperature
Tamb = 0 to 70 C; note 11
deg
HUE CONTROL
DEMODULATORS
General
D.6.3
spread of signal amplitude ratio

between standards
note 11
+1
dB
D.6.5
bandwidth of demodulators
3 dB; note 67
650
kHz
PAL/NTSC demodulator
D.6.6
gain between both demodulators INTF = 0

G(BY) and G(RY)
1.26
1.41
1.58
D.6.12
change of output signal

amplitude with temperature
note 11
0.1
%/K
D.6.13
change of output signal

amplitude with supply voltage
note 11
0.1
dB
D.6.14
phase error in the demodulated

signals
note 11
deg
2003 Nov 11
205
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SECAM demodulator
D.7.1
black level off-set
kHz
D.7.2
pole frequency of deemphasis
77
85
93
kHz
D.7.3
ratio pole and zero frequency
D.7.4
non linearity
D.7.5
calibration voltage
1.8
2.3
2.8
SBO1/SBO0 = 1/0
Base-band delay line

D.8.1
variation of output signal for

adjacent time samples at
constant input signals
0.1
0.1
dB
D.8.2
residual clock signal

mV
D.8.3
delay of delayed signal
63.94
64.0
64.06
D.8.4
delay of non-delayed signal
40
60
80
ns
D.8.5
difference in output amplitude

with delay on or off
COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT)
PAL/SECAM mode; (RY) and (BY) not affected

D.9.1
ratio of demodulated signals

(GY)/(RY)
0.51
10%
D.9.2
ratio of demodulated signals

(GY)/(BY)
0.19
25%
NTSC mode; the matrix results in the following signals (nominal hue setting)
MUS-bit = 0
D.9.6
(BY) signal: 2.03/0
2.03UR
D.9.7
(RY) signal: 1.59/95
0.14UR + 1.58VR
D.9.8
(GY) signal: 0.61/240
0.31UR 0.53VR
MUS-bit = 1
D.9.9
(BY) signal: 2.03/0
2.03UR
D.9.10
(RY) signal: 1.59/102
0.24UR + 1.55VR
D.9.11
(GY) signal: 0.61/236
0.31UR 0.51VR
REFERENCE SIGNAL OUTPUT/SWITCH OUTPUT; NOTE 68

D.10.1
reference frequency
CMB1/CMB0 = 01
D.10.2

CMB1/CMB0 = 01
D.10.3
output level (mid position)
CMB1/CMB0 = 01
1.9
2.1
2.3
D.10.4
SWO output level LOW
CMB1/CMB0 = 10
0.8
D.10.5
SWO output level HIGH
CMB1/CMB0 = 11
4.5
2003 Nov 11
206
CONFIDENTIAL
3.58/4.43
0.2
0.25
MHz
0.3

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Control part
SATURATION CONTROL; NOTE 38
C.1.1
saturation control range
52
dB
20
dB
CONTRAST CONTROL; NOTE 38

C.2.1
contrast control range
C.2.2
tracking between the three

channels over a control range of
10 dB
0.5
dB
C.2.6
contrast reduction
10
dB
0.4
1.2
0.5
2.5
3.0
BRIGHTNESS CONTROL
C.3.1
brightness control range
RGB AMPLIFIERS
C.4.1

C.4.101
output signal control range due

to the CCC gain loop
C.4.2
maximum signal amplitude

(black-to-white)
C.4.3
maximum peak white level
C.4.4
output signal amplitude for the

red channel (peak-to-peak
value)
at nominal luminance input
signal, nominal settings for

contrast, white-point
adjustment and cathode drive
level(CL3-CL0 = 7H)
note 69
at nominal settings for
contrast and saturation

control and no luminance
signal to the input (RY, PAL)
4.0
1.26
C.4.41
output impedance
300
C.4.5
nominal black level voltage
1.65
C.4.6
black level voltage
when black level stabilisation

is switched-off (via AKB bit)
1.65
C.4.61
black level voltage control range AVG bit active; note 70
1.0
1.65
2.3
C.4.71
timing of wide blanking with

respect to mid sync (HBL = 1);
note 71
start of blanking; WBI = 0
3.5
5.9
end of blanking; WBI = 0
7.8
10.2
start of blanking; WBI = 1
9.7
12.1
C.4.72
C.4.73
14.0
16.4
C.4.8
control range of the black-current

stabilisation
0.65
C.4.81
RGB output level when RGBL=1
0.8
C.4.74
2003 Nov 11
end of blanking; WBI = 1
207
CONFIDENTIAL

NUMBER
C.4.9
PARAMETER
UOCIII series
CONDITIONS
blanking level
difference with black level,

note 69
MIN.
TYP.
0.3
MAX.
UNIT
V
C.4.91
blanking level when RBL = 1
1.1
C.4.10
level during leakage test
0.07
C.4.11
level low measuring pulse
0.15
C.4.12
level high measuring pulse

(current setting 220 A); note 72
0.6
C.4.13
adjustment range of the cathode note 69

drive level
dB
C.4.14
variation of black level with

temperature
1.0
mV/K
C.4.141
black level off-set adjustment on 63 steps

the Red and Green channel
100
mV
C.4.21
signal-to-noise ratio of the output RGB input; note 73

signals
CVBS input; note 73
60
dB
50
dB
residual voltage at the RGB

outputs (peak-to-peak value)
at fosc
15
mV
C.4.24
at 2fosc plus higher harmonics
15
mV
C.4.25
bandwidth of output signals
RGB input; at 3 dB
MHz
C.4.26
CVBS input; at 3 dB;

fosc = 3.58 MHz
2.8
MHz
C.4.27
CVBS input; at 3 dB;

fosc = 4.43 MHz
3.4
MHz
C.4.28
S-VHS input; at 3 dB
MHz
HEX code
20H
dB
10
220
C.4.22
C.4.23
note 11
WHITE-POINT ADJUSTMENT
C.5.1
I2C-bus setting for nominal gain
C.5.2
adjustment range of the relative

R, G and B drive levels
2-POINT BLACK-CURRENT STABILIZATION, NOTES 74

C.6.1
amplitude of low reference

current
C.6.2
amplitude of high reference

current; note 72
C.6.3
acceptable leakage current
75
C.6.4
input impedance during scan
500
SLG0/SLG1 = 0/0
BEAM CURRENT LIMITING

C.7.1
contrast reduction starting

voltage
2.8
C.7.2
voltage difference for full contrast

reduction
1.8
C.7.3
brightness reduction starting

voltage
1.7
2003 Nov 11
CBS = 0
208
CONFIDENTIAL

NUMBER
PARAMETER
UOCIII series
CONDITIONS
MIN.
TYP.
MAX.
UNIT
2.4
voltage difference for full

brightness reduction
0.9
C.7.5
internal bias voltage
3.3
C.7.8
maximum allowable current
mA
C.7.31
brightness reduction starting

voltage
C.7.4
CBS = 1
FIXED BEAM CURRENT SWITCH-OFF; NOTE 75

C.8.1
discharge current during

switch-off
0.85
1.0
1.15
mA
C.8.2
discharge time of picture tube
38
ms
PEAK WHITE LIMITER AND SOFT CLIPPING; NOTES 76 AND 77

C.9.1
CVBS signal amplitude at which PWL range (15 steps); at

peak white limiter is activated
max. contrast
(black-to-white value)
0.40
0.60
C.9.2
soft clipper gain reduction
dB
maximum contrast; note 77,

see Fig.84
General purpose switch output SWO1 (controlled by SWO1 bit)

O.1.1
output voltage HIGH
3.5
5.0
5.5
O.1.2
output voltage LOW
0.2
0.4
O.1.3
sink current
mA
O.1.4
source current
mA
3.3
Vertical guard input and LED drive output; note 78

I/O.1.1
output voltage HIGH
vertical guard activated

vertical guard not activated
I/O.1.2
output voltage HIGH
5.5
I/O.1.3
output voltage LOW
0.2
0.4
I/O.1.4
sink current
mA
I/O.1.5
detection level for vertical guard

and input port
tbf
3.6
tbf
Notes
1. When the 3.3 V supply is present and the -Controller is active a low-power start-up mode can be activated. When
all subaddress bytes have been sent and the POR and XPR flags have been cleared the horizontal output can be
switched-on via the STB-bit (subaddress 3DH). In this condition the horizontal drive signal has the nominal TOFF and
the TON grows gradually from zero to the nominal value. As soon as the 5 V supply is present the switch-on procedure
(e.g. closing of the second loop) is continued.
2. The various parameters in this specification are guaranteed for a supply voltage range between 4.75 V and 5.5 V.
For supply voltages between 4.5 V and 4.75 v some output signals may be distorted or clipped, however, the
operation of the circuit is not affected at these supply voltages.
3. The supply voltage of the analogue audio part may have a value between 5V and 8V. For a supply voltage of 5V the
maximum amplitude of the output signals is 1Vrms. For a supply voltage of 8V the maximum amplitude of the output
signals is 2Vrms.
4. On set AGC.
5. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
2003 Nov 11
209
CONFIDENTIAL

UOCIII series
6. Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level as
FPLL input signal level).
7. The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a
digital control circuit which uses the clock frequency of the -Controller as a reference. The required IF frequency for
the various standards is set via the IFA-IFC bits in subaddress 2FH. When the system is locked the resulting IF
frequency is very accurate with a deviation from the nominal value of less than 25 kHz.
8. Measured at 10 mV (RMS) top sync input signal.
9. So called projected zero point, i.e. with switched demodulator.
10. Measured in accordance with the test line given in Fig.60. For the differential phase test the peak white setting is
reduced to 87%.
The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.
The phase difference is defined as the difference in degrees between the largest and smallest phase angle.
11. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
12. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.61.
13. The noise inverter is only active in the strong signal mode (no noise detected in the incoming signal)
14. The test set-up and input conditions are given in Fig.62. The figures are measured with an input signal of
10 mV RMS. This test can only be carried out in a test set-up in which the test options of the IC can be activated.
This because the IF-AGC control input is not available in this IC.
15. Measured at an input signal of 10 mVRMS. The S/N is the ratio of black-to-white amplitude to the black level noise
voltage (RMS value). B = 5 MHz. Weighted in accordance with CCIR 567.
16. Via this pin both the demodulated IF signal and the selected CVBS (or Y+C) signal can be supplied to the output.
The pin can also be used as CVBS input. The selection between both signals is realised by means of the SVO bits
in subaddress 39H.
17. The cascade of sound trap and group delay correction filter compensates for the group delay pre-distortion of the BG
standard, curve A (see Rec. ITU-R BT.470-4). The indicated values are the difference between the group delay at
4.43 MHz and the group delay at 10 kHz.
18. The time-constant of the IF-AGC is internal and the speed of the AGC can be set via the bits AGC1 and AGC0 in
subaddress 30H. The AGC response time is also dependent on the acquisition time of the PLL demodulator. The
values given are valid for the norm setting (AGC1-AGC0 = 0-1) and when the PLL is in lock.
19. The AFC control voltage is generated by the digital tuning system of the PLL demodulator. This system uses the
clock frequency of the TCG -Controller as a reference and is therefore very accurate. For this reason no maximum
and minimum values are given for the window sensitivity figures (parameters M.7.2 and M.7.3). The tuning
information is supplied to the tuning system via the AFC bits in output byte 04H. The AFC value is valid only when
the LOCK-bit is 1.
20. The QSS IF circuit can also be used for the preprocessing of digital TV signals. The modulated signal has to be
supplied to the sound IF input (via a suitable filter) and the mixed down I-signal is available at the DVB outputs.
The AGC has two modes of operation: the internal mode in which the IC sets the gain with its own reference and an
external mode in which the gain can be controlled with an external circuit. In the second case the QSS-IF AGC pin
is used as an input to control the IF gain with an external circuit.
21. The reference signal for the I-mixer (frequency 43.008 or 49.152 MHz) is internally generated. It is also possible to
supply an external reference signal to the mixer. This external mode is activated by means of the CMB2-CMB0 and
IFD bits. The signal has to be supplied to the pin which is normally used as the reference signal output of the colour
decoder (REFO).
2003 Nov 11
210
CONFIDENTIAL

UOCIII series
22. The weighted S/N ratio is measured under the following conditions:
a) The vision IF modulator must meet the following specifications:
Incidental phase modulation for black-to-white jumps less than 0.5 degrees.
QSS AF performance, measured with the television-demodulator AMF2 (audio output, weighted S/N ratio) better
than 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation.
Picture-to-sound carrier ratio: PC/SC1 = 13 dB (transmitter).
b) The measurements must be carried out with the Siemens SAW filters G3962 for vision IF and G9350 for sound
IF. Input level for sound IF 10 mVRMS with 27 kHz deviation.
c) The PC/SC ratio at the vision IF input is calculated as the addition of the TV transmitter ratio and the SAW filter
PC/SC ratio. This PC/SC ratio is necessary to achieve the S/N(W) values as indicated.
23. The input should be shunted with a resistor of 470 - 10 k
24. If a 10.7MHz FM radio IF signal is supplied to the external 2nd SIF input, an external 10.7MHz bandpass filter must
be used.
25. f = 4.5/5.5 MHz; FM: 70 Hz, 50 kHz deviation; AM: 1.0 kHz, 30% modulation.
26. f = 5.5 MHz; modulation frequency: 1 kHz, f = 27 kHz.
27. Depending on the application (FM or AM reception) the amplitude of the output signal can be increased with 6 dB by
the AGN bit in subaddress 33H (FM reception) or AMLOW bit in subaddress 35H (AM reception). The resulting output
signal amplitudes are given in Table 268.
28. The signal-to-noise ratio is measured under the following conditions:
a) Input signal to the SSIF pin (activated via the CMB2-CMB0 bits) with an amplitude of 100mVRMS, fMOD = 1 kHz
and f = 27 kHz
b) Output signal measured at the AUDEEM pin. The noise (RMS value) is measured according to the CCIR 468
definition.
29. In the Mono versions the deemphasis pin can also be used as additional audio input. In that case the internal
(demodulated FM signal) must be switched off. This can be realised by means of the SM (sound mute) bit. When the
vision IF amplifier is switched to positive modulation the signal from the FM demodulator is automatically switched
off. The external signal must be switched off when the internal signal is selected.
30. The Stereo and AV Stereo versions have 4 stereo inputs. The maximum output signal amplitude of the selector
(1.0 VRMS or 2.0 VRMS) is dependent on the supply voltage (5 V or 8 V) of the audio selector supply pin (VCC8V).
31. Audio attenuator at 6 dB, input signal 500 mVRMS
32. Audio input signal 200 mVRMS. Measured with a bandwidth of 15 kHz and the audio attenuator at 6 dB.
33. Unweighted RMS value, audio input signal 500 mVRMS, audio attenuator at 6 dB.
34. In versions without stereo decoder and digital sound processing circuits an analogue Automatic Volume Levelling
(AVL) function can be activated. The pin to which the external capacitor has to be connected can be chosen by
means of the AVLE bit (subaddress 34H). When the East-West output is not used (90 picture tubes) the capacitor
can be connected to the EW output pin. In 110 applications a choice has to be made between the AVL function and
a sub-carrier output / general purpose switch output. The selection must be made by means of the CMB0 to CMB2
bit in subaddress 4AH. More details about the sub-carrier output are given in the parameters D.10.
The Automatic Volume Levelling (AVL) circuit stabilises automatically the audio output signal to a certain level which
can be set by means of the volume control. This AVL function prevents big audio output fluctuations due to variation
of the modulation depth of the transmitter. The AVL can be switched on and off via the AVL bit in subaddress 34H.
The AVL is active over an input voltage range (measured at the deemphasis output) of 50 to 1500 mVRMS. The AVL
control curve is given in Fig.65. The control range of +6 dB to 14 dB is valid for input signals with 50% of the
maximum frequency deviation.
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35. Signal with negative-going sync. Amplitude includes sync pulse amplitude.
36. This parameter is measured at nominal settings of the various controls.
37. Indicated is a signal for a colour bar with 75% saturation (chroma : burst ratio = 2.2 : 1).
38. The contrast and saturation control is active on the internal signal (YUV) and on the external RGB/YUV/YPRPB input.
The Text/OSD input can be controlled on brightness only. Nominal contrast is specified with the DAC in position 20
HEX. Nominal saturation as maximum 10 dB.
39. The YUV/YPBPR input signal amplitudes are based on a colour bar signal with 75/100% saturation.
40. Depending on the setting of the INTF bit (subaddress 42H) the saturation of the output signal is 75% (YUV signal)
or 100% (YPRPB signal). The luminance and colour difference out- and inputs can directly be connected. When
additional picture improvement ICs (like the TDA 9178) are applied the inputs of these ICs must be ac coupled
because of the black level clamp requirement. The output signal of the picture improvement IC can directly be
coupled to the luminance and colour difference inputs as long as the dc level of these signals have a value between
1 and 4 V (for the luminance signal) or between 1 and 4 V (for the UV signals). When the dc level of the input signals
exceed these levels the signals must be ac coupled and biased to a voltage level within these limits.
41. Test signal:
For PAL B, G, H, D, I and N: CCIR-18 multi-burst (see Fig. 66).
For PAL M and NTSC M: 100% amplitude FCC multi-burst (see Fig. 67).
42. This control range is valid for a colour carrier frequency of 4.43 MHz. For a colour carrier frequency of 3.58 MHz the
control range has a value of 190 s (see also Table 132).
43. Test signal:
For PAL B, G, H, D, I and N: 100/0/75/0 EBU colour bar.
For PAL M and NTSC M: 100% white 75% amplitude FCC colour bar.
44. When the decoder is forced to a fixed subcarrier frequency (via the CM-bits) the chroma trap is always switched-on,
also when no colour signal is identified. In the automatic mode the chroma trap is switched-off when no colour signal
is identified.
45. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns
and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the
overshoots but by measuring the frequency response of the Y output.
46. The ratio between the positive and negative peaks can be varied by means of the bits RPO1 and RPO0 in
subaddress 47H. For ratios which are smaller than 1.7 the positive peak is not affected and the negative peak is
reduced.
47. The coring can be activated in the low-light part of the picture. This effectively reduces the noise while having
maximum peaking in the bright parts of the picture. The setting the video content at which the coring is active can be
adapted by means of the COR1/COR0 bits in subaddress 47H.
48. For video signals with a black level which deviates from the back-porch blanking level the signal is stretched to the
blanking level. The amount of correction depends on the IRE value of the signal (see Fig.72). The black level is
detected by means of an internal capacitor. The black level stretcher can be switched on and off via the BKS bit in
subaddress 45H. The values given in the specification are valid only when the luminance input signal has an
amplitude of 1 Vp-p.
49. The Dynamic Skin Tone Correction circuit is designed such that it corrects (instantaneously and locally) the hue of
those colours which are located in the area in the UV plane that matches to skin tones. The correction is dependent
on the luminance, saturation and distance to the preferred axis. Because the amount of correction is dependent on
the parameters of the incoming YUV signal it is not possible to give exact figures for the correction angle. The
correction angle of 45 (22.5) degrees is just given as an indication and is valid for an input signal with a luminance
signal amplitude of 75% and a colour saturation of 50%. A graphical representation of the control behaviour is given
in Figure 73 on page 229.
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50. The gamma control is realised by inserting a non-linear transfer characteristic in the luminance path. The shape of
the curve can be adapted by means of the WS1/WS0 bits in subaddress 45H. The control curves are given in Fig. 74.
It is possible to make the gamma control dependent on the Average Picture Level (APL). This function is identical to
the previous white stretch function. Then the GAM bit (subaddress 44H) must be set to 0. The control curve can
again be adapted by means of the WS1/WS0 bits (see also Fig. 75). When the gamma control is active the colour
saturation is adapted to the variation of the luminance linearity.
51. Via the blue stretch (BLS bit) function the colour temperature of the bright scenes (amplitudes which exceed a value
of 80% of the nominal amplitude) can be increased. This effect is obtained by increasing the small signal gain of the
blue channel and decreasing the small signal gain for the red channel for signals which exceed the 80% level. The
effect is illustrated in Figure 76 on page 230.
52. When this function is activated (TFR = 1) the black level of the RGB output signals is dependent on the average
picture information. For a black picture the black level is unaffected and the maximum black level shift for a complete
white picture (100 IRE) is 10 IRE in the direction black. The black level shift is linearly dependent on the picture
content.
53. The SVM is specified for a 2T-pulse input signal with an amplitude (100%) of 700 mVP-P. The coring system on the
SVM output signal has to levels. The SVM output signal amplitude is dependent on the setting of the coring and on
SVMA (see Fig. 77).
54. The delay between the RGB output signals and the SVM output signal can be adjusted (by means of the
SVM2-SVM0 bits in subaddress 48H) so that an optimum picture performance can be obtained. Furthermore a video
dependent coring function can be activated. Another feature is that the SVM output signal can be made dependent
on the horizontal position on the screen (parabola on the SVM output). The screen is equally divided into 6 parts (see
Fig. 78). By multiplying a gain factor with the SVM output signal as a function of the horizontal position several
discrete curves can be made. The shape of the curve can be programmed by means of the SPR2-SPR0 bits (in
subaddress 48H).
55. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing
level and the top sync level. When the amplitude of the sync pulse exceeds the value of 350 mV the sync separator
will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 0.4 Vp-p. By
means of the SSL bit (subaddress 3FH) the slicing level can be changed to 30% (SSL = 1).
The vertical slicing level is dependent on the S/N ratio of the incoming video signal. For a S/N 24 dB the slicing
level is 35%, for a S/N 24 dB the slicing level is 60%. With the bit FSL (Forced Slicing Level) the vertical slicing
level can be forced to 60%.
56. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition and the condition of the POC, FOA, FOB and VID bits in
subaddress 3DH. The circuit contains a noise detector and the time constant is switched to slow when too much
noise is present in the signal. In the fast mode during the vertical retrace time the phase detector current is increased
50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. Switching of the time
constant can be automatically or can be set by means of the control bits.
The circuit contains a video identification circuit which is independent of the first loop. This identification circuit can
be used to close or open the first control loop when a video signal is present or not present on the input. This enables
a stable On Screen Display (OSD) when just noise is present at the input.
To prevent that the horizontal synchronisation is disturbed by anti copy signals like Macrovision the phase detector
is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The width
of the gate pulse is about 22 s. During weak signal conditions (noise detector active) the gating is active during the
complete scan period and the width of the gate pulse is reduced to 5.7 s so that the effect of noise is reduced to a
minimum.
The output current of the phase detector in the various conditions are shown in Table 269.
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57. The ICs have 2 protection inputs. The protection on the second phase detector pin is intended to be used as flash
protection. When this protection is activated the horizontal drive is switched-off immediately and then switched-on
again via the slow start procedure.
The protection on the EHT input is intended for overvoltage (X-ray) protection. When this protection is activated the
horizontal drive is directly switched-off (via the slow stop procedure).
The EHT protection input can also be used to switch-off the TV receiver in a correct way when it is switched off via
the mains power switch or when the power supply is interrupted by pulling the mains plug. This can be realised by
means of a detection circuit which monitors the main supply voltage of the receiver. When this voltage suddenly
decreases the EHT protection input must be pulled HIGH and then the horizontal drive is switched off via the slow
stop procedure. Whether the EHT capacitor is discharged in the overscan or not during the switch-off period depends
on the setting of the OSO bit (subaddress 3EH, D4). See also note 75.
58. The control range indicates the maximum phase difference at the top and the bottom of the screen. Compared with
the phase position at the centre of the screen the maximum phase difference at the top and the bottom of the screen
is 0.75 s for the parallelogram and 1.0 s for the bow correction.
59. During switch-on the horizontal drive starts-up in a soft-start mode. The horizontal drive starts with a very short TON
time of the horizontal output transistor, the off time of the transistor is identical to the off time in normal operation.
The starting frequency during switch-on is therefore about 2 times higher than the normal value. The on time is
slowly increased to the nominal value in a time of about 1175 ms (see Fig.81). The rather slow rise of the TON
between 75% and 100% of TON is introduced to obtain a sufficiently slow rise of the EHT for picture tubes with
Dynamic Astigmatic Focus (DAF) guns. When the nominal frequency is reached the PLL is closed in such a way that
only very small phase corrections are necessary. This ensures a safe operation of the output stage.
During switch-off the soft-stop function is active. This is realised by doubling the frequency of the horizontal output
pulse. The switch-off time is about 43 ms (see Fig.81). When the switch off command is received the soft-stop
procedure is started after a delay of about 2 ms. During the switch-off time the EHT capacitor of the picture tube is
discharged with a fixed beam current which is forced by the black current loop (see also note 75). The discharge time
is about 38 ms.
The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched-on
during the flyback time.
60. The vertical blanking pulse in the RGB outputs has a width of 27 or 22 lines (50 or 60 Hz system). The vertical pulse
in the sandcastle pulse has a width of 14 or 9.5 lines (50 or 60 Hz system). This to prevent a phase distortion on top
of the picture due to a timing modulation of the incoming flyback pulse.
61. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit.
During TV reception this divider circuit has 3 modes of operation:
a) Search mode large window.
This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines
per frame outside the range between 311 and 314(50 Hz mode) or between 261 and 264 (60 Hz mode) is
received). In the search mode the divider can be triggered between line 244 and line 361 (approximately
45 to 64.5 Hz).
b) Standard mode narrow window.
This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window.
The IVWF bit in output byte 03 is set to 1 when 7 succeeding vertical sync pulses are detected in the narrow
window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical
ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small.
The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found
within the window.
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c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz).
When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are
in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched
to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical
sync pulse is missing.
When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this
window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.
The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the
divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit
in subaddress 3EH.
When RGB signals are inserted the maximum vertical frequency is increased to 72 Hz. This has the consequence
that the circuit can also be synchronised by signals with a higher vertical frequency like VGA.
62. Conditions: frequency is 50 Hz; normal mode; VS = 1F.
63. The output range percentages mentioned for E-W control parameters are based on the assumption that 400 A
variation in E-W output current is equivalent to 20% variation in picture width.
64. The ICs have a zoom adjustment possibility for the horizontal and vertical deflection. For this reason an extra DAC
has been added in the vertical amplitude control which controls the vertical scan amplitude between 0.75 and 1.38
of the nominal scan. At an amplitude of 1.06 of the nominal scan the output current is limited and the blanking of the
RGB outputs is activated. This is illustrated in Fig. 79.
When the vertical amplitude is compressed (zoom factor <1) it is still possible to display the black-current measuring
lines in the vertical overscan. The feature is activated by means of the OSVE-bit in subaddress 40H. Because the
vertical deflection output stage needs some time for the excursion from the top of the picture to the required position
on the screen the vertical blanking is increased when the OSVE-bit is activated. The shape of the vertical deflection
current for a zoom factor of 0.75 with OSVE activated is given in Fig. 80. The exact timing of the measuring pulses
and vertical blanking for the various conditions is given in Fig. 82.
The nominal scan height must be adjusted at a position of 19 HEX of the vertical zoom DAC.
65. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude
300 mV (p-p)) the dynamic range of the ACC is +6 and 20 dB.
66. The ACL function can be activated by via the ACL bit in the subaddress 3BH. The ACL circuit reduces the gain of
the chroma amplifier for input signals with a chroma-to-burst ratio which exceeds a value of 3.0.
67. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass
filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz.
68. The subcarrier output is combined with a 3-level switch output which can be used to switch external circuits like
sound traps etc. This output is controlled by the CMB1 and CMB0 bits in control byte 22H. The subcarrier signal is
available when CMB1/0 are set to 0/1. During the demodulation of SECAM signals the subcarrier signal is only
available during the vertical retrace period. The frequency is 4.43 MHz in this condition.
69. Because of the 2-point black current stabilization circuit both the black level and the amplitude of the RGB output
signals depend on the drive characteristic of the picture tube. The system checks whether the returning measuring
currents meet the requirement and adapts the output level and gain of the circuit when necessary. Therefore the
typical value of the black level and amplitude at the output are just given as an indication for the design of the RGB
output stage.
The 2-point black level system adapts the drive voltage for each cathode in such a way that the 2 measuring currents
have the right value. This has the consequence that a change in the gain of the output stage will be compensated
by a gain change of the RGB control circuit. Because different picture tubes may require different drive voltage
amplitudes the ratio between the output signal amplitude and the inserted measuring pulses can be adapted via the
I2C-bus. This is indicated in the parameter C.4.13.
Because of the dependence of the output signal amplitude on the application the soft clipping limiting has been
related to the input signal amplitude.
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70. The alignment system for the Vg2 voltage of the picture tube can be activated by means of the AVG bit. In that
condition a certain black level is inserted at the RGB outputs during a few lines. The value of this level can be
adjusted by means of the brightness control DAC. An automatic adjustment of the Vg2 of the picture tube can be
realised by using the WBC and HBC bits in output byte 01. These bits indicate whether the black level feedback
current is inside or outside the window between 12 and 20 A. The indication of these bits can be made visible on
the screen via OSD so that this alignment procedure can also be used for service purposes. Because the gain loop
is digital quantization steps may occur in the read-out of the WBC and HBC bits.
71. When the reproduction of 4 : 3 pictures on a 16 : 9 picture tube is realised by means of a reduction of the horizontal
scan amplitude the edges of the picture may slightly be disturbed. This effect can be prevented by adding an
additional blanking to the RGB signals. The blanking pulse is derived form the horizontal oscillator and is directly
related to the incoming video signal (independent of the flyback pulse). This blanking is activated with the HBL bit.
The width of the blanking can be set by means of the bits WBF3-WBF0 (start of blanking) and WBR3-WBR0 (end of
blanking) in subaddress 26H (see Fig.85).
When the Double Window feature is activated it may be necessary to increase the width of the wide blanking. This
can be realised by means of the WBI bit (subaddress 3EH).
72. This parameter is valid only when the CCC loop is active.
73. Signal-to-noise ratio (S/N) is specified as peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz).
74. This is a current input. The timing of the measuring pulses and the vertical blanking for the 50/60 Hz standard are
given in Fig.82
The start-up procedure is as follows.
When the TV receiver is switched-on the RGB outputs are blanked and the black-current loop will try to adjust the
picture tube to the right bias levels. The RGB drive signals are switched-on as soon as the black current loop is
stabilised. This results in the shortest switch-on time.
When this switch-on system results in a visible disturbance of the picture it is possible to add a further switch-on delay
via a software routine. In that case the RGB outputs must be blanked by means of the RBL bit. The condition of the
gain loop and the total black current loop can be read from the GLOK and BCF bits. This information can be used to
switch-on the RGB outputs after some additional delay.
75. During switch-off the magnitude of the discharge current of the picture tube is controlled by the black current loop.
Dependent on the setting of the OSO bit the vertical scan can be stopped in an overscan position during that time so
that the discharge is not visible on the screen. The switch-off procedure is as follows:
a) When the switch-off command is received the RGB outputs are blanked for a time of about 2 ms.
b) If OSO = 1 the vertical scan is placed in an overscan position
c) If OSO = 0 the vertical deflection will keep running during the switch-off time
d) The soft-stop procedure is started by doubling the frequency of the horizontal output pulse
e) The fixed beam current is forced via the black current loop
f) The soft-stop time has a value of 43 ms, the fixed beam current is flowing during a time of 38 ms.
76. The control circuit contains a Peak White Limiting (PWL) circuit and a soft clipper.
a) The detection level of the PWL is adjustable via the I2C-bus and has a control range between 0.4 and 0.6 VBL-WH
(this amplitude is related to the CVBS/Y input signal (typical amplitude 0.7 VBL-WH) at maximum contrast setting).
The high frequency components of the video signal are suppressed so that they do not activate the limiting action.
The contrast reduction of the PWL is obtained by discharging the capacitor of the beam current limiting input.
b) In addition to the PWL circuit the IC contains a soft clipper function which limits the high frequency signals when
they exceed the peak white limiting level. The difference between the peak white limiting level and the soft clipping
level is adjustable via the I2C-bus and can be varied between 0 and 10% in 3 steps (soft clipping level equal or
higher than the PWL level). It is also possible to switch-off the soft clipping function.
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77. The soft clipper gain reduction is measured by applying a sawtooth signal with rising slope and 0.7 VBL-WH at the
CVBS input. To prevent the beam current limiter from operating a DC voltage of 3.5V must be applied to BCLIN pin.
The contrast is set at the maximum value, the PWL (peak white limiting) level at the minimum value, and the soft
clipping level is set at 0% above the PWL level (SOC10=00). The tangents of the sawtooth waveform at one of the
RGB outputs is now determined at begin and end of the sawtooth. The soft clipper gain reduction is defined as the
ratio of the slopes of the tangents for black and white, see Fig.84.
78. The VGUARD/SWIO pin can be used for various purposes. The various combinations are given below.
a) Just vertical guard input.
b) Combination of vertical guard and LED drive output. In this condition the output is high-ohmic during the vertical
retrace (1 ms) so that the vertical guard pulse can be detected.
c) Single ended output switch
d) Input port
The functionality of this pin is controlled by the VGM1/0 and LED bits.
Table 268 Output signal amplitude of deemphasis pin as function of AGN and AMLOW bits; note 1
OUTPUT LEVEL DURING FM
RECEPTION
OUTPUT LEVEL DURING AM

RECEPTION
AGN
AMLOW
125 mVRMS
250 mVRMS
125 mVRMS
125 mVRMS
250 mVRMS
250 mVRMS
250 mVRMS
125 mVRMS
Note
1. The indicated values are valid for a modulation index of 54% for both the FM and AM signal
Table 269 Output current of the phase detector in the various conditions
I2C-BUS COMMANDS
VID
POC
0
FOA
0
-1 CURRENT/MODE
IC CONDITIONS
FOB
0
IFI
yes
SL
yes
NOISE
no
SCAN
200
V-RETR
GATING
MODE
300
yes
(1)
normal
normal
yes
yes
yes
30
30
yes(2)
yes
no
200
300
no
normal
yes
30
30
yes(2)
slow
yes
yes
no
200
300
no
slow
yes
yes
no
OSD
200
300
yes(1)
fast
no
no
OSD
off
Note
1. Gating is active during vertical retrace, the width is 22 s. This gating prevents disturbance due to Macro Vision Anti
Copy signals.
2. Gating is continuously active and is 5.7 s wide
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gm
handbook, halfpage
Ci
1
f osc = ----------------------------------------C i C tot
2 L i ---------------------C i + C tot
Co
276 k
100
XTALIN
XTALI
XTALOUT
XTALO
Li
Cp
Ci
Ri
Cx1
Ca
Ca Cb
C tot = C p + ------------------Ca + Cb
crystal
or
ceramic
resonator
Ca = Ci + Cx1
Cb = Co + Cx2
Cx2
Cb
MGR447
Fig.52 Simplified diagram crystal oscillator.
%
dB
80
-20
60
-40
40
-60
20
-80
0
0
10
20
30
40
DAC (HEX)
20
0
20
40
60
80
DAC (HEX)
Overshoot in direction black.
Fig. 54 Peaking control curve.
Fig. 53 Volume control curve
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+50
+50
(deg)
(deg)
+30
+30
+10
+10
10
10
30
30
50
50
0
10
20
30
40
DAC(HEX)
10
Fig.55 Hue control curve.
20
30
40
DAC(HEX)
Fig.56 Base-band tint control curve.
MLA740 - 1
MLA741 - 1
300
250
(%)
% 225
250
200
100
(%)
90
175
80
150
70
125
150
60
100
50
200
100
75
40
50
30
25
20
50
00
10
20
10
30
40
DAC (HEX)
Fig. 57 Saturation control curve.
2003 Nov 11
10
20
30
40
DAC (HEX)
Fig. 58 Contrast control curve.
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UOCIII series
(V)
MLA742 - 1
+0.4
0.7
(V)
MBC212
+0.2
0.35
16 %
100%
92%
0 0
-0.2
0.35
30%
for negative modulation
100% = 10% rest carrier
-0.4
0.7
0
10
20
30
40
DAC (HEX)
Fig. 59 Brightness control curve.
Fig. 60 Video output signal.
MBC211
100%
86%
72%
58%
44%
30%
10 12
22
26
32
36 40
44
48 52
56
60 64 s
Fig. 61 Test signal waveform.
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3.2 dB
10 dB
13.2 dB
13.2 dB
30 dB
30 dB
SC CC
PC
SC CC
PC
MBC213
BLUE
YELLOW
PC
SC
ATTENUATOR
TEST
CIRCUIT
SPECTRUM
ANALYZER
gain setting
adjusted for blue
CC
MBC210
Input signal conditions: SC = sound carrier; CC = colour carrier; PC = picture carrier.

All amplitudes with respect to top sync level.
V O at 3.58 or 4.4 MHz
Value at 0.92 or 1.1 MHz = 20 log ------------------------------------------------------------ + 3.6 dB
Value at 2.66 or 3.3 MHz = 20 log -----------------------------------------------------------V O at 2.66 or 3.3 MHz
Fig. 62 Test set-up intermodulation.
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Apr 16, 2002

18:39:04
- y1-axis -
225.0n
(LIN)
grp_55
_4.43M 197.853n
200.0n
- Subvar GD: 0.0
ST1: 0.0
ST0: 0.0
FILCON: 1.962
175.0n
150.0n
125.0n
100.0n
75.0n
50.0n
25.0n
0.0
-25.0n
0.0
1.0M
2.0M
500.0k
1.5M
3.0M
2.5M
4.0M
3.5M
Analysis: AC
5.0M
4.5M
F
(LIN)
User: nyoudees
Simulation date: 16-04-2002, 16:54:30
File: /user/nyoudees/kn10241d/simulation/kn10241d_sndgrp_sim/sndgrp_sim1/Pstar/schematic/netlist/sndgrp_sim1.c.sdif
Fig.63 Group delay characteristic without group delay correction (sound trap: 5.5 MHz)
Apr 16, 2002

18:51:44
- y1-axis -
400.0n
(LIN)
grp_gd
350.0n
- Subvar GD: 1.0
ST1: 0.0
ST0: 0.0
FILCON: 1.962
300.0n
250.0n
200.0n
_4.43M 177.613n
150.0n
100.0n
50.0n
_3.74M 406.163p
0.0
-50.0n
_2.42M -60.205n
-100.0n
0.0
1.0M
500.0k
2.0M
1.5M
3.0M
2.5M
Analysis: AC
User: nyoudees
4.0M
3.5M
(LIN)
5.0M
4.5M
F
Simulation date: 16-04-2002, 16:54:30
File: /user/nyoudees/kn10241d/simulation/kn10241d_sndgrp_sim/sndgrp_sim1/Pstar/schematic/netlist/sndgrp_sim1.c.sdif
Fig.64 Group delay characteristic with group delay correction (sound trap: 5.5 MHz)
2003 Nov 11
222
CONFIDENTIAL

CHARACTERISTIC POINTS AVL

Deemphasis voltage
UOCIII series
60
125
250
600
UNIT
mVRMS
1.8 V
Output voltage
1.0 V
0.1 V
10 mV
1V
100 mV
Deemphasis voltage
These curves are valid for an audio supply voltage of 5 V. When the supply voltage is increased to 8 V the audio
output signal is increased with 6 dB.
Fig. 65 AVL characteristic
2003 Nov 11
223
CONFIDENTIAL

UOCIII series
(V)
1.0
0.5
1.0
2.0
3.8
4.8
5.8
MHz
3.0
3.58
4.1
MHz
0.86
0.65
0.45
0.44
0.3
0.15
0.0
Fig.66 CCIR-18 multi-burst
(V)
0.5
1.5
2.0
1.0
0.65
0.45
0.3
0.15
0.0
Fig.67 100% amplitude FCC multi-burst
2003 Nov 11
224
CONFIDENTIAL

UOCIII series
Transition at top of field:

input:
line n-2
line n-1
line n
line n+1
line n+2
line n+3
line n+1
line n+2
line n+3
line n+1
line n+2
line n+3
line n+1
line n+2
output:
line n-2
line n-1
cross talk
Transition at bottom of field:
line n
cross talk
input:
line n-2
line n-1
line n
line n-1
line n
output:
line n-2
cross talk
line n+3
cross talk
Fig.68 Vertical transitions active video vertical blanking from line to line, PAL systems.
Transition at top of field:

input:
line n-2
line n-1
line n
line n+1
line n+2
line n+3
line n+1
line n+2
line n+3
line n+1
line n+2
line n+3
line n+2
line n+3
output:
line n-2
line n-1
line n
cross talk
Transition at bottom of field:
input:
line n-2
line n-1
line n
line n-1
line n
output:
line n-2
line n+1
cross talk
Fig.69 Vertical transitions active video vertical blanking from line to line, NTSC system
2003 Nov 11
225
CONFIDENTIAL

UOCIII series
Luminance
1
0.5
0
0
2 fsc
1 fsc
Detailed view:
Y
0.5
Comb depth at f = fSC

Y
Fig.70 Luminance transfer characteristic
2003 Nov 11
226
CONFIDENTIAL

UOCIII series
Chrominance
1
0.5
0
0
2 fsc
1 fsc
Comb depth at f = (284/283.75)fSC

Detailed view:
1
0.5
Fig.71 Chrominance transfer characteristic
2003 Nov 11
227
CONFIDENTIAL

UOCIII series
OUTPUT (IRE)
100
80
60
40
20
B
B
0
A
INPUT (IRE)
20
40
60
80
100
-20
A
A-A: MAXIMUM BLACK LEVEL SHIFT

B-B: LEVEL SHIFT AT 15% OF PEAK WHITE
Fig. 72 I/O relation of the black level stretch circuit (BSD = 0)
2003 Nov 11
228
CONFIDENTIAL

UOCIII series
red
V
I-axis
fully saturated colours
yellow
U
Fig.73 Skin tone correction range for the correction angle of 123 deg.
100%
YOUT
maximum
expansion
Expansion is dependent on the

setting of the WS1/WS0 bits
0%
0%
YIN
Fig.74 Gamma control characteristic
2003 Nov 11
229
CONFIDENTIAL
100%

UOCIII series
Gain
increase
WS1/WS0 = 1/1
10%
WS1/WS0 = 1/0
5%
WS1/WS0 = 0/1
10
20
30
40
50
APL-level
Output (%)
Fig.75 Gamma control (white stretch) characteristic; Gain increase as function of APL level and WS1/WS0 setting
104
BLUE (BLS=1)
100
RGB (BLS=0)
GREEN (BLS=1)
RED (BLS=1)
95
90
85
80
85
90
95
Fig.76 Blue stretch characteristic
2003 Nov 11
230
CONFIDENTIAL
100
Peak white level (%)

outputamplitude
UOCIII series
outputamplitude
SVMA = 0
SVMA = 1
soft-clipping
CRA0=0
1.8Vp-p
1.8Vp-p
CRA0=0
CRA0=1
CRA0=1
gain
gain
coring
50%
coring
100%
input-amplitude
(% of nominal input)
50%
100%
input-amplitude
(% of nominal input)
Fig.77 SVM Gain-curve
SVM gain
0dB
-3dB
-6dB
Horizontal position
Depending on VMA0, VMA1

curve at SPR2=1, SPR1=0 and SPR0=1
Fig.78 Parabola on the SVM output

2003 Nov 11
231
CONFIDENTIAL

UOCIII series
TOP
%
PICTURE
60
VERTICAL POSITION
50
138%
40
100%
30
75%
20
10
TIME
T/2
0
-10
-20
-30
-40
-50
-60
BOTTOM
PICTURE
BLANKING FOR EXPANSION OF 138%
Fig. 79 Vertical position and blanking pulse for 110 types
2003 Nov 11
232
CONFIDENTIAL

V-DRIVE
I-COIL
Measuring lines
Vertical blanking
Fig.80 Measuring lines in vertical overscan for vertical compressed scan
2003 Nov 11
233
CONFIDENTIAL
UOCIII series
Soft start
Soft stop
50
Frequency
HOUT = 2xFH
234
CONFIDENTIAL
TON
(%)
75

2003 Nov 11
100
25
57
73
50
1045
12
38
Fig. 81 Soft start and soft stop behaviour of horizontal output and timing picture tube discharge current
Discharge current
picture tube
UOCIII series
Time (ms)
2003 Nov 11
625
RESET LINE COUNTER
235
CONFIDENTIAL
RESET LINE COUNTER
RESET LINE COUNTER
Note 2: The vertical blanking is also dependent on the vertical Zoom and Scroll setting
Note 1: When OSVE and EVB are 1 the OSVE blanking value is valid
4 lines (OSVE and EVB = 0)

14 lines (OSVE = 1)
9 lines (EVB = 1)
Black current pulses
262
9.5 lines
60Hz
280
279
281
19
282
332
19
19
331
281
18
330
329
17
18
17
20
20
line 282.5 (OSVE and EVB = 0)

end line 292 (OSVE = 1)
line 285.5 (EVB = 1)
end line 20 (OSVE and EVB = 0)

end line 23 (EVB = 1)
line 335.5 (OSVE and EVB = 0)

end line 340 (EVB = 1)
336
end line 23 (OSVE and EVB = 0)

line 27.5 (EVB = 1)
23
Fig.82 Timing of vertical blanking and black current measuring pulses
14 lines
50Hz
2ND
FIELD
1ST
FIELD
FIELD
2ND
FIELD
1ST

Vert. Blank
Video
signal
525
4 lines (OSVE and EVB = 0)

14.5 lines (OSVE = 1)
9 lines (EVB = 1)
Vert. Blank
Reset Vert. Saw
internal
2fH clock
Video
signal
312
4.5 lines (OSVE and EVB = 0)

12 lines (OSVE = 1)
9.5 lines (EVB = 1)
Vert. Blank
Video
signal
4.5 lines (OSVE and EVB = 0)

12.5 lines (OSVE = 1)
9.5 lines (EVB = 1)
Vert. Blank
Reset Vert. Saw
internal
2fH clock
Video
signal
UOCIII series
2003 Nov 11
UOCIII series
236
CONFIDENTIAL
Fig.83 H/V timing output (CSY) on the flyback input pin (FBISO) in the LCD/100 Hz mode
14 lines
CSY
-1 REF
SYNC
2nd FIELD
CSY
14 lines
-1 REF
SYNC
1st FIELD


UOCIII series
2.4
clipper off
Soft clipping
range
(Defined by
SOC1/SOC0 bits)
1.8
RGBout
(Vb-w)
1.2
clipper on
0.6
20
60
40
00H
80
08H
100
0FH
120
130
CVBS IN (IRE)
PWL setting
Fig.84 Peak White Limiting / Soft clipper characteristic.
VIDEO
REF -1
BURST KEY
15 steps of 0.16 s
3.5 s
5.9 s
7.8 s
BLANKING
10.2 s
15 steps of 0.16 s
Fig.85 Timing of horizontal wide blanking
2003 Nov 11
237
CONFIDENTIAL

UOCIII series
TEST AND APPLICATION INFORMATION
The value of REW must be:
East-West output stage
V scan
R EW = R c ----------------------36 V ref
In order to obtain correct tracking of the vertical and

horizontal EHT-correction, the EW output stage should be
dimensioned as illustrated in Fig.86.
Example: With Vref = 1.95 V; Rc = 39 k and

Vscan = 120 V then REW = 68 k.
Resistor REW determines the gain of the EW output stage.

Resistor Rc determines the reference current for both the
vertical sawtooth generator and the geometry processor.
The preferred value of Rc is 39 k which results in a
reference current of 50 A (Vref = 1.95 V).
VDD
book, full pagewidth
HORIZONTAL
DEFLECTION
STAGE
V scan
DIODE
MODULATOR
V EW
R ew
TDA8366
TDA110XXH*
TDA 935X
TDA120XXH* 43
21
21
series
28
50
27
Rc
39 k
(2%)
I ref
EWD
EW output
stage
27
49
26
V ref
C saw
150
100nF
nF
(5%)
MLA744 - 1
Fig.86 East-West output stage
2003 Nov 11
238
CONFIDENTIAL

UOCIII series
700
IVERT 500
(A)
300
100
-100
-300
-500
-700
0
VA = 0, 20H and 3FH; VSH = 1FH; SC = 0EH.
T/2
TIME
VS = 0, 20H and 3FH; VA = 1FH; VSH = 1FH; SC = 0EH.
Fig. 87 Control range of vertical amplitude.
Fig. 88 Control range of vertical slope.
IVERT
(A)
600
400
200
0
-200
-400
-600
-1.0
VSH = 0, 20H and 3FH; VA = 1FH; SC = 0EH.
0.0
-250.0m
T/2
500.0m
250.0m
TIME
SC = 0, 0EH and 3FH; VA = 1FH; VSH = 1FH.
Fig. 89 Control range of vertical shift.
2003 Nov 11
-500.0m
-750.0m
Fig. 90 Control range of S-correction.
239
CONFIDENTIAL
1.0
750.0m

UOCIII series
IEW
(A)
500
IEW
(A)
1200
1000
400
800
300
600
200
400
100
200
0
0.0
400.0m
200.0m
T/2
800.0m
600.0m
TIME
T 1.0
0.0
400.0m
200.0m
T/2 600.0m TIME800.0m
1.0
PW = 0, 20H and 3FH; EW = 3FH; TC = 1FH; CP = 10H.

EW = 0, 20H and 3FH; PW = 3FH; TC = 1FH; CP = 10H.
Fig. 92 Control range of EW parabola/width ratio.
Fig. 91 Control range of EW width.
IEW
IEW
(A)
(A)
650
500
600
400
550
300
500
200
450
100
400
350
0
0.0
400.0m
200.0m
T/2600.0m
TIME800.0m
CP = 0, 20H and 3FH; EW = 3FH; PW = 3FH;TC = 1FH.
400.0m
200.0m
800.0m
T/2
600.0m
TIME
TC = 0, 20H and 3FH; EW = 1FH; PW = 1FH; CP = 10H.
Fig. 93 Control range of EW corner/parabola ratio.
2003 Nov 11
0.0
T 1.0
Fig. 94 Control range of EW trapezium correction.
240
CONFIDENTIAL

UOCIII series
IVERT
(A)
600
400
200
-200
-400
-600
0.0
400.0m
200.0m
800.0m
T/2
600.0m
VLIN = 0, 20H and 3FH; VA=1FH; VSH=1FH; SC=0
Fig.95 Vertical linearity control
2003 Nov 11
241
CONFIDENTIAL
TIME
1.0

Adjustment of geometry control parameters
The deflection processor offers the following parameters
for picture alignment, viz:
vertical amplitude
vertical slope
S-correction
vertical shift
Vertical zoom and vertical scroll
Vertical linearity correction, when required the linearity
setting of the upper and lower part of the screen can be
different.
horizontal shift.
EW width
EW parabola width
EW upper/lower corner parabola
EW trapezium correction.
Horizontal parallelogram and bow correction
It is important to notice that the ICs are designed for use
with a DC-coupled vertical deflection stage. This is the
reason why a vertical linearity alignment is not necessary
(and therefore not available).
For a particular combination of picture tube type, vertical
output stage and EW output stage it is determined which
are the required values for the settings of S-correction, EW
parabola/width ratio and EW corner/parabola ratio. These
parameters can be preset via the I2C-bus, and do not need
any additional adjustment. The rest of the parameters are
preset with the mid-value of their control range (i.e. 1FH),
or with the values obtained by previous TV-set
adjustments.
The vertical shift control is meant for compensation of
off-sets in the external vertical output stage or in the
picture tube. It can be shown that without compensation
these off-sets will result in a certain linearity error,
especially with picture tubes that need large S-correction.
The total linearity error is in first order approximation
proportional to the value of the off-set, and to the square of
the S-correction needed. The necessity to use the vertical
shift alignment depends on the expected off-sets in vertical
output stage and picture tube, on the required value of the
S-correction, and on the demands upon vertical linearity.
2003 Nov 11
UOCIII series
For adjustment of the vertical shift and vertical slope
independent of each other, a special service blanking
mode can be entered by setting the SBL bit HIGH. In this
mode the RGB-outputs are blanked during the second half
of the picture. There are 2 different methods for alignment
of the picture in vertical direction. Both methods make use
of the service blanking mode.
The first method is recommended for picture tubes that
have a marking for the middle of the screen. With the
vertical shift control the last line of the visible picture is
positioned exactly in the middle of the screen. After this
adjustment the vertical shift should not be changed. The
top of the picture is placed by adjustment of the vertical
amplitude, and the bottom by adjustment of the vertical
slope.
The second method is recommended for picture tubes that
have no marking for the middle of the screen. For this
method a video signal is required in which the middle of the
picture is indicated (e.g. the white line in the circle test
pattern). With the vertical slope control the beginning of the
blanking is positioned exactly on the middle of the picture.
Then the top and bottom of the picture are placed
symmetrical with respect to the middle of the screen by
adjustment of the vertical amplitude and vertical shift.
After this adjustment the vertical shift has the right setting
and should not be changed.
If the vertical shift alignment is not required VSH should be
set to its mid-value (i.e. VSH = 1F). Then the top of the
picture is placed by adjustment of the vertical amplitude
and the bottom by adjustment of the vertical slope. After
the vertical picture alignment the picture is positioned in
the horizontal direction by adjustment of the EW width and
the horizontal shift. Finally (if necessary) the left- and
right-hand sides of the picture are aligned in parallel by
adjusting the EW trapezium control.
To obtain the full range of the vertical zoom function the
adjustment of the vertical geometry should be carried out
at a nominal setting of the zoom DAC at position 19 HEX.
242
CONFIDENTIAL

UOCIII series
PACKAGE OUTLINE
QFP128: plastic quad flat package;
128 leads (lead length 1.95 mm); body 28 x 28 x 3.4 mm; lead angle 60 o
SOT320-3
c
y
X
A
96
65
97
64
ZE
A2
E HE
(A3)
A1
wM
Lp
bp
L
detail X
pin 1 index
33
128
1
32
wM
bp
ZD
v M A
HD
v M B
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
D(1)
E(1)
HD
HE
Lp
mm
3.95
0.25
0.05
3.70
3.15
0.25
0.45
0.30
0.23
0.11
28.1
27.9
28.1
27.9
0.8
32.2
31.6
32.2
31.6
1.95
0.95
0.55
0.25
0.2
0.1
ZD(1) ZE(1)
1.8
1.4
7o
0o
65o
55o
1.8
1.4
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT320-3
---
MO-112
2003 Nov 11
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
03-02-19
243
CONFIDENTIAL

UOCIII series
SOLDERING
WAVE SOLDERING
Introduction
Wave soldering is not recommended for QFP packages.

This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, for QFP

packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in
our IC package Databook (order code 9398 652 90011).
QFP
REFLOW SOLDERING
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For details,
refer to the Drypack information in our Quality Reference
Handbook (order code 9397 750 00192).
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 C.
2003 Nov 11
A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.
The footprint must be at an angle of 45 to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 C within
6 seconds. Typical dwell time is 4 seconds at 250 C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 C.
244
CONFIDENTIAL

UOCIII series
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2003 Nov 11
245
CONFIDENTIAL

Philips UOCIII-V1.8 Manual Entrenamiento

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INTEGRATED CIRCUITS

Versatile signal processor for low- and

BTSC stereo decoder

Analogue Video Processing (all versions)

Digital sound processing circuit

Multi-standard vision IF circuit with alignment-free PLL

Digital video processing circuit

Internal (switchable) time-constant for the IF-AGC circuit

The UOCIII series consists of the following 3 basic

Switchable group delay correction and sound trap (with

Stereo versions. These versions contain the TV

DVB/VSB IF circuit for preprocessing of digital TV

AV stereo versions. These versions contain the TV

Automatic Y/C signal detector

Mono sound versions. These versions contain the TV

Integrated luminance delay line with adjustable delay

The most important features of the complete IC series are

Switchable DC transfer ratio for the luminance signal

UOCIII is supported by a comprehensive Global TV

Multi-standard colour decoder with automatic search

(1) Both standard and face down versions of the QFP128

Versatile signal processor for low- and

Linear RGB/YPBPR input with fast insertion.

AM demodulator without extra reference circuit

Tint control for external RGB/YPBPR signals

The FM-PLL demodulator can be set to centre

Contrast reduction possibility during mixed-mode of

Switch to select between 2nd SIF from QSS

Vertical count-down circuit

Audio Interfaces and switching (stereo versions with

Horizontal and vertical geometry processing with

Audio switch circuit with 4 stereo inputs, a stereo output

Low-power start-up of the horizontal drive circuit

AVL (Automatic Volume Levelling) circuit for the

Analogue video processing (stereo versions)

Digital input crossbar switch for all digital signal sources

Analogue video processing (mono versions)

Digital output crossbar for exchange of channel

The low-pass filtered mixed down I signal is available

Digital audio input interface (stereo I2S input interface)

Digital Video Processing (some versions)

Audio interfaces and switching (AV stereo versions

Linear and non-linear horizontal scaling of the video

Audio switch circuit with 4 stereo inputs, a stereo output

Versatile signal processor for low- and

Audio interfaces and switching (mono versions)

Automatic Volume Level (AVL) control

Master volume control

Stereo Demodulator and Decoder (full stereo

Demodulator and Decoder Easy Programming (DDEP)

Auto standard detection (ASD)

Dynamic Bass Boost (DBB) (2)

Static Standard Selection (SSS)

Dynamic Virtual Bass (DVB) (3)

DQPSK demodulation for different standards,

BBE Sound processing (4)

NICAM decoding (B/G, I, D/K and L standard)

Two-carrier multistandard FM demodulation (B/G, D/K

Processed or non processed subwoofer

Decoding for three analog multi-channel systems (A2,

Reflection and delay for loudspeaker channels

Adaptive de-emphasis for satellite FM

Dolby Pro Logic Delay (1)