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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 62, NO. 5, MAY 2015
I. I NTRODUCTION
OGARITHMIC signal processing (LSP) has been proposed as a viable alternative to fixed- and floating-point
binary signal processing for many years. The properties of
logarithmic arithmetic make it particularly suitable for applications where a high dynamic range and relatively low
absolute accuracy can be used or when logarithms simplify
the arithmetic processing needed in computationally intensive algorithms [1], [2]. LSP can be also used with lowpower very-large-scale integration implementation [3], which
can be useful in low-power applications when the cost of
conversion to and from the logarithmic domain can be justified. Recently, there has been increased interest in the
use of LSP techniques on field-programmable gate arrays
(FPGAs). Recently, a number of new conversion algorithms
have been developed, and existing conversion algorithms have
been reevaluated for efficient implementation using FPGA resources [4], [5]. This brief presents an implementation of an
algorithm previously presented in [6] that has been adapted
Manuscript received July 21, 2014; revised October 14, 2014; accepted
December 16, 2014. Date of publication December 25, 2014; date of current version April 23, 2015. This brief was recommended by Associate
Editor S. Hu.
The authors are with the School of Engineering and Digital Arts, University
of Kent, Canterbury CT2 7NT, U.K. (e-mail: MC539@kent.ac.uk; P.Lee@kent.
ac.uk).
Digital Object Identifier 10.1109/TCSII.2014.2386252
(1)
where S is the sign bit, I and F are the integer and fractional (or mantissa) parts, respectively, of the logarithm base 2,
and Z is used to represent the special case of x = 0. The
derivation of Z, S, and I is straightforward and not discussed
further in this brief. However, the conversion to and from
the log domain requires the approximation of nonlinear terms
log2 (1.F ) for linear-to-log (Lin2Log) conversion and 20.F for
log-to-linear (Log2Lin) conversion. This brief concentrates on
the conversion of a normalized number 1 1.F < 2, where
F represents the fractional component, although the approach
described in this brief can be also applied to an approximation
of 20.F .
Early algorithms for approximating log2 (1.F ) were based on
improvements to the simple linear interpolation first proposed
by Mitchell in 1962 [9]. Subsequent papers have proposed
improvements to the basic Mitchell architecture, which have
been achieved through the use of more complex curve fitting
and/or error correction techniques that only require simple
arithmetic components.
For higher accuracy, lookup tables (LUTs) have been used.
However, for resolutions of 16 bits and beyond, the direct
use of LUTs becomes prohibitively large, and many methods
for reducing the size of LUTs while maintaining conversion
accuracy have been proposed and published. Most are based
on piecewise linear (PWL) or piecewise polynomial (PWP)
approximation techniques that reduce the size of the LUTs by
using more complex arithmetic components (e.g., multipliers
and adders) [10], [11]. Chaudhary and Lee [6] revisited a twostep algorithm first proposed in a patent attributed to Larson
1549-7747 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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CHAUDHARY AND LEE: IMPROVED TWO-STEP BINARY LOGARITHMIC CONVERTER FOR FPGAs
477
(2)
k
Fki 2i .
i=1
(3)
Larsons algorithm is based on an extension of the work
initially presented by Kmetz [13] and Maenner [14]. Kmetz
[13] used a LUT to approximate the difference (or error), i.e.,
, between a log2 (1.F ) and log2 (1.F ), i.e.,
= log2 (1.F ) a log2 (1.F )
(4)
where the n least significant bits of 1.F are used as the address
of the LUT containing 2n values of . F is partitioned into
p = 2m segments using the m most significant bits of F . Each
k
i=km1
Fki 2i + Sp
(6)
478
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 62, NO. 5, MAY 2015
TABLE I
LUT C OEFFICIENT B ITS [6]
The algorithm is implemented using two stages. Stage 1 contains a PWL approximation of the log function. The coefficient
LUT contains values for Ap and Bp , as well as scaling factor
Sp . Stage 2 is a PWL approximation of the error curve and
contains an additional multiplier to scale the curve.
It should be noted that the error curve generated for LUT2
is using a second-stage PWL, as shown in Fig. 2. The scaled
version of the normalized error curve is then added to the
first-stage PWL approximation of the log function to reduce
the overall conversion error. LUT1 is used to store the zeroth
(A) and first-order (B) coefficients of the PWL approximation
together with a scaling factor (S), which is used to multiply
the normalized error curve approximated using the PWL coefficients (A and B ) and stored in LUT2.
Although Larson [12] did not describe how this normalized
error curve was derived, Chaudhary and Lee [6] have analyzed
and verified some simple methods for deriving a curve that
produces the minimum (root mean square) error approximation
This was assessed for a normalized input with 23 bits of
fractional precision. Each configuration produced a conversion
error of less than 1 unit of last place (ULP), where 1 ULP =
223 = 1.19 107 . The results presented in [6] for different
LUT sizes for a 23-bit conversion are reproduced here in Table I
for reference.
Fig. 4. Residual error produced after approximating the normalized curve (as
shown in Fig 3) using a symmetrical approximation.
CHAUDHARY AND LEE: IMPROVED TWO-STEP BINARY LOGARITHMIC CONVERTER FOR FPGAs
479
Fig. 5. Residual error in the normalized error curve approximation (as shown
in Fig 3).
Fig. 7. (a) Overall error obtained in the approximation. (b) Histogram of the
approximated error distribution.
480
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 62, NO. 5, MAY 2015
TABLE II
LUT C OEFFICIENT B ITS
TABLE III
D EVICE U TILIZATION S TATISTICS
TABLE IV
U TILIZATION C OMPARISON
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pp. 113116.
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Jan. 2014.
[7] M. Haselman et al., A comparison of floating point and logarithmic
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Apr. 2005, pp. 181190.
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Aug. 1962.
[10] F.-S. Lai, A 10 ns hybrid number system data execution unit for digital
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pp. 590599, Apr. 1991.
[11] M. Arnold and M. Winkel, A single-multiplier quadratic interpolator for
INS arithmetic, in Proc. ICCD, 2001, pp. 178183.
[12] K. Larson, Floating point to logarithm converter, U.S. Patent 5 365 465.
Nov. 15, 1994, [Online]. Available: https://www.google.com/patents/
US5365465
[13] G. Kmetz, In a digital computation system, U.S. Patent 4 583 180.
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