Basic Concept of HDL

Graduate Institute of Electronics Engineering, NTU
Basic Concept of HDL

Lecturer: Huai-Yi Hsu ()
Date: 2004.03.05
ACCESS IC LAB
Outline
Hierarchical Design Methodology
Basic Concept of Verilog HDL
Switch Level Modeling
Gate Level Modeling
Simulation & Verification Tools
Basic Concept 2004.03.05
Huai-Yi Hsu
pp. 2
What is Verilog HDL ?

Hardware Description Language
Mixed level modeling
Behavioral
Algorithmic ( like high level language)
Register transfer (Synthesizable)
Structural
Gate (AND, OR )
Switch (PMOS, NOMS, JFET )
Single language for design and simulation

Built-in primitives and logic functions
User-defined primitives
Built-in data types
High-level programming constructs
Huai-Yi Hsu
pp. 3
Hierarchical Modeling Concept

Understand top-down and bottom-up design
methodologies
Explain differences between modules and
module instances in Verilog
Describe four levels of abstraction
Huai-Yi Hsu
pp. 4
Top-down Design Methodology

We define the top-level block and identify the sub-blocks
necessary to build the top-level block.
We further subdivide the sub-blocks until we come to leaf cells,
which are the cells that cannot further be divided.
Top level
block
sub
block 1
leaf
cell
leaf
cell
sub
block 2
leaf
cell
leaf
cell
sub
block 3
leaf
cell
Huai-Yi Hsu
sub
block 4
leaf
cell
leaf
cell
leaf
cell
pp. 5
Bottom-up Design Methodology

We first identify the building block that are available to us.
We build bigger cells, using these building blocks.
These cells are then used for higher-level blocks until we build
the top-level block in the design.
Top level
block
macro
cell 1
leaf
cell
leaf
cell
macro
cell 2
leaf
cell
leaf
cell
macro
cell 3
leaf
cell
Huai-Yi Hsu
macro
cell 4
leaf
cell
leaf
cell
leaf
cell
pp. 6
Example: 16-bit Adder

Add_rca_16
M1
M2
M3
Add_rca_4
Add_rca_4
Add_rca_4
Add_rca_4
M1
M2
M3
M4
Add_full
xor
nand
Add_full
M4
Add_full
Add_full
M1
M2
M3
M4
Add_half
Add_half
norf201
invf101
not
xor
nand
not
[HW]
Huai-Yi Hsu
pp. 7
Design Encapsulation
Encapsulate structural and functional details in a
module
module <Module Name> (<PortName List>);
// Structural part
<List of Ports>
<Lists of Nets and Registers>
<SubModule List> <SubModule Connections>
// Behavior part
<Timing Control Statements>
<Parameter/Value Assignments>
<Stimuli>
<System Task>
endmodule
Encapsulation makes the model available for

instantiation in other modules
Huai-Yi Hsu
pp. 8
Instances
A module provides a template from which you can
create actual objects.
When a module is invoked, Verilog creates a unique
object from the template.
Each object has its own name, variables, parameters
and I/O interface.
Huai-Yi Hsu
pp. 9
Hierarchical Design Example

Model complex structural detail by instantiating modules within modules
Add_full_0_delay
c_in
a
b
(a b) c_in
sum
a
Add_half_0_delay
sum w1
a
b
Add_half_0_delay
(ab)
b
c_out
w2
ab
c_out
sum
c_out
(a + b) c_in + ab
module Add_full_0_delay (sum, c_out, a, b, c_in);

input a, b, c_in;
output c_out, sum;
module instance
wire w1, w2, w3;
name
MODELING TIP
Add_half_0_delay M1 (w1, w2, a, b);

Add_half_0_delay M2 (sum, w3, c_in, w1);
or (c_out, w2, w3);
endmodule
MODELING TIP
w3
(a b) c_in
Use nested module instantiations to create a top-down

design hierarchy.
The ports of a module may be listed in any order.

The instance name of a module is required.
Huai-Yi Hsu
pp. 10
Verilog Language Rules

Verilog is a case sensitive language (with a few exceptions)
Identifiers (space-free sequence of symbols)
upper and lower case letters from the alphabet

digits (0, 1, ..., 9)
underscore ( _ )
$ symbol (only for system tasks and functions)
Max length of 1024 symbols
Terminate lines with semicolon ;

Single line comments:
// A single-line comment goes here
Multi-line comments:
/* Do not /* nest multi-line comments*/ like this */
Huai-Yi Hsu
pp. 11
Language Conventions
Case-sensitivity
Verilog is case-sensitive.
Some simulators are case-insensitive
Advice: - Dont use case-sensitive feature!
Keywords are lower case
Different names must be used for different items

within the same scope
Identifier alphabet:
Upper and lower case alphabeticals
decimal digits
underscore
Huai-Yi Hsu
pp. 12
Language Conventions (contd)

Maximum of 1024 characters in identifier
First character not a digit
Statement terminated by ;
Free format within statement except for within quotes
Comments:
All characters after // in a line are treated as a
comment
Multi-line comments begin with /* and end with */
Compiler directives begin with // synopsys

Built-in system tasks or functions begin with $
Strings enclosed in double quotes and must be on a
single line
Huai-Yi Hsu
pp. 13
Verilog Basis Cell

Verilog Basis Components
parameter declarations
nets or reg declarations
port declarations
Continuous assignments
Module instantiations
Gate instantiations
Function definitions
always blocks
task statements
Huai-Yi Hsu
pp. 14
Port Declaration
Three port types
Input port
input a;
Output port
output b;
Bi-direction port
module
inout c;
input
output
reg or net net
reg or net
inout
net
net
net
Huai-Yi Hsu
pp. 15
Data Types
nets are further divided into several net types
wire, wand, wor, tri, triand, trior, supply0, supply1
registers - stores a logic value - reg

integer - supports computation 32-bits signed
time - stores time 64-bit unsigned
real - stores values as real numbers
realtime - stores time values as real numbers
event an event data type
Wires and registers can be bits, vectors, and
arrays
Huai-Yi Hsu
pp. 16
Integer, Real, & Time

integer counter;
initial counter = -1;
real delta;
initial delta = 4e10;
time sim_time;
initial sim_time = $time;
Huai-Yi Hsu
pp. 17
Data Types
Nets ( wire or reg (in combinational always block)
Connects between structural elements
Must be continuously driven by
Continuous assignment (assign)
Module or gate instantiation (output ports)
Default initial value for a wire is Z
Registers ( reg (in sequential always block) )

Represent abstract data storage elements
Updated at an edge trigger event and holds its value until
another edge trigger event happens
Default initial value for a wire is X
Huai-Yi Hsu
pp. 18
Net Types
The most common and important net types
wire and tri
for standard interconnection wires
supply 1 and supply 0
Other wire types

wand, wor, triand, and trior
for multiple drivers that are wired-anded and wired-ored
tri0 and tri1

pull down and pull up
trireg
for net with capacitive storage
If all drivers at z, previous value is retained
Huai-Yi Hsu
pp. 19
Register Types
reg
any size, unsigned
integer (not synthesizable)

integet a,b; // declaration
32-bit signed (2s complement)
time (not synthesizable)

64-bit unsigned, behaves like a 64-bit reg
$display(At %t, value=%d,$time,val_now)
real, realtime (not synthesizable)

real c,d; //declaration
64-bit real number
Defaults to an initial value of 0
Huai-Yi Hsu
pp. 20
Wire & Reg

wire(wand, wor, tri)
Physical wires in a circuit
Cannot assign a value to a wire within a function or a
begin..end block
A wire does not store its value, it must be driven by
by connecting the wire to the output of a gate or module
by assigning a value to the wire in a continuous assignment
An un-driven wire defaults to a value of Z (high impedance).

Input, output, inout port declaration -- wire data type
(default)
Huai-Yi Hsu
pp. 21
Wire & Reg

reg
A variable in Verilog
Use of reg data type is not exactly synthesized to a

really register.
Use of wire & reg
When use wire usually use assign and assign does
not appear in always block
When use reg only use a=b , always appear in
always block
module
module test(a,b,c,d);
test(a,b,c,d);
input
input a,b;
a,b;
output
output c,d;
c,d;
reg
reg d;
d;
assign
assign c=a;
c=a;
always
always @(b)
@(b)
d=b;
d=b;
endmodule
endmodule
Huai-Yi Hsu
pp. 22
Wired Logic
The family of nets includes the types wand and wor
A wand net type resolves multiple driver as wired-and logic
A wor net type resolves multiple drivers as wired-or logic
The family of nets includes supply0 and supply1

supply0 has a fixed logic value of 0 to model a ground
connection
supply1 has a fixed logic value of 1 to model a power
connection
Huai-Yi Hsu
pp. 23
Data Type - Examples

reg
wand
reg
tri
reg
trireg
a;
b;
[3:0]
c;
[7:0]
bus;
[1:4]
d;
(small) store;
// scalar register
// scalar net of type wand
// 4-bit register
// tri-state 8-bit bus
// 4-bit
// specify logical strength (rare used)
wire/tri truth table

0
a
c
b
wand/triand
wor/trior
Huai-Yi Hsu
pp. 24
Vector
wire and reg can be defined vector, default is 1bit
vector is multi-bits element
Format: [High#:Low#] or [Low#:High#]
Using range specify part signals
wire
a;
wire [7:0] bus;
reg
clock;
reg [0:23] addr;
// scalar net variable, default

// 8-bit bus
// scalar register, default
// Vector register, virtual address 24 bits wide
bus[7]
// bit #7 of vector bus
bus[2:0] // Three least significant bits of vector bus
// using bus[0:2] is illegal because the significant bit should
// always be on the left of a range specification
addr[0:1] // Two most significant bits of vector addr
Huai-Yi Hsu
pp. 25
Array
Arrays are allowed in Verilog for reg, integer, time,
and vector register data types.
Multidimensional array are not permitted in Verilog.
integer
reg
time
reg [4:0]
integer
count[0:7];
bool[31:0];
chk_ptr[1:100];
port_id[0:7];
matrix[4:0][4:0]
count[5]
chk_ptr[100]
port_id[3]
// An array of 8 count variables

// Array of 32 one-bit Boolean register variables
// Array of 100 time checkpoint variables
// Array of 8 port_id, each port_id is 5 bits wide
// Illegal declaration
// 5th element of array of count variables

// 100th time check point value
// 3rd element of port_id array. This is a 5-bit value
Huai-Yi Hsu
pp. 26
Memories
In digital simulation, one often needs to model register files,
RAMs, and ROMs.
Memories are modeled in Verilog simply as an array of registers.
Each element of the array is known as a word, each word can
be one or more bits.
It is important to differentiate between
n 1-bit registers
One n-bit register
reg mem1bit[0:1023];
// Memory mem1bit with 1K 1-bit words
reg [7:0] mem1byte[0:1023]; // Memory mem1byte with 1K 8-bit words
mem1bit[255]
Mem1byte[511]
// Fetches 1 bit word whose address is 255

// Fetches 1 byte word whose address is 511
Huai-Yi Hsu
pp. 27
Strings
String: a sequence of 8-bits ASCII values
module string;
reg [8*14:1] strvar;
initial
begin
strvar = Hello World;
strvar = Hello World!!;
end
endmodule
// stored as 000000486561726c64
// stored as 00486561726c642121
Special characters
\n newline
\\ \ character
%% % character
\t tab character
\ character
\abc ASCII code
Huai-Yi Hsu
pp. 28
Four-valued Logic
Verilogs nets and registers hold four-valued data
0 represent a logic zero or false condition
1 represent a logic zero or false condition
z
Output of an undriven tri-state driver
high-impedance value
Models case where nothing is setting a wires value
x
Models when the simulator cant decide the value uninitialized
or unknown logic value
Initial state of registers
When a wire is being driven to 0 and 1 simultaneously
Output of a gate with z inputs
Huai-Yi Hsu
pp. 29
Logic System
Four values: 0, 1, x or X, z or Z
// Not case sensitive here
The logic value x denotes an unknown (ambiguous) value

The logic value z denotes a high impedance
Primitives have built-in logic

Simulators describe 4-value logic (see Appendix A in text)
a
b
a
b
y
Huai-Yi Hsu
x z
x z
x z
x z
pp. 30
Resolution of Contention Between Drivers

The value on a wire with multiple drivers in contention may be x
Huai-Yi Hsu
pp. 31
Logic Strength Levels

Types of strengths
Charge strength: trireg (large>medium>small)
Drive strength: <Net> (supply>strong>pull>weak)
Syntax
<NetType> <Strength> <Range>
trireg
(large)
[1:4]
<Delay>
#5
<Variables>;
c1;
Strength level
weakest
strongest
highz small medium weak large pull strong supply
Huai-Yi Hsu
pp. 32
Number Representation
Format: <size><base_format><number>
<size> - decimal specification of number of bits
default is unsized and machine-dependent but at least 32 bits
<base format> - ' followed by arithmetic base of number

<d> <D> - decimal - default base if no <base_format> given
<h> <H> - hexadecimal
<o> <O> - octal
<b> <B> - binary
<number> - value given in base of <base_format>

_ can be used for reading clarity
If first character of sized, binary number 0, 1, x or z, will extend
0, 1, x or z (defined later!)
Huai-Yi Hsu
pp. 33
Number Representation
Examples:
6b010_111
8b0110
4bx01
16H3AB
24
5O36
16Hx
8hz
gives 010111
gives 00000110
gives xx01
gives 0000001110101011
gives 00011000
gives 11100
gives xxxxxxxxxxxxxxxx
gives zzzzzzzz
Huai-Yi Hsu
pp. 34
Net Concatenations
A easy way to group nets
Representation
Meanings
{cout, sum}
{cout, sum}
{b[7:4],c[3:0]}
{b[7], b[6], b[5], b[4], c[3], c[2], c[1], c[0]}
{a,b[3:1],c,2b10}
{a, b[3], b[2], b[1], c, 1b1, 1b0}
{4{2b01}}
8b01010101
{{8{byte[7]}},byte}
Sign extension
Huai-Yi Hsu
pp. 35
Parameter Declaration
Parameters are not variables, they are constants.
Typically parameters are used to specify delays and
width of variables
Examples
module var_mux(out, i0, i1, sel);

parameter width = 2, delay = 1;
output [width-1:0] out;
input [width-1:0] i0, i1;
input sel;
If sel = 1, then i1 will be assigned to out;

If sel = 0, then i0 will be assigned to out;
assign #delay out = sel ? I1 : i0;

endmodule
Huai-Yi Hsu
pp. 36
Overriding the Values of Parameters

Module instance parameter value assignment.
Cannot skip any parameter assignment even you do
not want to reassign it.
module top;
wire [1:0] a_out, a0, a1;

wire [3:0] b_out, b0, b1;
wire [2:0] c_out, c0, c1;
var_mux
var_mux #(4,2)
var_mux #(3, )
endmodule
The order of assign of parameters

follows the order of declaration of
Parameters in the module.
U0(a_out, a0, a1, sel);

U1(b_out, b0, b1, sel);
U2(c_out, c0, c1, sel);
Huai-Yi Hsu
You cannot skip the delay

parameter assignment.
pp. 37
Overriding the Values of Parameters

You can use defparam to group all parameter value
override assignment in one module.
module top;
wire [1:0] a_out, a0, a1;

wire [3:0] b_out, b0, b1;
wire [2:0] c_out, c0, c1;
var_mux U0(a_out, a0, a1, sel);
var_mux U1(b_out, b0, b1, sel);
var_mux U2(c_out, c0, c1, sel);
endmodule
Huai-Yi Hsu
module annotate;
defparam
top.U0.width = 2;
top.U0.delay = 1;
top.U1.width = 4;
top.U1.delay = 2;
top.U2.width = 3;
top.U2.delay = 1;
endmodule
pp. 38
Gate and Switch Level Modeling

Primitives: bottom level of the hierarchy
Verilog Gate Level Primitives
User-defined Primitives (UDP): described by truth table
Conventional modules
Behavior statements
Structural statements
Switch Level Modeling (using transistors)
Delay Specification
Specify gate delay
Specify module path delay
Huai-Yi Hsu
pp. 39
Verilog Built-in Primitives

Ideal
MOS switch
Resistive
gates
and
buf
nmos
rnmos
pullup
nand
not
pmos
rpmos
pulldown
or
bufif0
cmos
rcmos
nor
bufif1
tran
rtran
xor
notif0
tranif0 rtranif0
xnor
notif1
tranif1 rtranif1
Huai-Yi Hsu
pp. 40
MOS Switches
Two types of MOS switches can be defined with the keywords, nmos
and pmos
nmos is used to model NMOS transistors
nmos n1(out, data, control);
pmos is used to model PMOS transistors

pmos p1(out, data, control);
out
data
out
data
control
control
NMOS transistor
PMOS transistor
Huai-Yi Hsu
H: stands for 1 or z
L: stands for 0 or z
pp. 41
CMOS Switches
CMOS switches are declared with the keyword cmos.
A cmos device can be modeled with a nmos and a
pmos device.
cmos c1(out, data, ncontrol, pcontrol);
The cmos gate is essentially a combination of two

gates: one nmos and one pmos.
nmos n1(out, data, ncontrol);
pmos p1(out, data, pcontrol);
pcontrol
out
data
ncontrol
CMOS
Huai-Yi Hsu
pp. 42
Bidirectional Switches
NMOS, PMOS, CMOS gates conduct from drain to source.
It is important to have devices that conduct in both directions.
In such cases, signals on either side of the device can be the
driver signal.
Bidirectional switches are typically used to provide isolation
between buses or signals.
tran
tranif0
tranif1
t1(inout1, inout2);
t2(inout1, inout2, control);
t3(inout1, inout2, control);
control
inout1
inout2
tran
inout1
control
inout2
tranif1
Huai-Yi Hsu
inout1
inout2
tranif0
pp. 43
Power and Ground

The power (Vdd, logic 1) and Ground (Vss, logic 0) sources are needed
when transistor-level circuits are designed.
Supply1 are equivalent to Vdd in circuits and place a logical 1 on a net.
Supply0 are equivalent to ground or Vss in circuits and place a logical 0
on a net.
supply1
supply0
vdd;
gnd;
assign a = vdd;
assign b = gnd;
// connect a to vdd
// connect b to gnd
Huai-Yi Hsu
pp. 44
Resistive Switches
Resistive switches have the same syntax as regular switches.
Resistive devices have a high source-to-drain impedance. Regular
switches have a low source-to-drain impedance.
Resistive switches reduce signal strengths when signals pass through.
Regular switches retain strength levels of signals from input to output.
Input Strength
Output Strength
Supply
Pull
Strong
Pull
Pull
Weak
Weak
Medium
Large
Medium
Medium
Small
Small
Small
High
High
Huai-Yi Hsu
pp. 45
Switches Example
a
out
// Define our own nor gate: nor_sw

module nor_sw (out, a, b);
output
input
pwr
out;
a, b;
// internal wires
wire c;
out
// set up power and ground lines

supply1 pwr;
supply0 gnd;
//instantiate pmos switches

pmos (c, pwr, b);
pmos (out, c, a);
//instantiate nmos switches
nmos (out, gnd, a);
nmos (out, gnd, b);
gnd
endmodule
Huai-Yi Hsu
pp. 46
Primitives & UDP

Primitives are simple modules
Verilog build-in primitive gate
not, buf:
Variable outputs, single input (last port)
and, or, xor, nand, nor, xnor:

Single outputs (first port), variable inputs
User defined primitive (UDP)

Single output (first port), variable inputs
The function is specified by a truth table
Z state is not allowed
Huai-Yi Hsu
pp. 47
Truth-Tables Models and UserDefined Primitives

Built-in primitives are for simple combinational logic gates and CMOS transistors
Primitives are memory efficient and simulate fast (good for ASIC libraries)
User-defined primitives accommodate combinational and sequential logic
Scalar output and multiple scalar inputs
Arrange inputs columns of truth table in same order as ports
Put output in last column, separated by :
Use a UDP like a built-in primitive
Table is searched top to bottom until match is found
z may not be used in table (z in simulation is treated as x)
No match results in propagation of x
See web site for more details
Huai-Yi Hsu
pp. 48
Example UDP
select
primitive mux_prim (mux_out, select, a, b);

output mux_out;
0
input
select, a, b;
mux_prim
mux_out
table
1
// select a
b
:
mux_out
0
0
0
:
0;
// Order of table columns = port order of inputs
0
0
1
:
0;
// One output, multiple inputs, no inout
0
0
x
:
0;
// Only 0, 1, x on input and output
0
1
0
:
1;
// A z input in simulation is treated as x
0
1
1
:
1;
// by the simulator
0
1
x
:
1;
// Last column is the output
// select a
b
:
mux_out
1
0
0
:
0;
1
1
0
:
0;
1
x
0
:
0;
1
0
1
:
1;
1
1
1
:
1;
1
x
1
:
1;
x
0
0
:
0;
// Reduces pessimism
x
1
1
:
1;
endtable
// Note: Combinations not explicitly specified will drive x
endprimitive
// under simulation.
Huai-Yi Hsu
pp. 49
Alternative model
table
// Shorthand notation:
// ? represents iteration of the table entry over the values 0,1,x.
// i.e., don't care on the input
select
0
0
0
1
?
?
:
:
0;
1;
1
1
?
?
0
1
:
:
0;
1;
?
0
?
1
endtable
0
1
:
:
0;
1;
mux_out
Huai-Yi Hsu
// ? = 0, 1, x shorthand notation.
pp. 50
UDPS FOR Sequential Logic

Output is viewed as next state
Insert a column for the present state truth
Declare output to have type reg
MODELING TIP
The output of a sequential user-defined primitive must be
declared to have type reg.
Huai-Yi Hsu
pp. 51
Example: Transparent Latch

primitive latch_rp (q_out, enable, data);
output q_out;
input enable, data;
reg
q_out;
table
//
enable data
1
1
1
0
0
?
:
:
:
state
?
?
?
q_out/next_state
:
1;
:
0;
:
- ;
// Above entries do not deal with enable = x.

// Ignore event on enable when data = state:
x
x
0
1
:
:
0
1
:
:
-;
-;
// Note: The table entry '-' denotes no change of the output.

endtable
endprimitive
Huai-Yi Hsu
pp. 52
Example: D-Type Flip-Flop

Notation for rising edge transition: (01), (0x), (x1)
Notation for falling edge transition: (10), 1x), (x0)
primitive d_prim1 (q_out, clock, data);
output q_out;
input clock, data;
reg
q_out;
table
// clk
data : state : q_out/next_state
(01)
0 :
? :
0 ; // Rising clock edge
(01)
1 :
? :
1;
(0?)
1 :
1 :
1;
(?0)
data
q_out
d_prim1
clock
? :
- ;
// Falling or steady clock edge
?
(??) :
endtable
endprimitive
- ;
// Steady clock, ignore data transitions
Huai-Yi Hsu
pp. 53
Example: JK-Type Flip-Flop

Level-sensitive and edge-sensitive behavior can be
mixed in a UDP
Place level-sensitive behavior a the top of the table
preset
q_out
j
k
clk
clear
J-K functionality:
- preset and clear override clock
- no change if j=0, k=0
- drive to 1 if j=1, k=0
- drive to 0 if j=0, k=1
- toggle if j=1, k=1
Huai-Yi Hsu
pp. 54
primitive jk_prim (q_out, clk, j, k, preset, clear);

output
q_out;
input
clk, j, k, preset, clear;
reg q_out;
table
//
clk
j
k
pre
// Preset Logic
?
?
?
0
?
?
?
*
// Clear Logic
?
?
?
1
?
?
?
1
// Normal Clocking
//
clk
j
k
pre
r
0
0
0
r
0
0
1
r
0
1
1
r
1
0
1
r
1
1
1
r
1
1
1
f
?
?
?
// j and k cases
//
clk
j
k
pre
b
*
?
?
b
?
*
?
// Reduced pessimism
p
0
0
1
p
0
?
1
p
?
0
?
(?0)
?
?
?
(1x)
0
0
1
(1x)
0
?
1
(1x)
?
0
?
x
*
0
?
x
0
*
1
endtable
endprimitive
clr
1
1
state q_out/next_state
:
:
0
*
:
:
clr
0
1
1
1
1
1
?
:
:
:
:
:
:
?
1
:
:
1;
1;
?
0
:
:
0;
0;
0
:
?
:
?
:
?
:
0
:
1
:
?
:
1;
- ;
0;
1;
1;
0;
-;
clr
?
?
:
:
?
:
?
:
-;
-;
1
?
1
?
1
?
1
1
?
:
:
:
:
:
:
:
:
:
?
0
1
?
?
0
1
1
0
:
:
:
:
:
:
:
:
:
-;
-;
-;
-;
-;
-;
-;
-;
-;
Note: * denotes any transition, and is equivalent to (??)

Huai-Yi Hsu
pp. 55
Timing and Delays
ACCESS IC LAB
Timing and Delay

Functional verification of hardware is used to verify functionality
of the designed circuit.
However, blocks in real hardware have delays associated with
the logic elements and paths in them.
Therefore, we must also check whether the circuit meets the
timing requirements, given delay specifications for the blocks.
Huai-Yi Hsu
pp. 57
Delay Specification in Primitives

Delay specification defines the propagation
delay of that primitive gate.
not #10 (out,in);
Huai-Yi Hsu
pp. 58

Verilog supports (rise, fall, turn-off) delay
specification.
Huai-Yi Hsu
pp. 59

All delay specification in Verilog can be specified as
(minimum : typical : maximum) delay
Examples
(min:typ:max) delay specification of all transition
or #(3.2:4.0:6.3) U0(out, in1, in2);
(min:typ:max) delay specification of RISE transition and

FALL transition
nand #(1.0:1.2:1.5,2.3:3.5:4.7) U1(out, in1, in2);
(min:typ:max) delay specification of RISE transition, FALL

transition, and turn-off transition
bufif1 #(2.5:3:3.4,2:3:3.5,5:7:8) U2(out,in,ctrl);
Huai-Yi Hsu
pp. 60
Types of Delay Models

Distributed Delay
Specified on a per element basic
Delay value are assigned to individual in the circuit
a
b
#5
e
#4
c
d
#7
out
module and4(out, a, b, c, d);
and #5 a1(e, a, b);

and #7 a2(f, c, d);
and #4 a3(out, e, f);
endmodule
Huai-Yi Hsu
pp. 61

Lumped Delay
Specified on a per module basic
They can be specified as a single delay on the output gate of
the module
The cumulative delay of all paths is lumped at one location
a
b
e
#11
out
and
a1(e, a, b);
and
a2(f, c, d);
and #11 a3(out, e, f);
endmodule
Huai-Yi Hsu
pp. 62

Pin-to-Pin Delay
Delays are assigned individually to paths from each input to
each output.
Delays can be separately specified for each input/output
path.
a
b
Path a-e-out, delay = 9

Path b-e-out, delay =9
Path c-f-out, delay = 11
Path d-f-out, delay = 11
out
c
Huai-Yi Hsu
pp. 63
Path Delay Modeling

Specify blocks
Assign pin-to-pin timing delay
across module path
Set up timing checks in the
circuits
Define specparam constanys
// specify block with path delay statements

specify
(a => out) = 9;
(b => out) = 9;
(c => out) = 11;
(d => out) = 11;
endspecify
// gate instantiations
and
a1(e, a, b);
and
a2(f, c, d);
and
a3(out, e, f);
endmodule
Huai-Yi Hsu
pp. 64
Parallel/Full Connection
(a[0] => out[0]) = 9;

(a[1] => out[1]) = 9;
(a[2] => out[2]) = 9;
(a[3] => out[3]) = 9;
(a => out) = 9;
(b => out) = 9;
(c => out) = 11;
(d => out) = 11;
(a => out) = 9;
(a,b *> out) = 9;

(c,d *> out) = 11;
Huai-Yi Hsu
pp. 65
Specparam Statement
Special parameters can be declared for use inside a
specify block.
Instead of using hardcoded delay numbers to specify
pin-tp-pin delays
// specify block with path delay statements

specify
specparam delay1 = 9;
specparam delay2 = 11;
(a,b *> out) = delay1;
(c,d *> out) = delay2;
endspecify
endmodule
Huai-Yi Hsu
pp. 66
Rise, Fall, and Turn-off Delays

Pin-to-pin timing can also be expressed in more
detail by specifying rise, fall, and turn-off delay values
// specify six delay statements
specparam t_01= 9, t_10 = 13;
specparam t_0z = 11, t_z1 = 9;
(clk => q) = (t_01, t_10, t_0z, t_z1, t_1z, t_z0);
// specify one delay statements

specparam t_delay = 9;
(clk => q) = t_delay;
// specify two delay statements
specparam t_rise = 9;
specparam t_fall = 13;
(clk => q) = (t_rise, t_fall);
// specify three delay statements
specparam t_rise = 9;
specparam t_fall = 13;
specparam t_turnoff = 11;
(clk => q) = (t_rise, t_fall, t_turnoff);
// specify twelve delay statements

specparam t_01= 9, t_10 = 13;
specparam t_0x= 9, t_x1 = 13;
specparam t_1x = 11, t_x0 = 9;
specparam t_xz = 11, t_zx = 13;
(clk => q) = (t_01, t_10, t_0z, t_z1, t_1z, t_z0,
t_0x, t_x1, t_1x, t_x0, t_xz, t_zx);
Huai-Yi Hsu
pp. 67
Min, Max, and Typical Delays

Min, max, and typical delay value were discussed
earlier for gates
Can also be specified for pin-to-pin delays.
// specify two delay statements

specparam t_rise = 8:9:10;
specparam t_fall = 12:13:14;
specparam t_turnoff = 10:11:12
(clk => q) = (t_rise, t_fall, t_turnoff);
Huai-Yi Hsu
pp. 68
Timing Checks
setup and hold checks
clock
data
setup
time
hold
time
specify
$setup(data, posedge clock, 3);
endspecify
specify
$hold(posedge clock, data, 5);
endspecify
Huai-Yi Hsu
pp. 69
Timing Checks
Width check
clock
width of
the pulse
specify
$width(posedge clock, 6);
endspecify
Huai-Yi Hsu
pp. 70
Structural Models
Verilog primitives encapsulate pre-defined functionality of common logic gates
The counterpart of a schematic is a structural model composed of Verilog
primitives
Model structural detail by instantiating and connecting primitives
module name
primary
inputs
primary
output
AOI_str
x_in1
y1
x_in2
x_in3
x_in4
x_in5
module ports
y_out
y2
module AOI_str (y_out, x_in1, x_in2, x_in3, x_in4, x_in5);

output y_out;
port modes
input x_in1, x_in2, x_in3, x_in4, x_in5;
internal wires
establish
wire y1, y2;
connectivity
nor
(y_out, y1, y2);
instantiated
and
(y1, x_in1, x_in2);
primitives
and
(y2, x_in3, x_in4, x_in5);
endmodule
Huai-Yi Hsu
pp. 71
Structural Connectivity
Wires in Verilog establish connectivity between primitives and/or
modules
Data type: nets (Example: wire)
The logic value of a wire (net) is determined dynamically during
simulation by what is connected to the wire.
An undeclared identifier is treated by default as a wire
Use nets to establish structural connectivity
Port connection by name
Add_half_0_delay M1(.b(b),.c_out(w2),.a(a),.sum(w1));
Port connection by place

Add_half_0_delay M1(w1, w2, a, b);
Huai-Yi Hsu
pp. 72
Simulation & Verification
ACCESS IC LAB
Test Methodology
Task: systematically verify the functionality of a model.
Approaches: Simulation and/or formal verification
Simulation:
(1) detect syntax violations in source code
(2) simulate behavior
(3) monitor results
Design_Unit_Test_Bench (DUTB)
Stimulus
Generator
Unit_Under_Test (UUT)
D
SET
CLR
Response
Monitor
Huai-Yi Hsu
pp. 74
Components of a Simulation
Stimulus Block
Dummy Top Block

Input
Patterns
Input
Patterns
Design Block
Stimulus
Block
Output
Results
Output
Results
Design
Block
Huai-Yi Hsu
pp. 75
Event-Driven Simulation
A change in the value of a signal (variable) during simulation is
referred to as an event
Spice-like analog simulation is impractical for VLSI circuits
Event-driven simulators update logic values only when signals
change
Huai-Yi Hsu
pp. 76
Inertial Delay
Not scheduled
x_in1
Descheduled
=1
3
tpd = 2
tsim = 4
x_in2
=6
3
y_out1
x_in1
tpd = 2
x_in2
y_out2
5
11
Note: The falling edge of x_in1 occurs before the response to the rising edge occurs.
Huai-Yi Hsu
pp. 77
Testbench Template
Consider the following template as a guide for simple testbenches:
module t_DUTB_name (); // substitute the name of the UUT
reg ;
// Declaration of register variables for primary inputs of the UUT
wire ;
// Declaration of primary outputs of the UUT
parameter
time_out = // Provide a value
UUT_name M1_instance_name ( UUT ports go here);
initial $monitor ( );
// Specification of signals to be monitored and displayed as text
initial #time_out $stop;
// (Also $finish) Stopwatch to assure termination of simulation
initial
// Develop one or more behaviors for pattern generation and/or

// error detection
begin
// Behavioral statements generating waveforms
// to the input ports, and comments documenting
// the test. Use the full repertoire of behavioral
// constructs for loops and conditionals.
end
endmodule
Huai-Yi Hsu
pp. 78
Example: Testbench
module t_Add_half();
wire
sum, c_out;
reg
a, b;
// Storage containers for stimulus waveforms
Add_half_0_delay M1 (sum, c_out, a, b);
initial begin
#100 $finish;
end
initial begin
#10 a = 0; b = 0;
#10 b = 1;
#10 a = 1;
#10 b = 0;
end
endmodule
//UUT
// Time Out
// Stopwatch
// Stimulus patterns
// Statements execute in sequence
Huai-Yi Hsu
pp. 79
Behaviors for Abstract Models

Verilog has three types of behaviors for composing abstract models of
functionality
Continuous assignment (Keyword: assign) -- later
Single pass behavior (Keyword: initial) -- Note: only use in testbenches
Cyclic behavior (Keyword: always) -- later
Single pass and cyclic behaviors execute procedural statements like a

programming language
The procedural statements execute sequentially
A single pass behavior expires after the last statement executes
A cyclic behavior begins executing again after the last statement
executes
Huai-Yi Hsu
pp. 80
Signal Generators
Use cyclic behaviors to describe stimulus generators

Statements in a behavior may be grouped in begin end blocks
Execution begins at tsim = 0
# delay control operator temporarily suspends execution of a behavior
The operator = denotes procedural assignment (also called blocking
assignment)
MODELING TIP
Use procedural assignments to describe stimulus patterns in
a testbench.
Huai-Yi Hsu
pp. 81
Simulation Results
MODELING TIP
A Verilog simulator assigns an initial value of x to all
variables.
Huai-Yi Hsu
pp. 82
Propagation Delay
Gate propagation delay specifies the time between an input
change and the resulting output change
Transport delay describes the time-of-flight of a signal transition
Verilog uses an inertial delay model for gates and transport
delay for nets
Inertial delay suppresses short pulses (width less than the
propdelay value)
MODELING TIP
All primitives and nets have a default propagation delay of 0.
Huai-Yi Hsu
pp. 83
Example: Propagation Delay

Unit-delay simulation reveals the chain of events
module Add_full (sum, c_out, a, b, c_in);
output
sum, c_out;
input
a, b, c_in;
wire
w1, w2, w3;
Add_half
Add_half
or
endmodule
#1
M1 (w1, w2, a, b);

M2 (sum, w3, w1, c_in);
M3 (c_out, w2, w3);
module Add_half (sum, c_out, a, b);

output
sum, c_out;
input
a, b;
xor
and
endmodule
#1 M1 (sum, a, b); // single delay value format

#1 M2 (c_out, a, b); // others are possible
Huai-Yi Hsu
pp. 84
Simulation with delay
Huai-Yi Hsu
pp. 85
Simulation with Standard Cells

`timescale 1ns / 1 ps // time scale directive for units and resolution
module Add_full_ASIC (sum, c_out, a, b, c_in);
output sum, c_out;
input a, b, c_in;
wire w1, w2, w3;
wire c_out_bar;
Add_half_ASIC M1 (w1, w2, a, b);
Add_half_ASIC M2 (sum, w3, w1, c_in);
norf201 M3 (c_out_bar, w2, w3);
invf101 M4 (c_out, c_out_bar);
endmodule
module Add_half_ASIC (sum, c_out, a, b);
output sum, c_out;
input a, b;
wire c_out_bar;
xorf201 M1 (sum, a, b);
// Standard cells - down load from web page
nanf201 M2 (c_out_bar, a, b);
invf101 M3 (c_out, c_out_bar);
endmodule
Huai-Yi Hsu
pp. 86
System Tasks
Displaying information
$display(ID of the port is %b, port_id);
ID of the port is 00101
Monitoring information
$monitor($time, Value of signals clk = %b rst = %b, clk, rst);
0 Value of signals clk = 0 rst = 1
Stopping and finishing in a simulation

$stop;
$finish;
// provided to stop during a simulation

// terminates the simulator
Huai-Yi Hsu
pp. 87
Compiler Directives
The `define directive is used to define text macros
`define WORD_SIZE 32
`define STOP $stop;
`define WORD_REG reg[31:0]
// Used as `WORD_SIZE in the code

// define an alias
// define a 32-bit register
The ìnclude directive allows you to include entire

contents of a Verilog source file
ìnclude header.v
ìnclude submodule.v
`timescale <reference_time_unit>/<time_precision>
`timescale 1 ns / 10 ps
`timescale 100 ns / 1ns
Huai-Yi Hsu
pp. 88
Summary
Understand switch level modeling
Understand gate level modeling
Specify timing delay
Function simulation
Timing simulation
Huai-Yi Hsu
pp. 89
Homework #1
Try to build your design by using gate-level
Check your syntax!! And record your miss errors!!
Writing your testbench to verify your design
Simulate and Verify your design
Optional:
Simulation with delay information on gate-level
Design example:
16-bits Adder, 4-bits multiplier (booth)
Counter, Clock generator (OSC)
Huai-Yi Hsu
pp. 90

Basic Concept of HDL

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Graduate Institute of Electronics Engineering, NTU