Instituto Tecnolgico de San Juan del Ro

DISEO DE TRANSISTORES
VEGA MANCILLA SOFIA
RESUMEN DE RUIDO DE BAJA FRECUENCIA

P RE S E N T A:

RAMREZ VZQUEZ CARLOS EDUARDO

ING. ELECTRNICA

1. Introduction
The presence of a gate that covers more than one side of the channel region
improves the electrostatic coupling between gate and channel, making multi-gate

devices less susceptible to the occurrence of short-channel effects (SCEs). The

formation of pn ultra-sharp junctions between source/drain and channel, however,
consists in an important issue for the fabrication process of inversion mode (IM)
multi-gate transistors, such as trigates, of extremely reduced dimensions, since the
thermal and doping conditions must be precisely controlled to avoid the
source/drain dopants diffusion into the channel region.
A novel device so-called Junctionless Nanowire Transistor (JNT) presents a
constant and heavy doping concentration (10 19 cm-3) from source to drain,
intrinsically eliminating diffusion-related problems.
The Low-Frequency Noise (LFN) is an important parameter which not only can limit
the output signal of an analog system, but also allows for the investigation of gate
dielectric integrity.
The LFN exhibited by n-type JNTs can be up to five orders of magnitude lower than
IM transistors of similar dimensions and can be partially explained by the smaller
current presented by such devices with respect to inversion mode ones. The noise
studies performed in present some discrepancies on LFN origin and its
dependence on the frequency (f). Show that the noise of n-type JNTs can exhibit
either 1/f or 1/f2 behavior depending on the samples and on the gate and drain
biases whereas in only a surprisingly weak 1/f is observed independently on biases
and samples.
2. Devices characteristics
Devices with different channel
lengths (50 and 100 nm) and
doping concentrations (0.5 and
1x1019 cm-3) were evaluated. The
gate stack is composed by
SiO2/HfSiON followed by TiN and
polysilicon, which results in an
effective oxide thickness of 1.5
nm. The application of a midgap
material with workfunction around
4.7 eV in the gate allowed for the
adjustment of the threshold
voltage (VTH) to suitable values.
The longer devices with doping
concentration of 5x1018 cm-3 have
presented |VTH| around 0.45 V
whereas the short channel ones
present |VTH| 0.35 V.
3. Low-frequency noise analysis

The high ion implantation dose required to attain the desired doping concentration
in the channel of JNTs can increase the defects in the silicon layer degrading the
LFN.
The curves of the current noise spectral density (S Id) as a function of the frequency
of both n- and p-type junctionless nanowires have been extracted and are
presented in Fig. 2 for transistors with L = 100 nm and doping concentration of
5x1018 cm-3 biased at drain voltage (VDS) of 0.1 V for gate biases from below
threshold up to gate voltage overdrives (|V GT| = |VGS VTH|) of 0.6 V, with steps of
100 mV. It can be seen that, mainly at higher V GT, p-type devices present lower
LNF than n-type ones, which is related to their reduced drain current (I DS) at a
similar |VGT|, resultant from the lower mobility presented by holes.
As stated in, devices fabricated with SiO 2 gate dielectric present lower overall noise
being more susceptible to Lorentzians. The shape of the current noise spectral
density is not significantly impacted when varying L or NA,D.
When evaluating the overall noise as a function of |V GT|, it can be noted that any
increase in |VGT| seems to raise SId up to |VGT| = 0.2 V. For higher gate overdrive
voltages, saturation on the overall noise is observed for both devices and is related
to the formation of a superficial accumulation layer when the transistors reach the
flatband limiting the trapping/release of carriers. The flatband voltage of the n-type
devices takes place around
VGS = 0.65 V (VGT around 0.30 V).
The transistors, indicating the prevalence of CNF as the main noise source, which
can be related to the trapping/release of charges in the gate dielectric. For p-type
transistors, however, different trends are observed along almost the whole |I DS|
range, revealing a strong influence of the mobility fluctuation component on the
LFN.
The effect of the doping concentration variation and the L reduction on the noise is
evaluated in terms of SId/IDS2 as a function of |gm/IDS|. In an inversion mode
transistor, |gm/IDS| indicates the inversion level of the interface from subthreshold
up to strong inversion. In JNTs, the meaning of |g m/IDS| can be interpreted
analogously. N-type transistors seem to present lower S Id/IDS2 than p-type ones
independently on L or NA,D for practically the entire |g m/IDS| range, which is
associated to the different |gm/IDS| required by p- and n-type devices to reach the
accumulation. The absolute variation of |gm/I DS| from depletion to accumulation is
much lower in p-type than in n-type JNTs as shown in Fig. 5(C), which shows the
correlation between gm/IDS and |VGT| for measured devices.

Finally, it is shown that p-type JNTs present higher SC*eff than n-type ones.
Indeed, the discrepancy between SC of p-type and n-type devices is supposed to
be even larger than indicated in Table 1 since the effective mobility of holes in ptype devices is expected to be lower than the one of electrons in n-type transistors.
However, the SC*eff factor extracted for p-type transistors can be overestimated
since screening effect has been neglected.
4. Trap density
The effective trap density (N T) for p- and n-type JNTs could also be determined as
well as its effective depth in the gate dielectric as described in. The effective trap
density has been obtained through the application of Eq.

where q is the electron elementary charge, k is the Boltzmann constant, T is the

absolute temperature, which has been considered equal to 300 K and is the
tunnelling parameter, equal to 10-8 cm for SiSiO2.

According to, the spectral noise density delivers important information about the
depth dependence of the effective trap. If it is considered that the charge exchange
between trap and channel is purely elastic, the effective trap depth (x) can be
calculated through the frequency as shown in Eq.

where min is the minimum trap time constant, which is assumed to be equal to 10 -10
s at x=0, i.e. at the interface between silicon and gate dielectric.

In Fig. 6(B), it can be observed that heavier doped devices present trap density
practically constant along the depth, whereas N T has a peak value for depths
around 1.4 nm for both p- and n-types devices with lower doping level. The overall
effective trap density obtained in JNTs does not consist in a technological
bottleneck since it is similar to the one presented by other ultimate multigate
transistors as stated in [26,28], where it is shown that N T is in the order of 10181020
cm-3 for different technologies of double and triple gate FinFETs.