Course No.

EEE 304

Experiment No. 04

Name of the Experiment: Design of Decoder/ Encoder/ Multiplexer Circuit

Submitted byTashrif Billah

# 1006022
Section- A1
Group No. 04
Other Group Members: 1006018, 19, 20, and 23
Date of Performance: February 5, 2013
Date of Submission: February 26, 2013

Objectives:
(i) Implementation of simple decoding technique
(ii) Introduction of priority concept in encoding/decoding
(iii) Study different aspects of MUX(Data Selector)
Apparatus:
(i) OR gate (IC 7432, 1 piece)
(ii) AND gate (IC 7408, 2 piece)
(iii) NOT gate (IC 7404, 1 piece)
(iv) IC 74150 (16X1 MUX)(1 piece)
(v) IC 74153 (dual 4X1 MUX)(1 piece)
(vi) IC 74154 (4 line to 16 line decoder)(1 piece)
(vii) Wires, trainer board etc.
Introduction to decoder logic:
The basic function of a decoder circuit is to detect the presence of a specific combination of
bits(code) on its inputs and to indicate the presence of that code by a specified output level. In its
general form, a decoder has n input lines to handle n bits and 2^n output lines to indicate the
presence of one or more n-bit combinations.
Example:
Suppose we need to construct a decoder system which has A and B (i.e 2 bits) as its input and we
have to determine the presence of each combination of these inputs (2^2=4 combination)by
observing the output lines(one for each combination). The presence of AB=11 can be determined
by observing the output of an AND gate whose output is AB. Similarly logic equation for other 3
combinations can be found. Then , if we find out which output line is active ,we can determine
input. The complete circuit diagram is shown below:

Prelab 1: Develop the logic required to detect the binary code 10010 and produce an active
LOW output.

Exercise 1: Construct a decoder circuit which can detect the presence of 8 and 15 at the
input.

The number (8 or 15) that is present at the input in binary, is high at the output.

Exercise 2: Construct a 5 bit(i.e 5 line to 32 line)decoder circuit by cascading two 4

line to 16 line decoder(IC 74154).

Here, each decoder has two control inputs. For active operation both of them should be low. The
upper decoder is for lines 0-15, and the lower decoder is for lines 16-32. The lower decoder is
chosen by the state of MSB (10000 - 11111). A NOT gate performs this function. When MSB is
equal to 1, the lower decoder is activated while the upper one is inactive.
For example, when the input is 10110 (decimal 22), the decoder output is 22nd pin which is low
and the rest are high.

The priority encoder circuit:

An encoder essentially performs a reverse decoder function. It accepts an active level on one
of its inputs representing a digit, such as a decimal or octal digit, and converts it to a coded
output, such as BCD or binary.
Example: The decimal to binary encoder
This type of encoder has ten inputs-one for each decimal digit-and four outputs corresponding to
the BCD code. The BCD code is listed in the following table:

Note that A0 output should be high when any of 1,3,5,7,9 input lines is present at the input.
Hence the expression for A0 will be:
A0 = 1+3+5+7+9
Similarly, A1=2+3+6+7
A2=4+5+6+7
A3= 8+9
The input lines do not always exhibits same priority. There may be cases where some inputs
have higher priorities than others. In such cases, when two input lines are active simultaneously,
the output choose to respond to the input line with highest priority. The encoder described above
can be modified to function as a priority encoder.
In that case, the encoder will produce BCD output corresponding to the highest order decimal
digit input that is active and will ignore any other active inputs. For example, if the 6 and 3
inputs are both active, the BCD output is 0110 (which represents decimal 6).
Now lets look at the requirements for the priority detection logic. This logic circuitry prevents a
lower order digit input from disrupting the encoding of a higher order digit. We want to examine
the output A0. Note that A0 is HIGH when 1,3,5,7 or 9 is high. Note that Digit 1 should activate
the A0 output only if no higher order digits other than those that also activate A0 are HIGH. The
requirements can be stated as follows:
1.A0 is HIGH if 1 is HIGH and 2,4,6 and 8 are LOW
2.A0 is HIGH if 3 is HIGH and 4,6 and 8 are LOW
3.A0 is HIGH if 5 is HIGH and 6 and 8 are LOW
4.A0 is HIGH if 7 is HIGH and 8 are LOW
5.A0 is HIGH if 9 is HIGH
A0 output is HIGH if any of the above 5 conditions occur. Hence,

Similarly, A1= (2+3) 4 5 8 9

A2= (5+6+7) 8 9
A3= 8+9
Exercise 3: Construct a priority encoder which implement the encoding of 0,3,1,2 with
descending priority (0 has the highest priority and 2 has the lowest).
0
1
0
0
0

1
x
x
1
0

2
x
x
x
1

3
x
1
0
0

Figure: Truth Table for the Priority Encoder

A1
0
1
0
1

A0
0
1
1
0

Multiplexer or Data Selector:

Multiplexers are also known as data selector. The basic multiplexer has several data input lines
and a single output line. It also has data selector inputs, which permit digital data on any one of
the inputs to be routed to the output line.

Note from the table that when C is 1, output is connected to the input B and in that case the state
of input at A does not have any effect on the output Y. Similarly when C is 0, output is connected
to the input A.
Exercise 4: Implementation of the Multiplexing function using IC 74LS153

IC 74153: Dual 4-to-1 Multiplexer

This multiplexer has two enable pins for each of configurations. Those pins 1G and
2G have to be low for active operation. It has two control inputs A, and B which are
represented respectively by S0, and S1 in the truth table. The output is found
according to the truth table in pins 1Y, and 2Y.

Combinational logic implementation using MUX:

A useful application of the data selector is in the generation of combinational logic functions in
sum of products form. When used in this way, the device can replace discrete gates, can often
greatly reduce the number of ICs and can make the design changes much easier. A good example
is given below.

Exercise 5: Implementation of the following logic using IC 74150

F(A,B,C,D)=(1,3,5,7,9,11,13,15)

Here the data inputs 1,3,5,9,11,13, and 15 are kept low while the rest are kept high.
According to the control inputs A,B,C, and D the appropriate input is chosen and
shown in the output. In this design output is high for odd number of input lines.

Cascading of MUX to increase the number of input line:

We can cascade several MUX's to construct a single MUX with higher number of input lines. In
the following example we have constructed a 4 line to 1 line MUX using three 2 line to 1 line
MUX.

Exercise 6: Implement a 8 line to 1 line MUX using two 4 line to 1 line MUX (found in IC
74153) and an OR gate.