Department of Electronic Engineering

School of Electronics and Physical Sciences

University of Surrey
Laboratory experiments E1 and E2 will give you practical experience with using state-of-theart computer aided design (CAD) software. The first laboratory session E1 will be an
introduction to the Cadence CAD system and Hspice simulator with the design of an
complementary metal-on-silicon (CMOS) inverter and CMOS NAND gate with simulation of
both.
The second laboratory session E2 will take knowledge and experience gained during the E1
laboratory experiment developing them further to design a 1-bit dynamic shift register and
simulate it to demonstrate correct functionality.

Year 2 Laboratory Experiment E2

Full-Custom VLSI Design of a 1-bit Shift Register

Using the Cadence CAD system and Hspice Simulator
The aim of this 1-day laboratory experiment is to design and simulate a full-custom
Very Large Scale Integration (VLSI) 1-bit shift register for the 0.35
austriamicrosystems complementary metal-on-silicon (CMOS) process. You will use
the Cadence Computer Aided Design (CAD) software and Hspice Simulator to
accomplish this.

E2 Lab Session Objectives:

Design and simulation of a transmission gate (i.e. t-gate or pass gate)

Design and simulation of a 1-bit shift dynamic register

Preparation for Lab Session E2:

You should have already done laboratory experiment E1.
Before coming to the E2 laboratory session you should carry out the following
preparatory work:

Learn about the 1-bit dynamic shift register components inverter, pass gate
(Also call a transmission gate) and logic NAND gate and how the pMOS and
nMOS transistors are connected in each component.

Learn how each of these components connect to form the 1-bit dynamic shift
register.

Ensure you have a valid username and password on the departmental network.

As part of your preparation, your log book should contain a diagram of the pass
gate at transistor and the 1-bit Dynamic shift register schematic diagram fully
explaining how each component works.

Equipment:
A Linux computer in the departmental computer laboratories or a PC running Exceed.

Marking:
You will be marked on your progress, innovative flair, and the quality of your log
book.

On-Line Manual:
A detailed version of the lab manual can be found online at:
http: //ulearn.surrey.ac.uk

E2 Lab Session Summary:

Your first task will be to construct a transmission gate. The schematic and layout
are as follows:
CLKB

CLK

The main task will be to construct a 1-bit dynamic shift register. The schematic is
as follows:
CLK2
IN
OUT

CLK1

CLR

CLK2

You will need to assemble and properly connect your transmission gates, NAND gate,
and inverter to complete the layout portion. Successful completion will be based on
the final simulation results of your shift register in Hspice

The E1 & E2 lab experiments are developed by:

David Barnhart and Dr Tanya Vladimirova
VLSI Design and Embedded Systems Research Group
Surrey Space Centre
December 2006
Acknowledgements:

Alistair Young developed the 1st version of the labs as part of his final year project in
May 2004.
Thanks are due to Georgi Kuzmanov for help with the installation, troubleshooting
and maintenance of the CAD software