Embedded Systems Conference

India 2010

CONFERENCE CATALOG

NIMHANS Convention Centre, Bangalore, India

www.esc-india.com

Platinum Partner Gold & Lanyard Gold Partner Association Partner Produced By: Organised By:
Partner
 A new era, a new ESC

Welcome Letter

I
t gives me great pleasure to welcome you to the 4th Annual ESC India event. As you
are aware, this is the largest technical conference of the many successful conferences
of ESC India. Our research has shown that developers in India desire the same career-
enhancing content as developers in the rest of the world, so that’s exactly what we’re
going to give you.
We’ve combined a team of recognised experts from all parts of the globe to provide you
with the content and training you need to get your job done. This includes our all-star cast
of speakers such as Michael Barr, Robert Oshana, Clive Maxfield, Gary Stringham and Bob
Zeidman. Michael Barr will exclusively cover topics such as The Top 10 Firmware Flaws,
Keeping Bugs Out with Embedded C Coding Standards, Top 5 RTOS Myths Busted
and The Worst Embedded C/C++ Code. Robert Oshana will emphasise on Firmware
Testing Tips & Techniques, Designing Software for Multicore Systems, DSP in Resource
Constrained Systems, Optimisation for Performance, Memory & Power.
Clive Maxfield will extensively elaborate on Hardware Concepts for Firmware Developers and How to Choose
the Best FPGA for Your Application. Gary Stringham will provide you with an in-depth focus and knowledge
on Hardware-Firmware Interface Design and How to Write Reusable Device Drivers in C. Most importantly,
Bob Zeidman will cover critical and insightful areas such as A Crash Course in Verilog, The Universal Design
Methodology and Measuring Software Changes with CLOC Method.
We will also have some of India’s most renowned experts delivering exclusive technical classes such as ARM
Development with Open Source Tools, Making Windows Real-Time, Migrating from RTOS to Linux, Why Static
Analysis Tools Fail ( and How…), Synchronization in Distributed Systems, CANbus & CANopen for Automation,
Making Embedded Linux Deterministic, Using & Understanding Linux Semaphores, Remote Debugging of
Embedded Systems, Moving from Analog to Digital Power Supply and Power over Ethernet (PoE).
For three days, you will get educated on tracks such as:

• Datacom/Telecom • Programmable Logic

• Debugging Techniques and Tools • Project Management/Software Engineering
Practices
• Developing for ARM
• Real-Time Kernels/Real-Time Development
• Linux and Open-Source Software
• Security
• Multi-core, Multi-threading, and Virtualization
• System Integration and Test
• Multimedia and Signal Processing

Don’t forget to check with our sponsors and exhibitors at the exhibition as they’ll have their own team of experts
on hand to answer some of your product specific questions.
I hope you have a great experience.

Sajid Desai
Director
UBM India

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 speakers
Michael Barr
Michael Barr is an internationally recognized
expert on the design of embedded computer
systems. In that role, he has provided expert
witness testimony in federal court, appeared
on PBS’ American Business Review, and
been quoted in various newspapers. He is
also the author of three books and more
than fifty articles on related subjects. For
three and a half years Michael served as editor-in-chief of
Embedded Systems Programming magazine. In addition,
Michael is a member of the advisory board and a track chair
for the Embedded Systems Conference. Software he wrote
continues to power millions of products. Michael holds B.S.
and M.S. degrees in electrical engineering and has lectured in
the Department of Electrical and Computer Engineering at the
University of Maryland, from which he also earned an MBA.
Robert Oshana
Rob Oshana has over 25 years of
experience in the software industry,
primarily focused on embedded and
real-time systems for the defense
and semiconductor industries. He
has BSEE, MSEE, MSCS, and MBA
degrees and is a Senior Member of
IEEE. Rob is a member of the Advisory
Board for the Embedded Systems Group, where he is also
an international speaker. He has over 100 presentations and
publications in various technology fields and is a licensed
professional engineer in Texas. Rob is an adjunct professor
at Southern Methodist University where he teaches graduate
software engineering courses. He is a Distinguished Member
of Technical Staff and Director of Global Software R&D for
Networking and Multimedia at Freescale Semiconductor.
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Clive Maxfield
Clive “Max” Maxfield is a well-known author,
editor, and engineer. After receiving his
B.Sc. in Control Engineering in 1980 from
Sheffield Polytechnic (now Sheffield Hallam
University) in England, Max began his
career as a designer of central processing
units for mainframe computers. In those days of yore, Max
and the rest of the team were designing silicon chips using
pencil and paper, because they didn’t have access to any
computer-aided tools. Over the following years, Max designed
everything from chips to circuit boards; he gained expertise
in digital logic simulation and wrote simulation models of
everything from ASIC cell libraries to microprocessors; and he
meandered his way through most of the tools used to design
and verify chips, circuit boards, and electronic systems.
In addition to numerous technical articles and papers
appearing in magazines and at conferences around the
world, Max is also the author and co-author of a number
of books, including BEBOP TO THE BOOLEAN BOOGIE
(AN UNCONVENTIONAL GUIDE TO ELECTRONICS),
BEBOP BYTES BACK (AN UNCONVENTIONAL GUIDE
TO COMPUTERS), DESIGNUS MAXIMUS UNLEASHED
(BANNED IN ALABAMA), EDA: WHERE ELECTRONICS
BEGINS, THE DESIGN WARRIOR’S GUIDE TO FPGAS,
and HOW COMPUTERS DO MATH (which features the
pedagogical and phantasmagorical virtual DIY Calculator).
To cut a long story short, Max now finds himself President
of TechBites Inc. (www.Techbites.Com) – The Science and
Technology Collaborative Community. This new website offers
a unique mix of technical content and social networking.
It’s FREE to join. Members can publish their own technical
content; access world-class content; participate in group
discussions; and connect with peers and industry experts in a
multitude of vertical communities.
On the off-chance that you’re still not impressed, Max
was once referred to as an “industry notable” and a
“semiconductor design expert” by someone famous who
wasn’t prompted, coerced, or remunerated in any way!

speakers
Gary Stringham
Gary Stringham is an embedded systems
expert with a specialization in the hardware/
firmware interface. He is the founder of
Gary Stringham & Associates, LLC, (www.
garystringham.com.) With over 25 years
of industry experience, Gary focuses on
diagnosing and resolving difficult hardware/
firmware integration issues and produces solid solutions to
prevent future occurrences of those issues. He is a frequent
presenter of this subject matter and is the author of the
book, Hardware/Firmware Interface Design: Best Practices
for Improving Embedded Systems Development. Previous
to founding the company, Gary was a technical lead at HP
establishing standards in firmware and ASIC designs. His
efforts have saved HP more than $100 million in development
costs across several projects. He holds a BSEE from Brigham
Young University and an MSEE from Utah State University.
Gary holds 12 patents in the area of printer hardware and
firmware.
Kiran Penneru
Embedded Software Architect, Integra Micro Systems
Shivakumar Murugesh
Sr. Research Staff (Central Research Laboratory)
Bharat Electronics Limited
Srinivas Adyapak
Principal Consultant (Telecom Domain), Wipro Technologies
B. Thangaraju
Senior Consultant, Wipro Technologies
Amit Joshi
Senior Software Engineer,
Wipro Technologies
A new era, a new ESC
Bob Zeidman
Bob is the president and founder of
Software Analysis and Forensic Engineering
Corporation (www.SAFE-corp.biz), the
leading provider of software intellectual
property analysis tools. Bob is considered
a pioneer in the field of analyzing software
source code, having created the patented
CodeSuite® program for detecting software intellectual
property theft that is sold by SAFE Corp.
Bob Zeidman is also the president and founder of Zeidman
Consulting (www.ZeidmanConsulting.com), a premiere
contract research and development firm in Silicon Valley that
now focuses on consulting to law firms about intellectual
property disputes. Since 1983, Bob has designed computer
chips and circuit boards for RISC-based parallel processor
systems, laser printers, network switches and routers, and
other complex systems. His clients have included Apple
Computer, Cisco Systems, Cadence Design Systems, Intel,
and Texas Instruments. Bob has worked on and testified
in cases involving billions of dollars in disputed intellectual
property.
Bob is a prolific writer and instructor, giving seminars at
conferences around the world. Among his publications
are numerous articles on engineering and business as well
as three textbooks -- Designing with FPGAs and CPLDs,
Verilog Designer’s Library, and Introduction to Verilog. Bob
holds seven patents and earned two bachelor’s degrees, in
physics and electrical engineering, from Cornell University
and a master’s degree in electrical engineering from Stanford
University.
Sudhir Abhyankar
Manager Operations, Global Technology
Ramakrishna Desetti
Senior Technology Architect - Product Engineering Division
Infosys Technologies
Diyanesh Babu
R&D Engineeer, IBM India Systems & Technology
Kavitha ShanmugaSundaram
Head - Firmware Development, Premier Evolvics
Ramesh Kankanala
Senior Applications Engineer - High Performance
Microcontroller Division, Microchip Technology
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 Technical Program Day 1

Please note that the technical program, speakers,
sessions, dates and times are subjects to change. For
complete class abstracts, instructor bios and latest
updates, please visit www.esc-india.com
Wednesday, 21 July
9:45AM – 11:00AM
HARDWARE CONCEPTS FOR FIRMWARE DEVELOPERS
- Part 1
Speakers: Clive Maxfield
This full-day (5 hours of classroom time) course will be based
on my popular book *Bebop to the Boolean Boogie (An
Unconventional Guide to Electronics)*. Recently published in
its third edition, this book is required reading for a lot of non-
hardware-oriented folks in EDA and System Design companies
around the world. Intended for Computer Scientists and
Embedded Software developers, this course will provide an
intuitive understanding of the underlying hardware they interact
with via their device driver code. The course will cover analog
versus digital (including A/D and D/A conversion); real-world
sensors (optical encoders, accelerometers, pressure sensors,
etc.); different types of numerical representations (sign-
magnitude versus signed binary, fixed-versus floating point, and
the use of Binary Coded Decimal (BCD) for certain applications);
microprocessors versus microcontrollers; what do we mean
by ASIC, ASSP, SoC, FPGA (can you have an ASIC that is
also an SoC)?; programmable logic (PLDs, CPLDs, FPGAs,
etc.); memory ICs (Flash vs. EEPROM; SRAM vs DRAM; the
underlying concepts of DDR, DDR2, DDR3; potential future
memory technologies like phase-change devices). Printed
circuit board technologies (multi-layer boards; lead-through-
hole vs. surface mount technology; high-density interconnect
and micro-via technologies) ... and so forth. There will also a
brief discussion as to the tools and flows used by hardware
designers. We will also save time (say 20 to 30 minutes) to
answer any specific questions from the attendees. The idea
of the course is not to delve down into the fiddly-details of
hardware and hardware design; instead, it’s to familiarize
the software folks with the concepts and terms used by the
hardware guys so as to facilitate communication between the
two domains.
Key Takeaways: This full-day (5 hours of classroom time) course
will give firmware developers an intuitive understanding of the
underlying hardware they interact with via their device driver
code.
A CRASH COURSE IN VERILOG - PART 1
Speaker: Bob Zeidman
Hardware description languages (HDLs) use statements
like programming language statements to define, simulate,
synthesize and lay out hardware. Verilog, a widely used and
standardized HDL, can be used to design anything from the
simplest PAL to a sophisticated ASIC. As ASICs and FPGAs
become more complex, HDLs are necessary for their design.
This course teaches how to use Verilog to design and simulate
hardware. It begins by explaining the benefits of HDLs over
other design entry methods, including its ability to model
different levels of abstraction, its reusability, and documentability.
Next, the syntax of the Verilog language is explained in detail.
Key Takeaways: By the end of the course, the student will
be able to design a complex chip using the Verilog hardware
description language.
ARM DEVELOPMENT WITH OPEN SOURCE TOOLS
Speaker: Kiran Penneru
When anyone starts the embedded product development,
one of the costs involved is the purchase of expensive tools.
Open source tools can be of help at this stage. However, there
is a general reluctance to use the open source tools since
it needs certain amount of effort and study to get the right
tools and set it up. This paper tries to remove that reluctance
and demostrates how the open source tools can be used for
professional ARM 7 embedded product development. For ease
of application development, an OS is needed. For this purpose,
porting of FreeRTOS, an open source embedded Real Time
Operating System is also discussed.
Key Takeaways: Attendee knows setting up the Development
Environment for ARM7 Microcontrollers which inculdes IDE,
compiler and Flash programming. He learns debugging and
developing applications on ARM7 using open source platform.
11:15AM – 12:30PM
HARDWARE CONCEPTS FOR FIRMWARE DEVELOPERS
- PART 2
Speakers: Clive Maxfield
Key Takeaways: This full-day (5 hours of classroom time) course
will give firmware developers an intuitive understanding of the
underlying hardware they interact with via their device driver
code.

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 A new era, a new ESC

Technical Program Day 1

A CRASH COURSE IN VERILOG - PART 2 4:35PM – 5:50PM

Speaker: Bob Zeidman HARDWARE CONCEPTS FOR FIRMWARE DEVELOPERS
- PART 4
Key Takeaways: By the end of the course, the student will
be able to design a complex chip using the Verilog hardware Speakers: Clive Maxfield
description language.
Key Takeaways: This full-day (5 hours of classroom time) course
will give firmware developers an intuitive understanding of the
underlying hardware they interact with via their device driver
2:00PM – 3:15PM
code.
HARDWARE CONCEPTS FOR FIRMWARE DEVELOPERS
- PART 3
THE UNIVERSAL DESIGN METHODOLOGY FOR CLPDs AND
Speakers: Clive Maxfield
FPGAs - PART 2
Key Takeaways: This full-day (5 hours of classroom time) course
Speaker: Bob Zeidman
will give firmware developers an intuitive understanding of the
underlying hardware they interact with via their device driver Key Takeaways: By the end of the course, the student will
code. understand the technologies and architectures of various
programmable devices and will be able to design them into their
systems.
THE UNIVERSAL DESIGN METHODOLOGY FOR CLPDs AND
FPGAs - PART 1
HOW TO WRITE REUSABLE DEVICE DRIVERS IN C
Speaker: Bob Zeidman
Speaker: Gary Stringham
This course examines various CPLD and FPGA programmable
devices and their underlying architectures and technologies. The Too many believe that device drivers are throw-away code,
course teaches superior design techniques that will improve the that every spin of the ASIC or reprogramming of the FPGA
timing, optimize the gate utilization, and increase the reliability of requires an extensive overhaul or complete rewrite of the device
your programmable device design. driver. However, device drivers can be written to be reused
effectively with different chips across a variety of models within
Key Takeaways: By the end of the course, the student will
an embedded product line. Successful driver reuse avoids
understand the technologies and architectures of various
diverging code branches, propagated defects, and extensive
programmable devices and will be able to design them into their
porting efforts. This class uses an embedded product case
systems.
study to teach how to support changes in bit and register
mappings, use compile-time and run-time switching, work
around chip defects, handle frequent changes to FPGAs, and
TOP 5 RTOS MYTHS BUSTED
request hardware changes to maximize driver reusability.
Speaker: Michael Barr
Key Takeaways: Firmware engineers will learn techniques and
Real-time operating systems are widely misused. Too often this tools on how to write reusable device drivers that will support
is because engineers lack trustworthy information about how to multiple generations and families of ASICs, FPGAs, ASSPs, and
use them properly. Some RTOS user manuals perpetuate bad other chips in multiple products.
habits, simply because they are written by RTOS developers
rather than experienced RTOS users. Come learn five tips for
using an RTOS well, from an RTOS user and expert.
Key Takeaways: A better understanding of the proper use of a
real-time operating system.

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 Technical Program Day 2
Thursday, 22 July
9:45AM – 11:00AM
DESIGNING SOFTWARE FOR MULTICORE SYSTEMS
Speakers: Robert Oshana
Multicore computing is becoming more ubiquitous in the
embedded space. Developing an embedded multicore application
is a large undertaking involving a complex software stack and
performance engineering in order to support a variety of customer
programming models. In this course we will overview multicore
terminology, discuss the advantages and diadvantages of
multicore, as well as some of the multicore programming models
such as SMP, AMP, and blending. We’ll look at the software
impact of multicore processing including issues associated with
partitioning, communication, agglomeration, and mapping. We
will study a couple industry examples to show how applications
have been partitioned on a multicore device. We will also take a
look at some embedded multicore processors and embedded
applications using multicore. We will also discuss debugging and
benchmarking of multicore applications and how to determine if
we are meeting our performance goals of the system.
Key Takeaways: Student will learn about the key development
challenges for multicore systems, the common software
architectures for embedded multicore devices, and techniques to
map and partition software applications onto multicore devices.
Migration from Proprietary RTOS to Carrier Grade
Linux in Telecom Equipments
Speaker: Srinivas Adyapak
The adoption of Linux as an embedded operating system is
widespread and expanding, particularly in telecommunications
equipment. Open source is considered less risky and more
accommodative of future protocol changes than the commercial
RTOS. Switching to Linux can be a cost effective way to
develop products. This presentation explores the different target
application devices where there is a significant movement to
Linux in both the control and management planes, helping
equipment vendors and service providers alike to address
growing needs of the subscribers.
Key Takeaways: An appreciation of the technical challenges in
moving from a commercial RTOS to open source Linux.
BEST PRACTICES FOR HARDWARE-FIRMWARE INTERFACE
DESIGN - PART 1
Speaker: Gary Stringham
Too often, design problems in the interface between hardware and
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firmware delay schedules, increase costs, impact quality. Turmoil
in FPGA designs causes difficult integration efforts with device
drivers. Errors in ASICs, ASSPs, and SoCs force respins. Many
of these problems can be eliminated or mitigated through proper
application of principles and best practices designed to streamline
the interface and provide diagnostic resources. In this class, both
hardware and firmware engineers will learn overarching principles
guiding hardware/firmware interface design. They will also learn
detailed best practices in areas such as register layout, interrupts,
documentation, and testing and debugging. Attendees will be
given an electronic copy of the best practices.
Key Takeaways: Hardware and firmware engineers will learn
principles and best practices of immediate value and applicability
to their own design processes, which could decrease the
development time and cost while improving the quality.
11:15AM – 12:30PM
DIGITAL SIGNAL PROCESSING IN RESOURCE
CONSTRAINED SYSTEMS
Speakers: Robert Oshana
Many of today’s DSP applications are subject to real-time
constraints. This presentation discusses the techniques used
in practice to optimize DSP applications for performance,
memory, and power. Topics include use of standard optimization
techniques such as loop unrolling, software pipelining and
vectorization, the use of intrinsics and pragmas, the application of
algorithmic transformation techniques such as partial summation
and multi-sampling techniques, a list of top 10 power optimization
techniques for software developers, other system related
techniques related to cache optimization and power optimization.
Key Takeaways: In this presentation, the attendee will take away
a number of practical techniques for specifying, developing, and
optimizing software for signal processing systems.
HOW TO MAKE EMBEDDED LINUX DETERMINISTIC
Speaker: B. Thangaraju
Today many necessary features of embedded systems are
available in open source to build embedded Linux Kernel but still
it is a big challenge to achieve real time response in embedded
Linux. This course demonstrates various ways to accomplish
deterministic behaviour in Linux-based systems by achieving
minimum interrupt latency, real time inter-process communication,
real time signal handling, efficient multithreaded programming,
and appropriate file systems in real time systems. Dual kernel
approach for real time environment will also be discussed.
Key Takeaways: How to achieve deterministic behaviour in Linux.

Technical Program Day 2
BEST PRACTICES FOR HARDWARE-FIRMWARE INTERFACE
DESIGN - PART 2
Speakers: Gary Stringham
Key Takeaways: Hardware and firmware engineers will
learn principles and best practices of immediate value and
applicability to their own design processes, which could
decrease the development time and cost while improving the
quality.
2:00PM – 3:15PM
OPTIMIZING SOFTWARE FOR PERFORMANCE, MEMORY
AND POWER - PART 1
Speaker: Robert Oshana
Many of today’s firmware applications are subject to real-time
constraints. This presentation discusses the techniques used
in practice to optimize firmware for performance, memory, and
power. Topics include use of standard optimization techniques
such as loop unrolling, software pipelining and vectorization,
the use of intrinsics and pragmas, the application of algorithmic
transformation techniques such as partial summation and
multi-sampling techniques, a list of top 10 power optimization
techniques for software developers, other system related
techniques related to cache optimization and power
optimization.
Key Takeaways: Student will learn processes and techniques for
optimizing embedded systems for performance, memory and
power.
REAL-TIME PROGRAMMING WITH WINDOWS
Speaker: Shivakumar Murugesh
Many applications require Windows as a component of the
solution, but also require real-time deterministic elements.
Windows OS being neither deterministic nor real-time, the
applications developed in Windows using Visual C++ are not
deterministic. There is no clear separation between the GUI
modules and Logical/Algorithmic modules. Applications that
require sub-millisecond response times, extreme accuracy,
predictable execution of control processes, require the absolute
determinism which is found in a real-time kernel. This course
presents an approach to separate the modules that need real-
time computation, from the modules that do not.
Key Takeaways: Explores multicore and virtualization
technologies, adding real-time executives to the windows,
Real-Time data acquisition, Instrumentation & Control, RT
scheduling.
A new era, a new ESC
BEST PRACTICES FOR HARDWARE-FIRMWARE INTERFACE
DESIGN - PART 3
Speaker: Gary Stringham
Key Takeaways: Hardware and firmware engineers will
learn principles and best practices of immediate value and
applicability to their own design processes, which could
decrease the development time and cost while improving the
quality.
4:35PM – 5:50PM
OPTIMIZING SOFTWARE FOR PERFORMANCE, MEMORY
AND POWER - PART 2
Speaker: Robert Oshana
Key Takeaways: Student will learn processes and techniques for
optimizing embedded systems for performance, memory and
power.
REMOTE DEBUGGING OF EMBEDDED SYSTEMS
Speaker: Himanshu Shrinkhal
Embedded software developers must frequently be able to
access target hardware setup anytime and anywhere for the
purpose of debugging, development and testing. The latest
advancements in mobile technology have erased physical
boundaries and enable engineers to communicate with the
development hardware system from across the globe. This
course shows programmers how to remotely load programs
into a target system, run them, step through them, and view
and change data used by the software under test.
Key Takeaways: How to use mobile technology to access test
setups and debug and development environments from remote
locations.
BEST PRACTICES FOR HARDWARE-FIRMWARE INTERFACE
DESIGN - PART 4
Speaker: Gary Stringham
Key Takeaways: Hardware and firmware engineers will
learn principles and best practices of immediate value and
applicability to their own design processes, which could
decrease the development time and cost while improving the
quality.
www.esc-india.com | page 
 Technical Program Day 3

Friday, 23 July cores, ultra-low-power FPGA fabrics, asynchronous FPGA

fabrics, mixed-signal FPGA fabrics, programmable analog fabrics,
9:45AM – 11:00AM
radiation-tolerant FPGA fabrics, and so forth. Also the differences
THE TOP 10 FIRMWARE FLAWS: HOW TO FIND, FIX, AND between devices like FPGAs, CSSPs, ECAs, etc. Other
PREVENT THE NASTIEST OF BUGS - PART 1 considerations include price, capacity, tool support, and the
ability to migrate a design from an FPGA to an ASIC if so-desired.
Speakers: Michael Barr
Key Takeaways: Attendees will be introduced to various types
Debugging embedded software is a challenging business. Many
of underlying FPGA fabrics along with their advantages and
symptoms, including crashes and hangs, come and go in ways
disadvantages for various classes of applications.
that can’t be reproduced. Some of the “glitches” observed in the
lab can’t be explained, but the product ships anyway. And no
amount of testing can prove the absence of hidden flaws. This
11:15 – 12:30PM
course introduces and fully explains ten of the most common
underlying causes of firmware glitches and probabilistic failures. THE TOP 10 FIRMWARE FLAWS: HOW TO FIND, FIX, AND
PREVENT THE NASTIEST OF BUGS - PART 2
Key Takeaways: How to find, fix, and prevent ten of the most
common causes of bugs in embedded software. Speakers: Michael Barr
Key Takeaways: How to find, fix, and prevent ten of the most
common causes of bugs in embedded software.
MEASURING SOFTWARE CHANGES WITH THE CLOC
METHOD
Speaker: Bob Zeidman FIRMWARE TESTING TIPS AND TECHNIQUES
What is your software worth? This question comes up during Speaker: Robert Oshana
project scheduling and budgeting, in litigation, and at tax time.
Embedded systems technology is among the most innovative
The important factors include the amount of development effort,
technology that has ever been created. Embedded technology
amount of debug time, code complexity, degree of expertise
has revolutionized sectors of the industry in ways that were
required, final selling price, and size of the market. Sometimes
previously never thought possible. For this reason, product
it can be useful to measure not the absolute value of software,
testing is becoming increasingly important. Ensuring that our
but the amount of change in the software. If your company
embedded technology works exactly as it should is a priority
pays to develop an initial version of a program, how much more
for most companies, regardless of where that technology
should it pay to develop the next version? If you hand your code
happens to be located. In this course we will explore white box
to an outsourced development team, how can you measure
and black box techniques for testing embedded systems, talk
the value of the code you got back? In this course we learn
about system and performance testing, and summarize some
the mathematics behind a new measurement method called
of the unique testing requirements and approaches for real-time
Changing Lines of Code or “CLOC” and how it can be applied.
embedded systems.
Key Takeaways: By the end of the course, students will
Key Takeaways: The attendee will learn techniques for testing
understand the CLOC method of measuring software changes.
embedded and real time system in a cost effective manner.
Students will also learn about tools available for measuring CLOC.

INTRODUCTION TO CONTROLLER AREA NETWORKING (CAN)

HOW TO CHOOSE THE BEST FPGA FOR YOUR APPLICATION
Speaker: Sudhir Abhyankar
Speaker: Clive Maxfield
Controller Area Networking (CAN) is an increasingly popular
In this course we will discuss a wide range of considerations
serial communications bus. This course will explain how
that may affect the FPGA selection process. This will include a
the CANopen protocols work and why CAN is an ideal bus
high-level view of the various underlying FPGA fabrics (Antifuse-
architecture for real-time communications in automotive and
based, FLASH-based, and SRAM based; also MUX-based vs.
industrial control applications. The discussion will include a look
LUT-based). Also the availability/use of hard IP block versus soft
at key device profiles.
IP implemented in programmable fabric (including hard and soft
uP/uC cores). Also discussed will be the various FPGA offerings Key Takeaways: How to use CAN to build real-time networks
from different vendors, including the availability of different uP/uC between processors.

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Technical Program Day 3
2:00PM – 3:15PM
THIS CODE STINKS! THE WORST EMBEDDED C/C++ CODE
EVER WRITTEN
Speakers: Michael Barr
Michael Barr is a firmware engineer. And he’s a collector of
bad code. Over the years he has aquired dozens of buggy and
poorly written bits of embedded software source code that was
used in real products. This course will teach you what NOT to
do when writing embedded software--by showing you source
code for some of the worst firmware ever written. Come join the
fun and see if you can spot the bugs before they are revealed.
Key Takeaways: An appreciation of the fact that real world
embedded systems contain many latent bugs and for what
those bugs look like in the source code.
WHY STATIC ANALYSIS TOOL DEPLOYMENTS FAIL (AND
HOW…)
Speaker: Ramakrishna Rao Desetti
To improve the quality of their software, embedded and
datacom system designers are increasingly deploying static
analysis tools. Unfortunately, it turns out that many of the
deployments are failures. Some have discontinued static
analysis tools altogether. Some continue to use them, but find
that the results are not as effective as they anticipated. What are
the causes of these failures? This course tries to answer that
question based on our own deployment of the tools, evaluation
of the tools, usage of these tools, consultancy to other
companies, and others’ experiences.
Key Takeaways: How to avoid common mistakes in choosing
and deploying static analysis tools.
MOVING FROM ANALOG TO DIGITAL POWER SUPPLIES
Speaker: Ramesh Kankanala
Digital Switch Mode Power Supplies are becoming an integral
part of many telecom, networking and server applications
because they meet the complex design requirements of these
applications and enable system miniaturization. Traditionally,
power supplies were designed using analog controllers,
whereas digital controllers have gained popularity in recent
years. Attend this course to learn six simple steps for creating a
successful digital power-supply design.
Key Takeaways: Attendees will learn about the advantages of
digital power control and how to implement it.
A new era, a new ESC
4:35PM – 5:50PM
KEEPING BUGS OUT OF EMBEDDED SOFTWARE WITH
CODING STANDARDS
Speaker: Michael Barr
There are many sources of bugs in software programs. Some
bugs are created by the original programmer. Other bugs result
from misunderstandings of the original code by those who
maintain, extend, and/or reuse (or port) that code at a later time.
The number of bugs introduced by the original programmer
can be reduced through the disciplined application of certain
coding practices. In addition, some types of bugs caused by
maintenance programmers can be prevented by the original
programmer through commenting and careful naming of variables
and functions. To keep bugs out of medical devices and other
safety-critical embedded systems, it is valuable to create a C
coding standard that considers these factors from the beginning.
This session describes such a standard in full detail.
Key Takeaways: Practical ideas for creating or improving a
firmware coding standard to keep bugs out of programs.
SYNCHRONIZATION IN DISTRIBUTED SYSTEMS
Speaker: Kavitha Shanmuga Sundaram
With the advent of microcontrollers getting more powerful at
a small footprint it is obvious that even sensors are becoming
intelligent. This paves way of distributed computing at
various nodes within a system and across systems. The
session focuses on the prevailing and possible varians of
synchronization methods and mechanisms of such distributed
systems networked serially, wired and wireless.
Key Takeaways: Ideas, working methods and mechanism to
synchronize distributed embedded systems.
INTRODUCTION TO POWER OVER ETHERNET (PoE)
Speaker: Diyanesh Babu
Any product attached to a wired network requires power for its
operation. The IEEE 802.3af and 802.3at standards for Power
Over Ethernet (POE) technology integrate data and power over
a traditional network infrastructure. Under this scheme, one
central node can serve as the DC power supply source for the
rest of the nodes using existing CAT5 cables. PoE provides
enormous opportunity to reduce the cost and improve the
reliability of networked embedded systems in medical, industrial
& networking applications.
Key Takeaways: How to convert power circuit designs to draw
Power Over Ethernet (POE).
www.esc-india.com | page 10
 registration packages

3 Easy Ways to Register Today!

For best conference rates, early registration is encouraged. No need to decide in advance, which sessions you would like to attend.
Admission to all sessions is on a first-come, first-served basis onsite.
1) Online: Register at www.esc-india.com
2) Fax: Submit your registration form to +91 – 22 – 6769 2426
(Download the PDF version of the registration form at www.esc-india.com)
3) Mail: Submit registration form to:
UBM India Pvt Ltd,
Sagar Tech Plaza A, 119,
1st Floor, Andheri Kurla Road,
Saki Naka Junction, Andheri East,
Mumbai – 400 072, India.

PACKAGES AND PRICING

1) All Access Conference Pass *Best Value*
• Access to ALL ESC classes and tutorials (Wednesday – Friday)
• access to the ESC Exhibits Floor (Wednesday – Friday)
• Daily Lunches (Wednesday – Friday)
• Class Notes and Conference Proceedings in digitized format
• Engineers Revival Kit
• Access to the Keynotes, Industry Addresses, and Sponsored Technical Sessions

Register by: 30 April 31 May 30 June Onsite

Price: Rs. 11,250 Rs. 13,000 Rs. 15,000 Rs. 18,000
Savings: Rs. 6,750 Rs. 5,000 Rs. 3,000
* Please add service tax as applicable

2) Two-Day Pass
• Access to ANY TWO days of ESC classes and tutorials (Wednesday or Friday registrant must make selection of days at point of
registration)
• Access to the ESC Exhibits Floor (Wednesday – Friday)
• Daily Lunches on days of attendance
• Class Notes and Conference Proceedings for the days attended in digitized format
• Engineers Revival Kit
• Access to the Keynotes, Industry Addresses, and Sponsored Technical Sessions

Register by: 30 April 31 May 30 June Onsite

Price: Rs. 7,000 Rs. 9,000 Rs. 11,000 Rs. 13,500
Savings: Rs. 6,500 Rs. 4,500 Rs. 2,500
* Please add service tax as applicable

page 11 | www.esc-india.com
 A new era, a new ESC

registration packages

3) One-Day Pass
• Access to any ONE day of ESC classes and tutorials (Wednesday - Friday; registrant must make selection of days at point of
registration)
• Access to the ESC Exhibits Floor (Wednesday – Friday)
• Lunch on day of attendance
• Class Notes and Conference Proceedings for the day attended in digitized format
• Engineers Revival Kit
• Access to the Keynotes, Industry Addresses, and Sponsored Technical Sessions

Register by: 30 April 31 May 30 June Onsite

Price: Rs. 6,750 Rs. 8,000 Rs. 9,000 Rs. 10,000
Savings: Rs. 3,250 Rs. 2,000 Rs. 1,000
* Please add service tax as applicable

4) ESC 1 - Class Pass

• Access to any ONE class/tutorial (Wednesday - Friday; registrant must make selection of Class at point of registration)
• Access to the ESC Exhibits Floor (Wednesday – Friday)
• Class Notes for the class attended in digitized format
• Access to the Keynotes, Industry Addresses, and Sponsored Technical Sessions

Register by: 30 April 31 May 30 June Onsite

Price: Rs. 3,500 Rs. 4,500 Rs. 5,000 Rs. 6,750
Savings: Rs. 3,250 Rs. 2,250 Rs. 1,750
* Please add service tax as applicable

5) Exhibit Pass (FREE)

• Access to the three-day Exhibit (July 21-23)
• Access to Keynotes, Industry Addresses, and Sponsored Technical Sessions

Group Registration Discount

Bring your whole team! The more people you bring, the more you save.
For more information call Syed Javed at +91 98674 40229, Monday-Friday, 10:00am – 6:00pm IST, or
email: syed.javed@ubm.com.
Groups of 4-10: Save 5% off current registration pricing
Groups of 11-15: Save 10% off current registration pricing
Groups of 16-19: Save 15% off current registration pricing
Groups of 20 or more: Save 20% off current registration pricing

For more information:

Syed Javed
Mobile: +91 98674 40229
Email: syed.javed@ubm.com
Monday-Friday
10:00am – 6:00pm IST

www.esc-india.com | page 12