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I.
INTRODUCTION
DFF
DFF
DFF
C1[i]
x[i]
First-order
Modulator
A1
DFF
C2[i]
-e1[i]
DFF
First-order
Modulator
A2
C3[i]
-e2[i]
First-order
Modulator
A3
-e3[i]
a1
1
3
5
9
15
19
a2
0
0
0
0
0
0
a3
3
1
1
1
1
1
X
-e[i]
X+Y
1bit
24bit
Reg
24bit
(a)
a=1
(b) a=3
Fig. 6 First-order modulator implementation circuit
101
-3
110
-2
111
-1
000
0
001
1
010
2
011
3
100
4
(a)
n=16777202240.099999900.1
(b)
n=83886052240.499999820.5
V. CONCLUSION
A fractional frequency divider in which a - modulator
named MASH-1-1-1 was proposed to be utilized is
implemented in SMIC 0.18-m CMOS technology based on
standard cells. Simulation results indicate that the frequency
divider achieves the expected precision. Its operating
frequency is from 20 MHz to 50 MHz. The precision of the
fractional division ratio can reach 1/224. Finally, the PLL
frequency synthesis for DAB is designed and works well
when the frequency divider is mixed with the other modules
designed with the full custom method.
ACKNOWLEDGMENT
The authors acknowledge the support of the Specialized
Research Fund for the Doctoral Program of Higher Education,
China (No. 20090092120012), and the Science and
Technology Program of Southeast University (No. KJ2010402)
and the suggestions by the DAB project group.
Fig.8 The relationship between the number of clock cycles and the cumulative
value (K= 6021342)
REFERENCES
[1]