Physical Design Flow

Mohammad reza Kakoee

micrellab
m.kakoee@unibo.it
@

Agenda
Introduction to design flow and Backend
Introduction to design planning
Floorplanning / Hierarchical design
Power
P
planning
l
i
Summary

Agenda
Introduction to design flow and Backend
Introduction to design planning
Floorplanning / Hierarchical design
Power
P
planning
l
i
Summary

The Physical Design Task

Verilog netlist

Physical Design
Flow
GDSII

SDC constraints

Front End

Back End

Example Physical Design Flow

Design/Constraints Import
Floorplanning
p
g
Placement
Cl k T
Clock
Tree S
Synthesis
th i
Routing
Post Route Optimization
Layout Verification / Finishing

Fullchip Design Overview

Core placement
area
The location of the core,
I/O areas P/G pads and
the P/G grid

P/G
Grid

Rings
Straps

Periphery
(I/O) area

RAM
IP
ROM

Where Do We Start? - Design

Planning
Physical Design
Flow

Verilog netlist

SDC constraints

How do we handle?
Die

size
IO / Hard-IP placement
Global clock distribution
Power
P
planning
l
i
Flat versus hierarchical design

Design Planning

Floorplanning
Determine die size
Shape and arrange hierarchical blocks
Integrate hard-IP efficiently
Predict and prevent congestion hotspots and critical timing
paths
Power planning
Create power distribution grid
Consider IR drop and Electromigration
Implement power saving techniques
Power gating
g
g
Multi-Voltage design / Voltage islands

Agenda
Introduction to design planning
Floorplanning
p
g

Setup/configuration
Die

size,
size utilization,
utilization metallization scheme
IO-ring and macro placement
Flat versus hierarchical design
Hierarchical design planning issues

Power planning
Summary

S t /
Setup/configuration
fi
ti

Read netlist
Read SDC
Read .lib files
Read footprint
p
for P&R
LEF : SOC encounter
Fram : Synopsys tools
Read technology file
Metal width (DRC
rules)

check netlist
High fanout
U i
Unique
Unconnected inputs
Standard cell area
Ch k titiming
Check
i without
ith t wire
i lload
d

Floorplanning Die Size

Size,
Utilization & Metal Stack-up

Choosing the die size, initial standard cell utilization and

metallization scheme involves several design tradeoffs (
Schedule, Cost, Performance)
Larger die
Easier to route, less congestion, lower cap (decrease
signal/power integrity related problems)
problems), faster design
cycle
Higher cost, higher power
More
M
d
dense power grid
id
Reduce risk of power related failures
Increase number of metal layer masks, reduce signal
route tracks

Floorplanning Utilization

Low standard-cell
utilization

High standard-cell
tili ti
utilization

Floorplanning Utilization

Utilization refers to the percentage of core area that is taken

up by standard cells.
A typical starting utilization might be 70%
This can very a lot depending on the design
High utilization can make it difficult to close a design
Routing congestion,
Negative impact during optimization legalization stages.
Utilization changes
g should be examined after each stage
g of
the flow
Avoid having large increases after placement optimization
Feedback should be given to front-end
front end designers
Topographical synthesis is now possible

Initialize Floorplan
Define globals (VDD1,VDD2,GND1,.)
Define
D fi core area : ((cells
ll + utilization
ili i ffactor))

[[Analog]
g] macro

IO

core

core

IO

Shape can be implied by a macro

Place IO (fixed, equidistant,..)

Take

macros and power domains into

account already

IO Ring and Large Macro

Placement

IO Ring is often decided by front-end designers, with input from

physical design and packaging engineers.
When placing large macros we must consider impacts on routing,
timing and power.
For wire-bond place power hungry macros away from the chip
Possible routing
center.

congestion hotspots

Flat Versus Hierarchical

Design

What happens if the design is too big to be

handled by
y the EDA tools?
Hierarchical

Design

Fullchip Design

I/O Pad
IP Macro

Blk 1
P&R
Flow

Blk 2
P&R
Flow

Blk 3
P&R
Flow

Fullchip Timing &

Verification

Block / Tile

Flat Versus Hierarchical

Design

Hierarchical Design
Advantages

Faster runtime, less memory needed for EDA tools

Faster eco turn-around time
Ability to do design re
re-use
use

Disadvantages

Much more difficult for fullchip timing closure

(ILMs)
More intensive design planning needed,
feedthrough generation
generation, repeater insertion
insertion, timing
constraint budgeting.

Hierarchical Design : Specify

Partitions / Plan Groups

Netlist must have partitions as top level modules.

Partitions generally sized according to a target initial utilization
~70% utilization, ~300k-700k instances

Channels
Ch
l or abutment
b t
t
Rectilinear block shapes are possible

Channels
Rectilinear
Blocks

Abutment

Hierarchical Design : Pin

Assignment

Pin constraints include parameters such as,

Layers, spacing, size, overlap
Net groups, pin guides
Pins can be assigned placement-based
placement based
(flightlines) or route-based (trial route,
boundary crossings).
Pin guides can be used to influence automatic
pin placement of particular net groups
Pins at partition
corners can make
routing
ti diffi
difficult
lt

Pin guide 1

Pin guide 2
Partition

Hierarchical Design : Timing

Budgeting

Chip level constraints must be mapped correctly to block

level constraints
Th design
The
d i mustt b
be placed,
l
d ttrial
i l routed
t d and
dh
have pins
i
assigned before running budgeting
Block level constraints will be assigned input or output
delays on I/O ports based off of the estimated timing
slack.
1.5ns

set input delay 1.5

set_input_delay
1 5 [ get_port
get port IN1 ]

IN1

Block Boundary

Hierarchical Design : Timing

Budgeting & Fullchip Timing Closure

Fullchip timing closure is typically a bottleneck for design cycles.

Block-level P&R flow does not emphasize io-to-flop, flop-to-io, io-to-io
timing paths
paths, because budgeted constraints are only estimates
Interface logic models (ILMs) can be used
To speed-up timing analysis runs when fullchip design is too large.
Required
q
clock and datapaths
p
are p
preserved,, net/cell names are
identical

Clk

Clk

Original Netlist

Interface Logic Model (ILM)

Agenda
Introduction to design planning
Floorplanning
Power planning

Intro

to power issues in IC design

Basic power grid creation
Multi-voltage
Multi voltage design & power gating
Automated power grid design flows

Summary

Power Consumption and Reliability

IR Drop /
IR-Drop
Voltage Drop

Dynamic Power
Average Power
problem
p
ob e

Static Power
(Leakage Power)

Floorplan
+
Design of the grid

Fail

Power density
problem in the
Long run

Electromigration
(EM)

1 out of 5 chips fail due to excessive power consumption

Power Consumption and Reliability :

IR-Drop

The drop in supply voltage over the length of the supply line
A resistance matrix of the power grid is constructed
The average
g current of each g
gate is considered
The matrix is solved for the current at each node, to determine
the IR-drop.
VDD Pad

VDD

Where does the all power go

to?
Total Power

Core

Standard Cells
Clock network

Macros

I/O
Separate supply ring
Often higher voltage
Fixed, no optimization

Agenda
Introduction to design planning
Floorplanning
Power planning

Intro

to p
power issues in IC design
g
Basic power grid creation
Multi-voltage design & power gating
Automated power grid design flows

Summary

Power Grid Creation : Macro

Placement

Blocks with the

highest
performance and
highest power
consumption
Close to border power
pads (IR drop)
Away from each other
(EM)

Agenda
Introduction to design planning
Floorplanning
Power planning

Intro

to p
power issues in IC design
g
Basic power grid creation
Multi-voltage design & power gating
Automated power grid design flows

Summary

Agenda
Introduction to design planning
Floorplanning
p
g
Power planning

Intro

to power issues in IC design

Basic power grid creation
Multi-voltage
g design
g &p
power g
gating
g
Automated power grid design flows

Summary
y

Automated Power Grid Design:

PNS & PNA

Power grid creation has usually done by hand using

rules of thumb for widths and number of straps
Analysis often done late in the design flow
Grid is typically over-designed to prevent timeintensive power grid changes.
When incorporating advanced low-power strategies,
there are too many variables to achieve an optimal result
manually.
For more complex designs an automated strategy is
preferred.
e.g
e g Power Network Synthesis (PNS) and Power
Network Analysis (PNA) from Synopsys
Allows designers to anticipate affects of floorplanning

P
Power
Network
N t
k Analysis
A l i (PNA)

There are EDA tools that allow early power network

analysis for designs in the early floorplaning stage.
Not
N t signoff
i
ff quality,
lit b
butt good
d enough
h ffor iinitial
iti l d
design.
i
e.g. Synopsys Power Network Analysis (PNA)
VDD Pad

VDD

Power Network Synthesis:

PNS What?

Goal is to QUICKLY find minimum routing resource

required to meet specified IR drop target
More power routing => easier to reach IR-drop
target, but harder to route clock and signals with
remaining tracks
Power straps
(in Red)
Power pads
Power trunks
Power rings

PNS : Running PNS Trials

Run PNS

PNS : C
Create
t P
Power R
Routing
ti

After running
g trials,, an optimal
p
p
power g
grid can be chosen and the
actual rails can be laid out.
Virtual rails => actual rails
Outside main PNS : memory footprint + cpu time
Many options : eg. % Via penetration , order of routing
Check legal cell/pin placement (grid aligned ?)
Depending
p
g on the design
g p
phase
What cells, nets and layers
eg. First macros and pads, then high voltage areas,
Secondary
Seco
da y PG
G po
ports
ts o
on level
e e sshftrs,
t s, isol.
so ce
cells,
s, ret.
et Regs
egs
Later after placement during routing : same as the follow pins for
the normal vdd and gnd of the std cells.

PNS : Create
C t P
Power Routing
R ti

Summary

The g
goal of design
g p
planning
g is to arrange
g the chip
p so that the Place and
Route flow can converge quickly and easily.
Design experience is needed
Floorplan is driven by :
Power
P
Timing
Congestion
Minimum area
There is no 1 way to create a floorplan
Flat hierarchical
Regions,
g
,p
position of the macros
Order of placement IO versus macros versus core
This phase can take a significant portion of the complete backend design
time.
E l analysis
Early
l i off power grid
id iis essential
ti l ffor avoiding
idi major
j problems
bl
near
the end of the design cycle.
Automated power grid tools may help reduce necessary safety margins.

Placement

Design Specification
Logic Design and Verification

F
Front-End
d

Placement in the Flow

Physical
Libraries
Netlist
Physical Design
Constraints

Floorplanning
Placement
Routing

Physical
Design
Stage
g

Ba
ack-End

Logic Synthesis

D fi iti off Pl
Definition
Placementt
Placement : Exact placement of the
modules (modules can be gates, standard
cells macros
cells,
macros).
) The general goal is to
minimize the total area and interconnect
cost.
cost
The quality of the attainable routing is highly
d t
determined
i db
by th
the placement.
l
t
Circuit placement becomes very critical in 90nm
and below technologies.

C tF
Cost
Function
ti for
f Placement
Pl
t
Cost components

Methods of consideration

Area
Wire length

Traditional methods of Placement

Overlap
Timing

Timing driven Placement

Timing-driven

Congestion

Congestion-driven Placement

Clock

Clock Gating

Power

Multivoltage and Multisupply Placement

Placement Steps
p
Input information:
Netlist
Mapped and floorplanned design
Logical and physical libraries
Design constraints
Reading Gate
Gate-level
level netlists from synthesis
Global placement
D il d placement
Detailed
l
Placement optimization
Output information:
Physical layout information
Cell placement locations
Physical layout
layout, timing
timing, and technology information of reference libraries

Inputs for the Placement Tool

Gate-level netlist
Design
constraints

Logical
Target
Placement
tool

Design libraries
Physical
Macro cell
Floorplanned
design
Technology file

Reference
Standard cell

Inside A Physical Library

Example
.lef
l f

Dimension
bounding box

VDD

Blockage
Symmetry
(X, Y, or 90)
;
;
;
;

reference point
(typically 0,0)

MACRO AN2D0
CLASS CORE ;
FOREIGN AN2D0 0.000 0.000 ;
ORIGIN 0.000 0.000 ;
SIZE 1.400 BY 2.520 ;
SYMMETRY x y ;
SITE core ;
PIN Z
ANTENNADIFFAREA 0.1680 ;
DIRECTION OUTPUT ;
PORT
LAYER M1 ;
RECT 1.300 0.640 1.330 1.675
RECT 1.190 0.640 1.300 1.780
RECT 1.140 0.640 1.190 0.900
RECT 1.140 1.520 1.190 1.780
END
END Z
PIN A2
ANTENNAGATEAREA 0.0704 ;
DIRECTION INPUT ;
PORT
LAYER M1 ;
RECT 0.610 0.975 0.770 1.545
END

NAND_1
GND

Abstract View

Pins
(direction, layer
and shape)

T h l
Technology
IInformation
f
ti

For each tool, a specific set of files are required to

provide details about the metal layers for the chosen
process technology
Number and name designations for each layer/via
Physical
Ph i l and
d electrical
l t i l characteristics
h
t i ti ffor each
h llayer
Dielectric constant
Design rules for each layer (min spacing, min width,
etc))
Units and precision for numerical values
Example
p filetypes
yp
.lefhdr, .tf -> contain layer and design rule
information
Also, there are files that enable improved RC estimation
that can be read by the placement engines.
.captable, .tluplus -> store RC coefficients.

Ph i l T
Physical
Technology
h l
D
Data
t

The technology files contain

design rule information that
can be read by the tools
For example,
example the
spacing table constrains
the parallel runlength of
adjacent
dj
t wires
i
on the
th
same layer.
Wire width and pitch are
also described, as well
as any more complex
design rules for routing
routing.

LAYER M1
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
OFFSET 0 ;
PITCH 0.280 ;
WIDTH 0.120 ;
MAXWIDTH 12.000 ;
AREA 0.058 ;
MINENCLOSEDAREA 0.200 ;
THICKNESS 0.240 ;
HEIGHT 0.765 ;

SPACINGTABLE
PARALLELRUNLENGTH
WIDTH
0.00
WIDTH
0.30
WIDTH
1.50
WIDTH
4.50
MINIMUMCUT
MINIMUMCUT
MINIMUMCUT
MINIMUMCUT
MINIMUMCUT

2
4
2
2
2

WIDTH
WIDTH
WIDTH
WIDTH
WIDTH

Example
.lefhdr

0.00
0.12
0.12
0.12
0.12
0.42
0.98
0.70
2.00
3.00

0.52
0.12
0.17
0.17
0.17

1.50
0.12
0.17
0.50
0.50

4.50
0.12
0.17
0.50
1.50

;
FROMABOVE ;
LENGTH 0.70 WITHIN 1.001 ;
LENGTH 2.00 WITHIN 2.001 ;
LENGTH 10.0 WITHIN 5.001 ;

MINIMUMDENSITY 15 ;
MAXIMUMDENSITY 70 ;
DENSITYCHECKWINDOW 50 50 ;
DENSITYCHECKSTEP 50 ;
FILLACTIVESPACING 0.60 ;

Gl b l and
Global
dD
Detail
t il Pl
Placementt
Reading Gate-Level
Gate Level
Netlist from synthesis

Global Placement
Detailed Placement

Pl
Placement
t optimization
ti i ti

Gl b l Pl
Global
Placementt
Standard cells are placed into groups such
that the number of connections between
groups is minimized.
This is solved through circuit partitioning
partitioning.

Bad Placement

Good Placement

Detail Placement : Coarse

Placement
C
Coarse
Pl
Placementt
All the cells are placed in the
approximate
i t locations
l
ti
b
butt th
they
are not legally placed

No logic optimization is done

D t il Pl
Detail
Placementt : L
Legalization
li ti

Legalization: Ensures that the

final placement is legal before
saving the design.

Legal placement of cells is not required for analyzing routing

congestion
ti att an early
l stage
t

H dM
Hard
Macro Pl
Placementt

Hard macros are placed during the

fl
floorplanning
l
i stage
t
and
d th
then marked
k d as
FIXED for placement.
Typically, hard macros are placed near the
sides of the core area.

S
Some
Guidelines
G id li
ffor Pl
Placementt (2)
RAM 1

RAM 2

RAM 3

RAM 4

RAM 5

RAM 6

Avoid
constrictive
channels
Avoid many pins in
the narrow
channel. Rotate for
pin accessibility

RAM 7

RAM 8

Use blockage
t improve
to
i
pin
i
accessibility

Review of Placement Cost

Function
Cost components

Methods of consideration

Area
Wire length

Traditional methods of Placement

Overlap
Timing

Timing-driven Placement

Congestion

Congestion-driven Placement

Clock

Clock Gating

Power

Multivoltage and Multisupply Placement

Ti i D
Timing
Driven
i
Pl
Placementt

Critical p
paths are determined using
g static timing
g
analysis (STA).
Tool attempts to minimize wire length of critical
paths to meet setup timing.
Net RCs are based on Virtual
Routing (VR) estimates

Vi t l Route
Virtual
R t / Trial
T i l Route
R t
Manhatten geometry
Horizontal Vertical
NO diagonal routing

Virtual
Route

Congestion Driven Placement:

Detouring Routes
Congestion Map

Issues with Congestion

Congestion
hot spot

If congestion is not too

severe, the actual route can
be detoured around the
congested area
The detoured nets will have
worse RC delay compared to
the VR estimates

Detour

In highly congested areas

areas, delay estimates during placement will
be optimistic.

C
Congestion
ti M
Map
No need to use -congestion
unnecessarily

Causes high local

utilization

By default, physical synthesis tools

perform some congestion optimization
which has a reasonable chance of
providing acceptable congestion
Congestion driven placement increases
the effort of algorithm to fix congestion
On average congestion option
increases runtime by 20%

For better correlation to post-route,

congestion-driven
co
gest o d e p
placement
ace e t is
se
enabled
ab ed
based on GR congestion map

G
Gives
uniform
f
density

Congestion Driven Placement:

Options

Some Congestion: using medium effort congestiondriven

Max
M routing
ti congestion
ti > 90%
Large hot spots
Bad Congestion: using high effort congestion-driven
Max routing congestion >> 90%
Very
y large
g hot spots
p
Congestion-driven might affect timing negatively but
Post-route numbers will not create surprises
Lower congestion will speed up the detailed router

M dif i Ph
Modifying
Physical
i lC
Constraints
t i t
Modifying Physical Constraints:
Cell Density
Cell densityy can be up
p to
95% by default

x2 y2

Density level can also be

applied to a specific region

Lower cell density in

congested areas using
coordinate option

x1 y1

M dif i th
Modifying
the Fl
Floorplan
l

Top level ports

Top-level
Changing to a different metal layer
Spreading them out, re-ordering or moving to other
sides
Macro location or orientation
Alignment of bus signal pins
Increase of spacing between macros
Core aspect
p
ratio and size
Making block taller to add more horizontal routing
resource
Increase
I
off the
th block
bl k size
i tto reduce
d
overallll congestion
ti
Power grid: Fixing any routed or non-preferred layers

Congestion Driven vs. Timing

Driven Placement

In general there is a direct trade-off

between congestion
g
and timing
g
Timing-driven

placement tries to shorten nets

whereas congestion
g
driven p
placement tries to
spread cells, thus lengthing nets.

Iterative p
placement trials should be
performed to find a balance between the
different tool options/settings.
p
g

Timing and Congestion

Optimization

Some things that can be done for timing optimization

Adding
Addi / d
deleting
l ti b
buffers
ff
Resizing gates
Restructuring the netlist
Swapping pins
Moving
g instances
Area recovery
Congestion optimization tries to reduce local congestion
hotspots.
Generally if congestion exists after placement, little
more can be done
done, if area recovery is not significant
significant.
It is essential that sufficient area is available for any
optimizations that are required

Cl k T
Clock
Tree S
Synthesis
th i
CTS

General Concept of Clock tree

synthesis
y
CLK

CLK

Unbuffered clock tree

Buffered/balanced clock tree

Skew

Area (#buffers)

Power

Slew rates

+ Minimize total insertion delay (latency)

71

S
Sources
off skew
k

Not p
perfectly
y balanced clock tree
Different levels of buffering
Different cells
Different load due to routing
Different RC delays
S
Setting
a skew constraint = 0 ps
Makes no sense
Insertion delay (latency) will increase
Power consumption will increase
Area will increase
Rule of thumb : skew values : 100 150 ps for 90 nm

Extra sources of clock skew : variabilityy

Unwanted Skew Variations
T

Process variations in clock buffers

Power supply noise

H

Temperature variations

.
.
.

Ground plane

part of the OCV (lecture 15)

Gate length
Gate width

L effective

tox

73

CTS in a design flow

VLSI Design Steps
RTL

Simplified CTS Design Flow

Clock
gating

Logical
Clock Tree

Sequentials
((x,y)
,y)

Logic
Synthesis
Physical
Synthesis (Placement)

Clock
Buffering
Routing
Clock Nets

CTS
Sizing
Clock Buffers
Routing

Prepare the netlist for CTS

Analyze the clock trees
Check the clocks
Remove unwanted buffering

R
Remove
unwanted
t db
buffering
ff i

Unnecessary pre-existing clock

buffers/inverters
remove_clock_tree

CTS : Goals
Meeting the clock tree design rule
constraints
Maximum transition delay
Maximum load capacitance
Maximum fanout

Constraints are upper

bound goals. If constraints
are nott met,
t violations
i l ti
will
ill
be reported.

[[Maximum buffer levels]]

defaults
Meeting the clock tree targets
Maximum skew
Min/Max insertion delay (latency)

Highest priority
77

Effect of Clock Tree Synthesis

on placement
Clock buffers added
Congestion may increase
Non clock cells may have been
moved to less ideal locations
Inserting clock trees can
introduce new timing and max
tran/cap violations
real skew taken into
account

Summary
Clock tree synthesis is one of the most
important steps of IC design and can have
a significant impact on timing
timing, power
power, area
area,
etc.
The
Th clocking
l ki strategy
t t
h
has tto b
be di
discussed
d
with the frontend people before CTS is
started
t t d

Clocks

identification
Clock dependencies
Clock balancing

Routing

Overview
Routing fundamentals / Advanced issues
intro
The routing flow
Special topics for 90nm and below
Additional routing considerations
Summary

Physical Design Flow

Physical Design Flow
Design/Constraints Import
Floorplanning
Placement
Clock Tree Synthesis
Routing
g
Post Route Optimization
Fi i hi
Finishing
82

Routing Fundamentals

Goal is to realize the metal/copper connections between the pins of

standard cells and macros

Input :

Goal:

placed design
fixed number of metal/copper layers
routed design that is DRC clean and meets setup/hold timing

Consists of two phases

1. Global
route
Standard
pin
2. Detailcellroute

Vertical
routing
tracks

Horizontal
routing
tracks

Routing Fundamentals :
Advanced Issues

Timing driven routing

Timing

budget for each net

Minimize critical paths

Signal integrity aware : 90nm and below !!!!

Minimize

crosstalk

DFM / DFY
DRC

clean
Rule based versus Model based

General Flow for Routing

Placement and CTS
Route Clock Nets

Global Route Signal Nets

Detail Route Signal Nets

Design for Manufacturing
(DFM)
Geert Vanwijnsberghe - Affiliation

85

Global Route
Vertical routing
capacity = 9 tracks

Horizontal routing
capacity = 9 tracks

X
Y

86

Global Route

Input:
Cell

and macro placement

Routing channel capacity per layer / per direction

Goal:
Perform

fast, coarse grid routing through global routing

cells (GCells) while considering the following:

Wire length
Congestion
Timing
Noise / SI

Often used by placement engines to predict

congestion in the form of a trial ro
route
te or
virtual route
87

Global Route
Global Route
Assigns nets to specific metal layers
and global routing cells (Gcells)

global route

Tries to avoid congested Gcells while

minimizing detours
Congestion exists when more tracks
are needed than available
Detours increase wire length (delay)

Also avoids P/G (rings/straps/rails) and

routing blockages

virtual route
X
congested area

88

Global Route

Preroute

Global route
89

Detail Route

Using global route plan, within each

global route cell
Assign

nets to tracks
Lay
L d
down wires
i
Connect pins to corresponding nets

Solve DRC violations

Reduce cross couple
p cap
p
Apply special routing rules

90

Detail Route: Track Assignment

For nets that

traverse multiple
GCells
Assigns each net to
a specific track and
lays down the actual
metal traces
Makes long, straight
traces and
Reduces the number
of vias

Preroute TA metal traces Jog reduces via count

91

Detail route : Solve DRC Violations

Solve
shorts

Detail Route Boxes

Notch
Spacing

Notch
Spacing

Thin&Fat
Spacing

Mi
Min
Spacing

92

Detail Route: Analysis of Routing

DRC Errors

93

Timing Driven Routing

At 90 Quality of route can effect timing

nm net delay becomes significant
Optimize critical paths
Route some nets first
Most routing freedom at start
Use shortest paths possible
Net weights
Order of routing (priorities : eg. Default : Clocks 50,
others 2)
Wi widening
Wire
id i
Reduce resistance

What is Signal Integrity or SI? (1)

Signal delay caused by crosstalk noise
Possible in 2 directions : p
push-out p
pull-down

Speed Up

net 1

Aggressor

net 2

Victim

Delay

95

What is SI? (2)

Glitch caused by crosstalk noise

Aggressor
Extra clock cycle!
Functional Failure
Vdd

^
Clk

Victim

96

Crosstalk Prevention : Design

Optimization

Noise depends on
Coupling

capacitance
Total net capacitance
Strength of the driver (Rd of the victim net)

Design optimization
Increase

drive strength
strength, often easier (only
local effect)
Buffer long nets

Crosstalk Prevention : Routing

Routing solution
Limit length of parallel nets (H&V)
Wire spreading (skip track - clocks)
Shield special nets
Coupling free routing

98

Crosstalk Prevention : Reduce

Cross Coupling Cap
Critical Nets
Extra space

Spacing

Grounded shields

Shielding
Same layer (H)
Adjacent layers (V)

Net Ordering

99

Effect of Floorplanning on Routing

Congestion

For hierarchical designs, good pin

placement is essential to p
p
preventing
g
routing congestion.
Can

use pin guides during partitioning

Routing around blockages and over

macros
By default routing tool will:
Route over macros

M1- M4 Routing Blockage

Not route where there is a routing

blockage
Not route through a narrow
channel in the non-preferred
non preferred
routing direction

M1- M3 Routing Blockage

M1- M4 Routing Blockage

M4 has a horizontal routing

channel but its preferred
routing direction is vertical

Macro

The preferred routing direction needs to be changed

Clock Tree Routing

For SI prevention we generally want to route

our clocks with extra spacing
spacing.
Global H-trees are often routed manually
before placement
Htree

nets may be routed with wide-metal and

shielding.
Wide-metal
Wide
metal H-Tree
H Tree net

Grounded shields

102

Post Route Clock Tree

Optimization (CTO)
improve the skew on clock nets
Detail Routed
Design
Yes

Before CTO

Short
path

Skew OK?
No
Postroute CTO
ECO Route

After CTO

Increased
delay

O ti
Options
for
f CPU effort
ff t

# processors
Routing

in parallel on # processors
Superthreading, multithreading
Some routers are better a threading than
others

# iterations for detail route

#

of iteration steps done to get a DRC free

design

Summary

Starting from 90 nm technologies

Timing

SI

net delay is becoming more of a factor

Aware Route
Small geometries make SI timing closure much
more difficult

DFM

Driven Route

/ DFY

Now a crucial part of the routing flow

DRC

Number and complexity of DRC rules has

increased dramatically