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EE5502 MOS DEVICES TERM PAPER

A Novel TFET Structure


-employing Hetero-junction source,
Asymmetric Gate Oxide layer along with Gate
Work function engineering.

SUBMITTED BY:
KARNATI PENCHALA ROHITH CHOWDARY / A0076958H
KATHIRESAN RAMPRAKASH / A0077080H

K P ROHITH CHOWDARY Hetero-junction source with simpler


Fabrication
K RAMPRAKASH Asymmetric Gate oxide with gate work
function engineering

EE5502 MOS DEVICES TERM PAPER

[A NOVEL TFET STRUCTURE ]

TABLE OF CONTENTS:

PAGE NO.

1. ABSTRACT ...3
2. INTRODUCTION.................................................................................................................................3
3. DEVICE STRUCTURE AND WORKING PRINCIPLE..................5
4.

CURRENT EXPRESSION..6

5. TUNNEL FET ON CURRENT IMPROVEMENT7


5.1 HETERO-STRUCTURE TFET.........9
5.2 SIMULATION MODEL AND DEVICE PARAMETERS..9
5.3 RESULTS AND DISCUSSION10
5.4 FABRICATION OF THE DEVICE15
6. A NOVEL STRUCTURE TO OPTIMIZE THE SWITCHING SPEED OF A TFET.....16
6.1 STRUCTURE OF DEVICE .16
6.2 REDUCTION OF OFF CURRENT.16
7. GATE WORK FUNCTION ENGINEERING..................19
8. SCALING EFFECT ON ASYMMETRIC GATE OXIDE STRUCTURE........20
9. NOVEL STRUCTURE PROPOSED.21
10. TFET BEATS MOSFET.22
11. CONCLUSION23
12. REFERENCES 23

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1. ABSTRACT:
The latest ITRS roadmap describes in detail the target values for scaling of CMOS down to 35 nm in the year
2014. This gives many exciting materials, physics and integration challenges left to continue CMOS scaling.
Innovative small swing devices are to be designed to cope up with the ITRS roadmap. The low swing switch
such as the Tunnel Field Effect Transistor (TFET) provides a solution in the near future. Though TFETs have
attracted with its sub 60mV/decade sub-threshold swing, its practical application is questionable due to its very
low ON state current and complex fabrication process steps. The ON state current is improved by using
strained Si-Ge hetero-structure at the source and the complicated fabrication process is also solved. Further,
the OFF state current is reduced by 5 orders by using an asymmetric gate oxide implant. The results are
arrived based on experimental data. A device which combines the two approaches has been suggested which
would perform faster while maintaining Ion intact.

2. INTRODUCTION:
Many digital circuit designers are just used to the fact that every year they get more transistors on their chips for
the same cost, and all they have to do is to use a new version of the simulation models of the design and layout
tools and to rely on device and process development for the rest.
In the traditional era of scaling, the gate oxide thickness, Voltage and junction scaling were implemented to
cope up Moores law. The Post TraditionalScalingInnovations include uni-axial strained silicon technology
innovation introduced at 90nm node to enhance mobility, Hi-K gate insulator introduced at 45nm CMOS node
to reduce gate leakage, Metal Gate introduced at 45nm CMOS node to eliminate poly depletion.
As CMOS scaling proceeds closer and closer towards its limits we have seen many new physical effects, most
of them degrading the MOSFET behavior compared to ideal long channel devices. Many challenges have to be
addressed for the CMOS nodes below 45 nm regarding lithography, metallization, power dissipation, circuit
design and also for the device, but this is more a performance issue than a limitation from basic physical laws.
The power packing density in a chip that increases with each generation contributes to the power challenge
the most important limitation to be addressed. Power Dissipation is now limited to approximately 100W, but
increased transistor count is needed in this Multi-Core CPU Era! Then, the dominant leakage power issue has to
be resolved. This issue has continuously slowed down the voltage scaling (90nm:1.2V, 45nm: 1V, 22nm: 0.8V)
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and now saturated by 60mV/decade physical KT/q limit. Future Transistors will need to continue to achieve
higher performance while Scaling Power Supply Voltage. To achieve this, identification of novel power aware
or energy efficient device architectures / mechanisms: small swing switches is necessary [1].
The novel device such as the tunnel FET (TFET) is a quantum-mechanical device that employs a different
transport mechanism based on the inter-band tunneling effect. TFET is basically a MOS gated PiN diode and it
is recently undergoing many theoretical and experimental studies. It has been shown that this device has several
superior properties as compared to the conventional MOSFET. Due to its built-in tunnel barrier, the TFET does
not suffer from short channel effects (SCE) which are detrimental to the MOSFET OFF currents. Moreover, the
sub-threshold swing (SS) of the TFET is not limited to kT/q (=60 mV/decade at 300K).

This enables the TFET to perform more closely to the ideal switch when compared to the MOSFET device.
Here, we discuss methods to boost the ON current Ion (making it intact), reduce the OFF current Ioff and
thereby have an optimized value for Ion / I off ration that will enable faster operation.
OVERCOMING THERMAL kT/q LIMIT BY TUNNELING:

Electrons go over a potential barrier. Hence the sub-threshold slope is limited by the Boltzmann distribution or
60mV/decade (due to sub-threshold current). This can be overcome when the electrons are allowed to pass
through the energy barrier and not over it tunneling. Thereby, a steeper slope is obtained enabling faster
operation.
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3. DEVICE STRUCTURE AND WORKING PRINCIPLE :


As stated earlier, the tunnel Field effect transistor (TFET) is a three terminal MOS gated p-i-n diode which
operates based on Band to Band tunneling (BTBT) mechanism. This is an interesting device whose fabrication
procedure is compatible with CMOS process flow and that has a source doping opposite to the conventional
enhancement mode MOSFET. Figure.1 shows the TFET structure in P and N-modes.

Fig.1 TFET Structure


A positive voltage applied to the drain reverse biases the p-i-n diode; then the gate voltage enables the Tunnel
FET conduction by electron band-to-band tunneling between the source and the intrinsic-region. Fig. 2 shows
the bands in the OFF and ON states for an n-type Tunnel FET.

Fig.2, N-TFET Band diagram

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Increasing the positive voltage on the gate makes the energy barrier between the source and intrinsic region
narrower. When this becomes less than 10 nm wide, significant electron tunneling occurs from the valence band
of the p-region to the conduction band of the i-region causing conduction between drain and source.
Threshold voltage for TFET:
Tunnel FETs have outstanding non-linear abrupt IDSVGS characteristics, essentially dictated by the control
(narrowing) of the energy barrier width, Wb, with the applied gate voltage. It is shown that the Tunnel FET has
the outstanding property of having two threshold voltages: one in terms of gate voltage, VTG, and one in terms of
drain voltage, VTD.[2]
Gate threshold voltage, VTG:
While for the MOS transistor there is a physical definition of the threshold voltage as the gate voltage
corresponding to the onset of strong inversion, there is no such identified mechanism in Tunnel FETs. The gate
threshold voltage, VTG, of the Tunnel FET is defined as as the gate voltage for which the energy barrier
narrowing starts to saturate with the applied gate voltage. One should note that this definition of VTG is
consistent with a MOSFET threshold voltage for which a quasi-saturation of the value of the surface potential is
experienced at threshold.
Drain threshold voltage, VTD:
A unique characteristic of the Tunnel FET is that tunneling requires a certain minimum amount of drain voltage
to turn the device ON, whatever the applied VGS. The drain threshold voltage, VTD, can be defined as the drain
voltage for which the drain current dependence changes from quasi-exponential to linear. This feature is not
shared by conventional MOS transistors.
4. CURRENT EXPRESSION:
We can write the familiar Kanes model of Band to band tunnelling generation rate [3] as
GBTBT =AkaneE2Eg-1/2e-BkaneEg-3/2/E

(1)

Where, Akane and Bkane are constants where Akane = (e2mo1/2)/(18h2) and Bkane =(mo1/2)/(2eh) GBTBT is the
Band to band tunnel generation rate, E is the electric field, Eg is the Energy bandgap, mo is the carrier effective
mass, e is the electronic charge and h is the planks constant.

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This equation (1) is similar to the fowler-Nordheim tunnelling equation for Band to band tunnelling in silicon
assuming a triangular potential barrier. The current density J can be expressed as [4]
J = CE2e-Eo/E

(2)

Where C and Eo are constants corresponding to Akane and Bkane in equation (1).
The maximum Electric field Emax across the tunnel junction is simulated as a function of VGS and VDS [5] and
the tunnelling Electric field can be expressed as Emax = DVgs. We have to note that D here is a function of Vds,
oxide thickness tox, doping concentrations in the three regions and the channel length L. Now we can write
equation (1) with Ids proportional to GBTBT as :
Ids = AkaneD2Eg-1/2V2gse-(BkaneEg3/2)/(VgsD)

(3)

The sub threshold swing of the TFET can be obtained by taking log of equation (3) and differentiating with
respect to Vgs .
So we get,

(4)

5. TUNNEL FET ON CURRENT IMPROVEMENT :


Many different types of Tunnel Field Effect Transistor ( TFET ) with different structures has been proposed
before [5,6,7]. Among these Vertical channel Tunnel FET with strained pseudomorphic SiGe layer is one of the
most discussed one[5]. But due to the complex fabrication steps in the layout and packaging( not compatible
with standard CMOS process ), vertical channel TFET are not a good option for LSTP applications(figure 3).
Then there comes other non Si lateral TFET as proposed by T.Baba [7], or Si lateral TFET as proposed by
Reddick. These devices are fabricated with CMOS compatible process, having good subthreshold slope and
good Ion/Ioff ratio. But the main drawback is the low Ion current. Ion improvement has been discussed in [6] ,
but due to the high K dielectric mobility degradation occurs and under high electric fields dielectric breakdown
occurs, so such an idea is not feasible.

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Figure 3 : Schematic representation of vertical tunnel FET structure with strained SiGe at the source. [5]

Here we are proposing a MOSFET lookalike n-type TFET with sub 60mV/decade subthreshold swing and
improved Ion . Using Strained SiGe layer over the silicon source the improvement in Ion current is achievable. As
said earlier the use of strained SiGe layer over source has been discussed already[5], but because of the complex
fabrication steps involved in layout and packaging, it is not implementable. TCAD simulations were used to
check the devices natural robustness to Short channel effects (SCE) and the device can be fabricated with
standard CMOS process. Some of the key observations are like, the device is immune to Drain induced Barrier
lowering (DIBL) and the Ion is increased exponentially when the mole fraction of Ge is increased. The Device
is shown in the fig 4.

Fig 4 : Proposed N-type TFET structure with strained SiGe layer at source

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5.1 HETERO-STRUCTURE TFET :


The basic idea of introducing a strained SiGe layer over the source is derived from the Ion expression as shown
in equation (3). The exponential term in the equation (3) can be expanded as shown in the equation (5) as the
electron\hole transmission probability (T(E)). So the ON current of a Tunnel FET is proportional to the
electron\hole transportation probability T(E) in BTBT mechanism[9].
Ids(Ion)

T(E)

(5)
Where m* is the carrier effective mass
Eg is the band gap
is Energy range over which tunnelling takes place
tox, tsi,

are the oxide and silicon thickness and dielectric constants resp.

So, from this equation shows that we can improve the Ion current by decreasing tox , increasing

and reducing

Eg. Already we know the effect of using high K-dielectric gate oxide in Boucart and Ionescus work [6]. Now
here we can propose that we can improve the Ion current by modulating the band gap Eg by introducing strained
SiGe(hetero-structure) over the source side and varying the Ge mole fraction (x) [8].
5.2 SIMULATION MODELS AND DEVICE PARAMETERS :
The device is simulated similar to the two-dimensional Kanes Model[3]. Kanes has shown good BTBT
generation and recombination in silicon based tunnel transistors at both low and high temperatures. Here since
the source is highly doped and tunnelling is dependent on Energy band gap, bandgap narrowing model (BNG) is
also included in simulations.
The doping profiles of source, drain and substrate are chosen to optimise the Ion current, here they are chosen to
be 1 x 1020, 5 x 1019, 1 x 1016 cm-3. The performance of the device is very sensitive to the work function of the
gate terminal , but here we are choosing n+ polysilicon compatible to CMOS process. A constant oxide
thickness of tox 2nm and channel length of 100nm is chosen for all simulations.

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5.3 RESULTS AND DISCUSSION :


Impact of Strained SiGe Layer :

Fig 5: Band diagram with strained SiGe at source. Eg is the reduced at the SiGe surface with the introduction of strained SiGe and the
tunnelling width also reduces with the introduction of SiGe.

The figure 5 shows the Systematic band energy diagram with strained SiGe at the source end[5]. As seen from
the figure, with the addition of strained SiGe at the source end will lead to two consequences as : 1) Lowering
of the Band gap at the tunnelling junction. 2) Tunnel width is lowered for SiGe at constant Vgs. We can also
note that lowering of the tunnel width is found with the increase of x in Si(1-x)Gex mole fraction [5]. From the
figure 5 we can infer that introduction of strained SiGe will lead to reduction in tunnelling band gap( Eg ) and
increases the tunnelling probability(equation (5)) and hence increase in drain current(Ion). Similar to that, here
we can show the equilibrium band gap of the proposed device with Ge mole fraction(x)(figure 6(a)).

Fig 6 : The band diagram of theTFET device (a) equilibrium band gap of device for various Ge mole fractions (b) Effect of
introduction of drain bias. As its shown lesser dependence on drain voltage resulting in immunity to DIBL

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Fig 6(b) shows the effect of increasing drain voltage (VDS). As shown in the figure there is negligible difference
in the height and width of the tunnelling with the increase of VDS. The transfer and Output characteristics is
shown in the figure 7. As shown in the figure 7(a) the overall drain current increases with the increase in the Ge
mole fraction (x). Fig 7(b) shows the output characteristics of the proposed device with the Ge mole fraction(x),
the graph shows high output impedance due to the reversed biased p-i-n junction.

Fig 7 (a) Simulated transfer characteristics of the device at various mole fractions (x) for linear and saturation VDS (b) Output
characteristics of the device at various VGS

Fig 8 : Shows the average Subthreshold Swing (SS) vs x and Ion vs x. Ion increases exponentially with x

The Fig 8 shows the plots of Subthreshold swing(SS) with Ge mole fraction (x) and the Ion current vs x . As
from the equation (5), we have seen that the Ion current is exponentially dependent on the Energy band gap (Eg) .
The energy band reduces linearly with the increases of the Ge mole fraction (x). This increase of Ion will lead to
reduction in average subthreshold swing because now the threshold voltage lies in the steeper region of the
curve. Few simulated results are like Ion =580 UA/Um, Ioff = 0.52 fA/Um and average SS of 13mV/decade was
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achievable for x = 0.7 and VDD = 1.2V[8]. However tunnelling through gate oxide was observed and gate
leakage current of 3.7mA/cm2 was obtained[8]. This value is lower than the ITRS specs. Here we have to note
that if Ion is matched with equivalent thicker tox in ITRS specs will leads to lower gate leakage.
Depth of SiGe Layer (Ld )
The TFET structure proposed here has the active region situated right at the surface near the source-channel
junction. The 2D simulations shows that the band to band tunnelling is only observed at the top 20nm of
layer(figure 9). It can be shown that the Ion increase can be achieved by decreasing the Band gap in the 20nm
region below the surface. The figure 10 shows the plot of Ion vs the depth Ld. It is shown that the Ion increases
linearly with the depth Ld till the depth of 20nm. Any further increase of Ld layer beyond this point will increase
the Ioff current. Also shown from figure 10 is that the Ion dependence on Ld is more in the case of more mole
fractioned (x) layer.

Fig.9: two- dimensional simulation shows the


Band to band tunneling in the top 20nm of the device

Fig.10, Ion as a function of Ld. I on increases linearly


up to 20nm then saturates.

SCE and DIBL :


The active region of the tunnel FET is a very thin region near the surface of the source-channel junction. This
shows that the device can be scaled up to channel lengths up to 30nm without affecting its performance. Fig 11
shows the effect of channel length and drain bias on the threshold voltage(VTH).

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Fig 11: Suppressed SCE is seen with the increase of x. DIBL also decreases with increase of x

It is seen that there is virtually no DIBL for x more than 0.3. This is because the barrier width is much stronger
function of x than VDS. Thus if we increase x, lowering of band gap by x is dominating than lowering of band
gap by VDS.
Effect of Body Bias :
The effect of body bias both positive and negative bias is shown in the fig 12. It can be shown that the effect of
Body bias does not affect the threshold voltage or drain current like in MOSFET.

Fig 12 : Effect of body bias. Ge mole fraction here is x=0.3 and VDS=1.0V. ID vs VGS characteristics remains unaltered only the bulk
current increases linearly with body bias. (a) Negative bias (b) Positive bias

High K-Material As Dielectric :


We have already seen the effect of using high K-dielectric to improve Ion[6]. The thickness of Dielectric
material used is very small (less than 3nm), realising such a thin dielectric material is practically not possible,
and their breakdown voltages are lower than SiO2 . If the same high K-dielectric is used with the proposed

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device it is possible to achieve the same Ion for the practically realisable thicknesses (more than 5nm). Figure 13
shows the effect of using high K-dielectric on the drain current for the various Ge mole fraction values.

Fig 13: High dielectric constant (K=29) along with strained SiGe at source helps in achieving good Ion current and subthreshold swing.
Ld=10nm and tdielectric= 5nm.

Effect of Strain of Channel and SiGe Layer :


In this model, strain SiGe is added only to the source side. Firstly, the main reason would be the active region of
device is near the source-channel junction. Secondly, if we add SiGe to the drain there would be strain from
both the sides to the channel. This may lead to increase or decrease of mobility of the channel. The proposed
device will work with same efficiency if we introduce fully SiGe source instead of strained SiGe on the top of
Si Source. We have proposed strained SiGe in certain regions to minimise the stress on the Si channel.

Fig 14 : Band gap of strained SiGe and relaxed SiGe at various values of Ge mole fraction

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5.4 FABRICATION OF THE DEVICE :


The fabrication process flow is given in the figure 15.(a) It starts with Si wafer containing thin layer of strained
SiGe(20nm) layer. Then the Strained SiGe layers are etched in the channel and drain region, Si is grown in
those regions. (b) dummy gate (Si3N4, poly Si, SiO2) formation and source(p+) and drain(n+) are doped using 2
separate masks and spacer formation. The gate is dummy because when we dope source and drain regions, due
to mask misalignment the gate maybe doped with p+, so we are changing the gate later. (c) deposit pre-metal
dielectric(PMD) film SiO2, CMP(chemical mechanical planarization) till Si3N4 is exposed then remove the
dummy gate. (d) Si film is washed with HF acid, grow gate oxide (SiO2\ high K), deposit gate electrode(n+
poly- Si), CMP and PMD is removed.

Fig 15:n-type TFET fabrication process flow (a) STI, etch SiGe in drain and channel, we are left with source alone (b) dummy gate
formation, source(p+) and drain (n+) doping, spacer formation (c) PMD deposition, CMP, removal of dummy gate (d) Clean Si surface
with HF, formation of gate stack, CMP, remove PMD

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6. A NOVEL STRUCTURE TO OPTIMIZE THE SWITCHING SPEED OF A TFET:


The switching speed depends upon the Ion / Ioff ratio. Higher the ration, the faster is the device operation. The
technique to boost Ion current has been discussed earlier. Now the goal is to minimize the OFF current of the
device while maintaining the ON current intact.
The proposed structure employs an asymmetric gate oxide thickness. Along with work function engineering, it
is found possible to reduce the Ioff by 5 orders without significantly affecting the driving current Ion. Hence the
current ratio is boosted up for faster operation.
6.1 STRUCTURE OF THE DEVICE:
The structure is said to have symmetric oxide thickness when the gate oxide thickness is uniform and
asymmetric oxide thickness when a step is employed in the gate oxide near the source end [10].

Fig.16, asymmetric TFET structure

The figure 16 shows the asymmetric TFET structure where HNAR determines the thickness of the extent to
which the oxide layer is raised above the channel outside the tunneling junction.
6.2 REDUCTION IN OFF CURRENT:
The tunneling probability in the tunneling junction is given by the following expression:

Where, m* - electron effective mass, Eg bandgap, energy range in which tunneling occurs, tox - oxide
thickness, tsi silicon thickness (in the tunneling junction), si permittivity of silicon, ox- permittivity of
oxide (in the tunneling junction).
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From the relation, oxide thickness has a low effect on tunneling probability outside the tunneling junction. This
feature enables for the reduction of Ioff. It is implemented by increasing the HNAR. Experimental observation
shows the reduction of Ioff as a function of HNAR as shown in fig. 17:

Fig.17 : Reduction of Ioff as a function of HNAR

The simulation studies were performed using the ISE TCAD tools. The HURX model for BTBT is employed.
The device parameters maintained are: gate length of 100nm, channel doping equals to 1 x 10 17 cm-3, drain
doping of 5 x 10 18 cm-3, source doping of 1 x 10 20 cm-3 and the difference in the metal-semiconductor work
function, ms = -0.55ev. Band gap narrowing model is also employed due to the high doping concentration of
source and drain.
From the plot, it can be inferred that Ioff reduces significantly and approaches a constant for the values of HNAR
above 15nm. The reduction in Ioff can be explained due to the weakening of the electric field in the tunneling
junction region in the OFF state of the device. The electric field lines emanate from the drain region and
terminate on the negative ions present in the tunneling region through the oxide. As HNAR is increased, the oxide
thickness increases which causes the density of electric field lines to reduce in the tunneling junction region in
the OFF state of the device. The fig .18 shows the reduced electric field in the channel, the peaks of the electric
field in the tunneling leakage regions for asymmetric gate oxide thickness in the off state.

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Fig.18 : Reduced electric field in the channel

This further affects the BTBT generation leading to a decreased OFF current. Added to it, the tunneling leakage
is reduced due to the increased tunneling barrier width in the tunneling regions. The following energy band
diagram in fig.19 shows the modified gradient from which the compression of the band in the OFF state can be
inferred.

Fig.19 : Compression of the band in the OFF state

This weakening of electric field affects the BTBT generation leading to a decreased OFF current as shown.

Fig.20 : Decreased OFF current

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From the graph (fig.20), the OFF current, i.e, the current at Vgs=0 is reduced by a factor of 10. In other words,
the OFF current Ioff is reduced by nearly 90%.
7. GATE WORK FUNCTION ENGINEERING:
The optimized Ion/Ioff ration can further be enhanced by employing gate work function engineering concept
which renders Ion intact for a particular value of ms. Ioff is plotted as a function of ms for asymmetric gate
oxide thickness as shown in fig. 21

Fig.21: Ioff as a function of ms for asymmetric gate oxide thickness

It could be inferred that Ioff is reduced as ms is increased. This is due to the shift in the threshold voltage.
However, this process is found to reduce the ON current Ion. For a particular value of ms=2.5 ev, Ioff is found
to be reduced dramatically without any significant reduction in Ion.

Fig.22 : log ID VGS curve

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The log ID VGS curve (fig.22) shows that the OFF current is reduced by 5 orders in an asymmetric gate oxide
structure with reduced gate work function when compared to that of a normal symmetric structure.
8.

SCALING EFFECT ON ASYMMETRIC GATE OXIDE STRUCTURE:

Ion is plotted as a function of gate length as shown in fig. 23

Fig.23 : Ioff vs Gatelength

The plot leads to two inferences:

Ion is nearly independent of gate length. This is due to the fact that active region in the device is a
tunneling junction.

Ion is decreased negligibly for the optimized structure. i.e, for HNAR=15nm and ms = -0.25ev.

Fig.24 : The band diagram of asymmetric oxide structure

The band diagram of the proposed asymmetric oxide structure with lowered gate work function is shown in fig.
24 . The kink in the band diagram around 0.1um may be attributed to the reduced Ion.
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Fig.25 : Ion/Ioff ratio as a function of gate length

Fig. 25 shows the dependence of Ion/Ioff ratio as a function of gate length. Electron direct tunneling from source
to drain becomes dominant in the OFF state with gate length scaling which causes the Ion/Ioff ration to decrease
as Ioff increases.
However, As seen, Ion/Ioff is improved noticeably for the optimized structure. Hence the switching speed of the
device can be increased.
9. NOVEL STRUCTURE PROPOSED:

Figure 26: The proposed device with hetero-junction and asymmetric gate structure to improve the switching speed

The device Structure we are proposing is shown in the figure 26. The device is similar to the normal Tunnel
FET with high doped source side and having a 20nm thick strained Si-Ge over the source side. The gate is an
asymmetric structure with 2nm gate oxide near the tunneling junction and 15nm gate oxide outside the junction.
The gate metal Work function is chosen to be MS = -0.25eV. Using this structure we can increase the Ion and
decrease the Ioff by considerable levels so that we can increase the device switching speed.
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10. TFET BEATS MOSFET


The three terminal TFET has been proposed as the next device replacing the conventional MOSFETs because of
its increased speed by quantum mechanical tunneling. Apart from that, the very low OFF current and
exponentially increasing ON current makes the device score over MOSFETs. The drain current is determined
by electron tunneling from valence band to conduction band of the intrinsic channel for both P-channel as well
as N-channel modes. The carrier mobility in the intrinsic channel region is not dependent on tunneling, it
means that same channel width can be chosen for both the types of device. Furthermore, the tunneling
region(active region) is lesser than 5nm, so the devices could be shrunk to ultra small dimensions without
significant loss in performance. This is possible because the tunnel FET is virtually free from the short channel
effects (SCE) which affects the MOSFET performance. The threshold voltage of the TFET is controlled mainly
by the tunneling width near the tunneling region, so no complicated doping profiles like control of threshold
voltage, drain extension or halo implants are required. The most important advantage will be the subthreshold
slope lower than 60mV/decade in TFETs compared to MOSFETs which are limited by kT/q (60mV/decade at
300K).

Table i: comparison of 20nm Tunnel FET with CMOS


The table i shows the comparison of 20nm tunnel FET with CMOS [11]. It can be seen that TFET has very
less dynamic and leakage power. This is mainly due to the low subthreshold swing and leakage current of
TFET. So we can find several application of TFET in low power applications in the future. As far as power and
energy consumption, TFET is way ahead of MOSFETs.

K.P. ROHITH CHOWDARY & K. RAMPRAKASH

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EE5502 MOS DEVICES TERM PAPER

[A NOVEL TFET STRUCTURE ]

11. CONCLUSION:
A novel hetero-junction asymmetric gate oxide structure with work function engineering has been proposed.
This structure gives a significant improvement in the desired device performance. The Tunnel FET is a
promising transistor for very low OFF currents applications. The use of BTBT as an operation phenomenon in a
switch enabled to demonstrate functional TFETs. We reviewed here the different aspects and particularities of
this innovative device, mainly by experimental results. Thus, the tunnel FET looks good for sub-100 nm analog
and digital applications for both high-speed and low-power applications. Ultimate transistors may need tunnel
injection at ultra-low Vcc. This would require new materials with more efficient tunneling and atomic scale
fabrication control. Nevertheless, scientists, engineers and designers succeeded up to now, to solve or surmount
all these barriers by optimization and new ideas.
12. REFERENCES:
[1] D. Schmitt-Landsiedel *, C. Werner, Innovative devices for integrated circuits A design perspective,
Solid-State Electronics 53 (2009) 411417.
[2] Kathy Boucart, Adrian Mihai Ionescu, A new definition of threshold voltage in Tunnel FETs, Solid-State
Electronics 52 (2008) 13181323.
[3] E. O. Kane, Zener tunneling in semiconductor, J. Phys. Chem. Solids, vol. 12, no. 2, pp. 181188, 1960.
[4] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981, p. 497.
[5] K. Bhuwalka, J. Shulze, A simulation approach to optimize electrical parameters of a vertical tunnel FET,
IEEE Trans. Electron Devices 52 (7) (2005) 15411547.
[6] K.Boucart, A.Ionescu, A Double gate tunnel FET with High K dielectric, IEEE Trans. Electron Devices
54(7)(2007)17251733.
[7] T. Baba, Proposal for surface tunnel transistors, Jpn. J. Appl. Phys. 31 (4B) (1992) L455L457.
[8] Nayan Patel, A.Ramesha , Santanu Mahapatra, Drive current boosting of n-type tunnel FET with strained
SiGe layer at source, Microelectronics Journal 39 (2008) pp.16711677
[9] J.Knoch, J.Appenzeller, A novel concept for field effect transistorsthe tunnelling carbon nanotube FET,
in: Proceedings of the 63rdDRC,vol.1,June2022,2005,pp.153158.
[10] Mahdi Vadizadeh, Morteza Fathipour, Arash Amid, A novel nanoscale tunnel FET structure for
increasing On/Off current ratio, 2008 International conference on Microelectronics.
[11] K K Bhuwalka, Vertical Tunnel Field-Effect Transistor with Bandgap Modulation and Workfunction
Engineering, ESSDERC 2004, Leuven Belgium, Sept.2004, pp.241-244.
[11] Qin Zhang and Alan Seabaugh, Can the Interband Tunnel FET Outperform Si CMOS?, Department
ofElectrical Engineering, University ofNotre Dame, IN 46556.

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