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DESCRIPTION
The LTC2943 measures battery charge state, battery voltage, battery current and its own temperature in portable
product applications. The wide input voltage range allows
use with multicell batteries up to 20V. A precision coulomb
counter integrates current through a sense resistor between
the batterys positive terminal and the load or charger.
Voltage, current and temperature are measured with an
internal 14-bit No Latency ADC. The measurements
are stored in internal registers accessible via the onboard
I2C/SMBus Interface.
APPLICATIONS
n
n
n
n
Power Tools
Electric Bicycles
Portable Medical Equipment
Video Cameras
The LTC2943 features programmable high and low thresholds for all four measured quantities. If a programmed
threshold is exceeded, the device communicates an alert
using either the SMBus alert protocol or by setting a flag
in the internal status register. The LTC2943 requires only
a single low value sense resistor to set the measured
current range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency and PowerPath are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
Total Charge Error vs
Differential Sense Voltage
2.0
1A
LOAD
CHARGER
3.3V
2k
2k
2k
VDD
ALCC
SDA
SENSE+
SENSE
SCL
GND
RSENSE
50m
+
MULTICELL
LI-ION
2943 TA01a
1F
LTC2943
VSENSE+ = 10V
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
0.1
10
100
VSENSE (mV)
2943 TA01b
2943fa
LTC2943
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
SENSE+
GND
GND
SCL
8 SENSE
9
7 GND
6 ALCC
5 SDA
DD PACKAGE
8-LEAD (3mm 3mm) PLASTIC DFN
TJMAX = 150C, JA = 100C/W
EXPOSED PAD (PIN 9) PCB GND CONNECTION OPTIONAL
ORDER INFORMATION
LEAD FREE FINISH
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2943CDD#PBF
LTC2943CDD#TRPBF
LGCS
0C to 70C
LTC2943IDD#PBF
LTC2943IDD#TRPBF
LGCS
40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Requirements
VSENSE+
Supply Voltage
3.6
ISUPPLY
ISENSE+
80
500
15
A
A
A
ISENSE
1
150
1
A
A
A
VUVLO
VSENSE+ Falling
VSENSE+ VSENSE
80
650
15
l
l
l
3.0
3.3
20
120
750
25
A
A
A
3.6
50
mV
Coulomb Counter
VSENSE
RIDR
qLSB
400
0.340
mAh
2943fa
LTC2943
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C.
SYMBOL
PARAMETER
CONDITIONS
TCE
l
l
(Note 8)
VOSE
MIN
TYP
MAX
UNITS
1
1.5
3.5
%
%
%
10
VLSB
TUEV
GainV
INLV
Integral Nonlinearity
TCONV(V)
14
(Note 6)
Bits
23.6
1.44
mV
1
1.3
%
%
1.3
LSB
VSENSE+ > 5V
3.6V VSENSE+ 5V
LSB
48
ms
(Note 8)
VFS(I)
VSENSE
VSENSE+ VSENSE
ILSB
(Note 6)
GainI
12
Bits
60
mV
50
29.3
Offset
INLI
Integral Nonlinearity
TCONV(I)
V
1
1.3
%
%
10
LSB
LSB
ms
VOS(I)
mV
(Note 8)
11
Bits
TFS
Full-Scale Temperature
TLSB
TUET
3
5
K
K
ms
TCONV(T)
(Note 6)
510
0.25
VSENSE+ 5V
0.8
2.2
0.5
1.8
VITH(LV)
VOL
I = 3mA, VSENSE+ 5V
0.4
IIN
VIN = 5V
CIN
10
pF
2943fa
LTC2943
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C.
SYMBOL
PARAMETER
tPCC
CONDITIONS
MIN
TYP
MAX
1
UNITS
s
tBUF(MAX)
1.3
600
ns
600
ns
600
ns
100
ns
50
ns
THDDATO
TOF
(Notes 7, 8)
400
900
kHz
0.3
0.9
20 + 0.1 CB
300
ns
TIMING DIAGRAM
tOF
SDA
tSU(DAT)
tHD(DAT0)
tHD(DAT1)
tBUF
tSU(STA)
tHD(STA)
tSU(STO)
2943 TD01
SCL
tHD(STA)
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
LTC2943
TYPICAL PERFORMANCE CHARACTERISTICS
Total Charge Error vs Differential
Sense Voltage
1.00
0.75
1
0
0.50
VSENSE = 10mV
0.25
0
VSENSE = 50mV
0.25
0.50
10
100
1.00
VSENSE (mV)
15
10
VSENSE+ (V)
20
2943 G01
0.50
25
1.00
50
TA = 85C
ISUPPLY (A)
80
TA = 40C
70
75
60
TA = 25C
20
TA = 85C
15
10
50
100
1.0
25
TA = 25C
25
50
0
TEMPERATURE (C)
30
90
25
2943 G03
110
100
VSENSE = 50mV
0.25
2943 G02
40
0.25
0.75
0.75
3
0.1
VSENSE = 10mV
0.50
TA = 40C
1.00
0.75
ISUPPLY (A)
0.5
TA = 40C
TA = 85C
0
TA = 25C
0.5
5
0
15
10
VSENSE+ (V)
20
25
10
15
VSENSE+ (V)
20
2943 G04
25
1.0
10
15
VSENSE (V)
20
2943 G05
25
2943 G06
TA = 40C TO 85C
TA = 40C
2
0.5
TA = 25C
TA = 85C
1
INL (ILSB)
INL (VLSB)
0
1
0.5
2
6
8
10
15
VSENSE (V)
20
25
2944 G07
1.0
15
10
VSENSE (V)
25
20
2943 G08
3
50
25
0
VSENSE (mV)
25
50
2943 G09
2943fa
LTC2943
TYPICAL PERFORMANCE CHARACTERISTICS
Temperature Error vs Temperature
900
1
COUNTS
0
1
VSENSE+ = 3.6V
VSENSE+ = 5.5V
VSENSE+ = 10V
VSENSE+ = 20V
2
3
50
25
0
25
50
TEMPERATURE (C)
75
100
800
400
700
350
600
300
COUNTS
500
400
250
200
300
150
200
100
100
50
0
1
1.44mV/LSB
2
2943 G11
2943 G10
800 READINGS
0
1
29.3V/LSB
3
2943 G12
PIN FUNCTIONS
SENSE+ (Pin 1): Positive Current Sense Input and Power
Supply. Connect to load/charger side of the sense resistor.
VSENSE+ operating range is 3.6V to 20V. SENSE+ is also
an input to the ADC during current measurement. Bypass
to GND with a 1F capacitor located as close to pin 1 and
pin 2 as possible.
2943fa
LTC2943
BLOCK DIAGRAM
LTC2943
VSUPPLY
1
SENSE+
CC
COULOMB COUNTER
REF
TEMPERATURE
SENSOR
ACCUMULATED
CHARGE
REGISTER
CLK
REFERENCE
GENERATOR
AL
2C/
I
SMBUS
OSCILLATOR
F = 10kHz
ALCC
SCL
SDA
REF+
7
2
3
SENSE
MUX
IN
6
4
5
CLK
ADC
DATA AND
CONTROL
REGISTERS
REF
GND
GND
GND
2943 BD
2943fa
LTC2943
OPERATION
Overview
The LTC2943 includes a 14-bit No Latency analog-todigital converter, with internal clock and voltage reference
circuits.
CHARGER
LOAD
SENSE+
REFHI
VCC
S1
S2
RSENSE
S3
8
SENSE
S4
+
REFLO
BATTERY
2
CONTROL
LOGIC
M
PRESCALER
IBAT
+
ACR
POLARITY
DETECTION
GND
2943 F02
LTC2943
APPLICATIONS INFORMATION
Internal Registers
The LTC2943 register map is shown in Table 1. The
LTC2943 integrates current through a sense resistor,
measures battery voltage, current and temperature and
stores the results in internal 16-bit registers accessible
via I2C. High and low limits can be programmed for each
measured quantity. The LTC2943 continuously monitors
these limits and sets a flag in the status register when a
limit is exceeded. If the alert mode is enabled, the ALCC
pin pulls low.
Table 1. Register Map
ADDRESS NAME REGISTER DESCRIPTION
R/W
00h
Status
01h
Control
R/W
DEFAULT
See Table 2
3Ch
02h
R/W
7Fh
03h
R/W
FFh
04h
R/W
FFh
05h
R/W
FFh
06h
R/W
00h
07h
R/W
00h
08h
Voltage MSB
00h
09h
Voltage LSB
00h
0Ah
R/W
FFh
0Bh
R/W
FFh
0Ch
R/W
00h
0Dh
R/W
00h
0Eh
Current MSB
00h
0Fh
Current LSB
00h
10h
R/W
FFh
11h
R/W
FFh
12h
R/W
00h
13h
R/W
00h
14h
Temperature MSB
00h
15h
Temperature LSB
00h
16h
R/W
FFh
17h
R/W
00h
R = Read, W = Write
NAME
OPERATION
A[7]
Reserved
A[6]
Current Alert
A[5]
Accumulated
Charge
Overflow/
Underflow
A[4]
Temperature
Alert
A[3]
Charge Alert
High
A[2]
Charge Alert
Low
A[1]
Voltage Alert
A[0]
Undervoltage
Lockout Alert
DEFAULT
LTC2943
APPLICATIONS INFORMATION
All status register bits are cleared after being read by the
host, but might be reasserted after the next temperature,
voltage or current conversion or charge integration, if the
corresponding alert condition is still fulfilled.
BIT
NAME
OPERATION
B[2:1]
ALCC
Configure
The operation of the LTC2943 is controlled by programming the control register. Table 3 shows the organization
of the 8-bit control register B[7:0].
NAME
OPERATION
B[7:6]
ADC Mode
DEFAULT
[00]
000
001
010
16
011
64
100
256
101
1024
110
4096
111
4096
Shutdown
[0]
Prescaler M
[10]
B[5:3]
DEFAULT
[111]
10
LTC2943
APPLICATIONS INFORMATION
If neither the alert nor the charge complete functionality
is desired, bits B[2:1] should be set to [00]. The ALCC
pin is then disabled and should be tied to the supply of
the I2C bus with a 10k resistor.
Avoid setting B[2:1] to [11] as it enables the alert and the
charge complete modes simultaneously.
Choosing RSENSE
To achieve the specified precision of the coulomb counter,
the differential voltage between SENSE+ and SENSE must
stay within 50mV. With input signals up to 300mV the
LTC2943 will remain functional but the precision of the
coulomb counter is not guaranteed.
The required value of the external sense resistor, RSENSE,
is determined by the maximum input range of VSENSE and
the maximum current of the application:
RSENSE
50mV
IMAX
50m M
RSENSE 4096
0.340mAh 216
50m
QBAT
In these applications with a small battery but a high maximum current, qLSB can get quite large with respect to the
battery capacity. For example, if the battery capacity is
100mAh and the maximum current is 1A, the standard
equation leads to choosing a sense resistor value of
50m, resulting in:
qLSB = 0.340mAh = 1224mC
50m
RSENSE
or
qLSB = 0.340mAh
RSENSE
qLSB = 0.34mAh
50m M
RSENSE 4096
2943fa
11
LTC2943
APPLICATIONS INFORMATION
To use as much of the range of the accumulated charge
register as possible the prescaler factor M should be
chosen for a given battery capacity QBAT and a sense
resistor RSENSE as:
M 4096
RSENSE
216 0.340mAh 50m
QBAT
M=1
M=4
0.005h
M = 16
0.02h
50mV
IMAX
M = 64
0.08h
RSENSE
M = 256
0.34h
1.4h
M = 1024
5.5h
0.34mAh 216
50m
QBAT
M = 4096
22h
QBAT/IMAX
2943 F03
Figure 3. Choice of Sense Resistor and Prescaler as Function of Battery Capacity and Maximum Current
2943fa
12
LTC2943
APPLICATIONS INFORMATION
Alert Thresholds Registers (E,F,G,H,K,L,M,N,Q,R,S,
T,W,X)
For each of the measured quantities (battery charge,
voltage, current and temperature) the LTC2943 features
high and low threshold registers. At power-up, the high
thresholds are set to FFFFh while the low thresholds are set
to 0000h, with the effect of disabling them. All thresholds
can be programmed to a desired value via I2C. As soon
as a measured quantity exceeds the high threshold or
falls below the low threshold, the LTC2943 sets the corresponding flag in the status register and pulls the ALCC
pin low if alert mode is enabled via bits B[2:1].
Accumulated Charge Register (C,D)
The coulomb counting circuitry in the LTC2943 integrates
current through the sense resistor. The result of this charge
integration is stored in the 16-bit accumulated charge
register (registers C, D). As the LTC2943 does not know
the actual battery status at power-up, the accumulated
charge register (ACR) is set to mid-scale (7FFFh). If the
host knows the status of the battery, the accumulated
charge (C[7:0]D[7:0]) can be either programmed to the
correct value via I2C or it can be set after charging to FFFFh
(full) by pulling the ALCC pin low if charge complete mode
is enabled via bits B[2:1]. Note that before writing to the
accumulated charge registers, the analog section should
be temporarily shut down by setting B[0] to 1. In order to
avoid a change in the accumulated charge registers between
reading MSBs C[7:0] and LSBs D[7:0], it is recommended
to read them sequentially as shown in Figure 10.
Voltage Registers (I,J), and Voltage Threshold
Registers (K,L,M,N)
The result of the 14-bit ADC conversion of the voltage at
SENSE is stored in the voltage registers (I, J).
From the result of the 16-bit voltage registers I[7:0]J[7:0]
the measured voltage can be calculated as:
VSENSE = 23.6V
B01Ch
45084DEC
= 23.6V
16.235V
FFFFh
65535
R SENSE R SENSE
7FFF h
R SENSE
32767
Positive current is measured when the battery is charging and negative current is measured when the battery is
discharging.
RESULTh
RESULTDEC
= 23.6V
FFFFh
65535
2943fa
13
LTC2943
APPLICATIONS INFORMATION
Example 1: a register value of O[7:0] = A8h P[7:0] = 40h
together with a sense resistor RSENSE = 50m corresponds
to a battery current:
IBAT =
7FFF h
50m
T = 510K
RESULTDEC
RESULTh
= 510K
FFFFh
65535
377.3mA
32767
50m
IHIGH (DEC) =
32767 + 32767= 60073
60mV
1A 50m
V 2
CE OV = OS
VSENSE
2943fa
14
LTC2943
APPLICATIONS INFORMATION
The reduction of the impact of the offset in LTC2943 can
be explained by its integration scheme depicted in Figure 2.
While positive offset accelerates the up ramping of the
integrator output from REFLO to REFHI, it slows the down
ramping from REFHI to REFLO thus the effect is largely
canceled as depicted below.
INTEGRATOR
OUTPUT
REFHI
WITHOUT OFFSET
WITH OFFSET
REFLO
FASTER
UP RAMPING
SLOWER
DOWN RAMPING
TIME
2943 F0B
SDA
a6 - a0
SCL
1-7
ADDRESS
R/W
ACK
I2C Protocol
The LTC2943 uses an I2C/SMBus-compatible 2-wire
interface supporting multiple devices on a single bus.
Connected devices can only pull the bus lines low and
must never drive the bus high. The bus wires are externally
connected to a positive supply voltage via current sources
or pull-up resistors. When the bus is idle, all bus lines are
high. Data on the I2C bus can be transferred at rates of
up to 100kbit/s in standard mode and up to 400kbit/s in
fast mode.
Each device on the I2C/SMbus is recognized by a unique
address stored in that device and can operate as either a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be classified as masters or slaves when performing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals to
permit that transfer. At the same time any device addressed
is considered a slave. The LTC2943 always acts as a slave.
Figure 4 shows an overview of the data transmission on
the I2C bus.
Start and Stop Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master signals the beginning of a transmission with
a START condition by transitioning SDA from high to low
while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by
b7 - b0
1-7
b7 - b0
1-7
S
START
CONDITION
P
DATA
ACK
DATA
ACK
STOP
CONDITION
2943 F04
2943fa
15
LTC2943
APPLICATIONS INFORMATION
transitioning SDA from low to high while SCL is high. The
bus is then free for another transmission. When the bus
is in use, it stays busy if a repeated START (Sr) is generated instead of a STOP condition. The repeated START
(Sr) conditions are functionally identical to the START (S).
Write Protocol
REGISTER
DATA
DATA
1100100
02h
F0h
01h
2943 F06
ADDRESS
ADDRESS
REGISTER
DATA
1100100
01h
FCh
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address 1100100 and the
R/W bit set to zero, as shown in Figure 7. The LTC2943
acknowledges and the master sends a command byte
which indicates which internal register the master is to
read. The LTC2943 acknowledges and then latches the
command byte into its internal register address pointer.
The master then sends a repeated START condition followed by the same seven bit address with the R/W bit
now set to one. The LTC2943 acknowledges and sends
the contents of the requested register. The transmission
is ended when the master sends a STOP condition. If
the master acknowledges the transmitted data byte, the
LTC2943 increments its address pointer and sends the
contents of the following register as depicted in Figure 8.
P
2943 F05
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
S: START CONDITION
P: STOP CONDITION
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
ADDRESS
REGISTER
1100100
00h
Sr
ADDRESS
DATA
1100100
01h
2943 F07
ADDRESS
REGISTER
1100100
08h
Sr
ADDRESS
DATA
DATA
1100100
F1h
24h
2943 F08
2943fa
16
LTC2943
APPLICATIONS INFORMATION
Alert Response Protocol
In a system where several slaves share a common interrupt
line, the master can use the alert response address (ARA)
to determine which device initiated the interrupt (Figure 9).
S
DEVICE ADDRESS
0001100
1100100
2943 F09
02h
2943 F10
01h
4C
TO
CHARGER/LOAD
RSENSE
TO BATTERY
40ms
1100100 0 0
08h
2
3
2943 F11
LTC2943
7
6
5
2943 F12
2943fa
17
LTC2943
PACKAGE DESCRIPTION
0.70 0.05
3.5 0.05
1.65 0.05
2.10 0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 0.05
0.50
BSC
2.38 0.05
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
3.00 0.10
(4 SIDES)
R = 0.125
TYP
5
0.40 0.10
8
1.65 0.10
(2 SIDES)
0.75 0.05
4
0.25 0.05
0.50 BSC
2.38 0.10
0.00 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
2943fa
18
LTC2943
REVISION HISTORY
REV
DATE
DESCRIPTION
05/14
Corrected Note 6
PAGE NUMBER
4
2943fa
19
LTC2943
TYPICAL APPLICATION
2-Cell 8.4V Linear Charger and Battery Gas Gauge
VIN = 10V
MBRM120T3
R1
1k
R2
1k
3
SEL
VCC
SENSE
DRV
CHRG
Q1
Si7135DP
LTC1732-8.4
10
4
ACPR
BAT
TIMER
CTIMER
0.1F
PROG
IBAT = 500mA
1
6
GND
C1
1F
RSENSE
0.25
RPROG*
19.6k
C2
10F
0.5A
LOAD
3.3V
R3
2k
R4
2k
R5
2k
C3
1F
LTC2943
VDD
ALCC
SDA
SENSE+
SENSE
SCL
GND
RSENSE
100m
+
8.4V
Li-Ion
BATTERY
2943 TA02
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LTC1732
2943fa
www.linear.com/LTC2943