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Slide 1
WARNING
COMMONWEALTH OF AUSTRALIA
Copyright Regulations 1969
This material has been reproduced and communicated to you by or on
behalf of Monash University pursuant to Part VB of the Copyright Act
1968 (the Act).
The material in this communication may be subject to copyright under
the Act. Any further reproduction or communication of this material by
you may be the subject of copyright protection under the Act.
Slide 2
Outcomes
Design simple combinational logic with always
blocks.
Appreciate high level design approaches.
Avoid common problems.
Slide 3
Slide 4
Example
module MyModule(Z, A, B);
output reg Z;
All output signals of an always
input A, B;
Slide 5
Sensitivity List
Tells the always block when it executes in a
simulation.
When a signal changes in a sensitivity list the
simulator runs the statements in the block
Eg in previous example any change in A or B will
trigger the block.
Slide 6
Body
Sequential statement(s) execute to the end of the
block.
New values of signals at the end of the block after all
statements are used to update the outputs of the
block.
A signal should only be updated in one always
block.
SYNTHESIS tries to find hardware that matches the
behaviour of the sequential statements in the block.
Slide 7
Whoops!
What happens
When Sel is 5
=> Latch inferred
Slide 8
Slide 9
Input Combinations
Combinational functions need to cover all input
combinations in always blocks.
Failing to cover all input combinations results in
inferred latches since the uncovered input
combination has to be preserved between sensitivity
list triggers.
Solutions:
Use default and else in case and if statements
Use assignment of default value at start of always
block.
Slide 10
hrs
4
hr0
5
4
Slide 11
Hrs24toBCD
module Hrs24toBCD(hrs, hr1, hr0);
input [4:0] hrs;
output reg [3:0] hr1, hr0;
always @(
) begin
end
endmodule
ECE2072 Digital Systems
Slide 12
Hrs24toBCD
module Hrs24toBCD(hrs, hr1, hr0);
input [4:0] hrs;
output reg [3:0] hr1, hr0;
always @( hrs
) begin // sensitivity list
hr1 = 4d0;
hr0 = hrs[3:0]; // default values covers all input combinations
if (hrs > 5d9) begin
hr1 = 4d1;
hr0 = hrs[3:0] 4d10;
if (hrs > 5d19) begin
hr1 = 4d2;
hr0 = {2b00, hrs[1:0]}; // optimised version of hrs-20
end
end
end
endmodule
ECE2072 Digital Systems
Slide 13