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M.Tech Student at National Institute of Electronics and Information Technology (NIELIT) Gorakhpur
Scientist-C at National Institute of Electronics and Information Technology (NIELIT) Gorakhpur
ABSTRACT
The simulation result of the 45nm CMOS EIS (Efficient
Inverter scheme) comparator and fat tree encoder circuit
for 2, 3, 4, and 6 bit flash A/D converters are presented
in this paper. Flash A/D converter requires 2n-1
comparators. Each one different from all others depends
on the particular design. The used analog power supply
in this Flash ADC is only 1.2V. Low voltage analog
design is necessary to compile so As to get decreasing
digital supply voltage used for the complete mixedsignal chip. Supply voltages in deep submicron CMOS
technologies decrease due to the short channel effects
and decrease with the technology length. Optimal design
method of Flash ADCs presented in this paper
significantly improves the linearity of the A/D converter
against the CMOS process variation. These 2, 3, 4, and 6
bit Flash ADC consumes .2 watt, .492 watt, .991
watt and 4.556 watt respectively.
Keyword: 45nm, CMOS, EIS, Flash A/Ds, PTM, LTSpice
1. INTRODUCTION
A flash Analog to Digital Converter (ADC)
architecture is mainly used for its high-speed conversion
rate application. The latest VLSI design trend for signal
processing system demands high-speed and low power
consumption.
The simulation of Flash ADCs is done in 45nm
PTM CMOS technology using LT-Spice. The transient
analysis of the ADCs is made by giving a ramp input
signal ranging from 562mV to 680 mV for all Flash
ADCs at a 1.2V Power Supply. The digital codes are
obtained correctly for all Flash ADCs as shown in
following figures.
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The following
figure-6 shows the output
waveform of Fat Tree Encoder.
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Flash Comparat
ADC -or Unit
Encoder
Unit
Total
Power
Sample/
Sec
2-Bit
166.24nw
34.44nw
200nw
1GSPS
3-Bit
377.13nw
115.02nw
492.15
nw
1GSPS
4-Bit
797.28nw
193.94nw
991.22
nw
1GSPS
6-Bit
3.530w
1.025w
4.555
w
1GSPS
7. CONCLUSION
Figure-11 1-out-of-N code of 6 Bit Flash ADC
5.2.2 Fat Tree Encoder Output waveform:
The following figure-12 shows the output
waveform of Fat Tree Encoder.
6. RESULT
The following Table-6.1 shows the power
dissipation calculation of all Flash ADCs which has been
stated in this paper. Here 1.2 volt power supply and
input signal range 562mv to 680mv is used.
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Authors
DHARMENDRA KUMAR GANGWAR received the
B.Tech Degree in
Electronics and Communications
Engineering from Invertis
Institute of Engineering And
Technology Bareilly in 2012.
He is currently working toward
the M.Tech degree in Electronic Design and Technology
in the Department of Electronic Design and Technology,
National Institute of Electronics and Information
Technology (NIELIT) (An Autonomous body of
Department of Electronics & Information Technology,
Government of India) Gorakhpur Centre Gorakhpur273010
dharmendra.gangwar7@gmail.com
DIVAKAR SHAHI received the B.Tech Degree in
Electronics and
Communications Engineering
from IIMT College of
Engineering Greater Noida
in 2012. He is currently working
toward the M.Tech degree in
Electronic Design and Technology in the Department of
Electronic Design and Technology, National Institute of
Electronics and Information Technology (NIELIT) (An
Autonomous body of Department of Electronics &
Information Technology, Government of India)
Gorakhpur Centre, Gorakhpur-273010
divakarshahi05@gmail.com
SH. NISHANT TRIPATHI
nishant@nielit.gov.in
Scientist-'C'
Department of ED&T
National Institute of Electronics
and Information Technology
(NIELIT)(An Autonomous body of Department of
Electronics & Information Technology,
Government of India) Gorakhpur Centre, Gorakhpur273010
[15] Choi, M., & Abidi, A. A. (2001) A 6-b 1.3Gsample/s A/D converter in 0.35-m CMOS, IEEE
Journal of Solid-State Circuits, vol. 36, no. 12, pp. 18471858.
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