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I.
phase
noise,
voltage-
INTRODUCTION
D1
Dn
D2
VTUNE
(a)
VTUNE
OUT-
OUT+
OUT-
OUT+
OUT-
OUT+
(b)
Fig.1. Block diagram (a) single- ended VCO (b) differential ring VCO.
75
International Journal of Advances in Engineering Sciences Vol.3 (3), July, 2013 e-ISSN: 2231-0347 Print-ISSN: 2231-2013
Special Issue: Proceedings of 2nd International Conference on Emerging Trends in Engineering and Management, ICETEM 2013
II.
M3
M4
M7
Vi1+
Vo+
M10
M5
Vi1+
VTUNE
M6
Vi1-
M2
M1
VTUNE
M2
M1
Vi2+
M9
Vo+
M6
M8
Vo-
Vi2+
Vo-
M4
Vi2-
M8
Vi2-
M5
M3
Vi1P5
P1
P2
P6
P4
P3
Vs-
VCOARSE
N4
Vo+
Vp+
N5
VFINE
N1
N2
Vp-
itor at the output node Vo-. As a result, the time for the
output node to rise from low to high is decreased. In order
to avoid the loss of oscillation at the extreme cases of
frequency tuning, extra PMOS loads, P3 and P4, are
added in parallel with the P1 and P2. In this design, the
gates of P3 and P4 are connected to ground to bias the
(1)
76
International Journal of Advances in Engineering Sciences Vol.3 (3), July, 2013 e-ISSN: 2231-0347 Print-ISSN: 2231-2013
Special Issue: Proceedings of 2nd International Conference on Emerging Trends in Engineering and Management, ICETEM 2013
Technology
[1]
[2]
600nm
250nm
Frequency
(MHz)
750-1200
850-2100
[3]
[4]
130nm
65nm
7300-7860
480-1100
IV.
M8
M4
M3
Vi2-
Vo+
M5
M6
S1
Phase noise
(dBc/Hz)
-117@600 KHz
-103.4@1 MHz
-120 to -108@1
MHz
CONCLUSION
Vi2+
Vo-
Power
(mW)
30
10.2@1.5
GHz
60
3.84
VTUNE
REFERENCES
C1
C2
[1]
S2
[2]
Vi1-
Vi1+
M1
M2
[3]
III.
[4]
[5]
[6]
77
International Journal of Advances in Engineering Sciences Vol.3 (3), July, 2013 e-ISSN: 2231-0347 Print-ISSN: 2231-2013