Académique Documents
Professionnel Documents
Culture Documents
Chapter Outline
15.1 Pseudo-NMOS Logic Circuits
15.2 Pass-Transistor Logic Circuits
15.3 Dynamic MOS Logic Circuits
15.4 Emitter-Coupled Logic (ECL)
15.5 BiCMOS Digital Circuits
15-1
Enhancement Load
NMOS Inverter
Pseudo-NMOS Inverters
Depletion Load
NMOS Inverter
Pseudo-NMOS Inverter
15-2
1
k p (VDD Vt ) 2 for vO Vt (saturation)
2
1
iDN
iDN
iDP
iDP
15-3
Region
R i IV (S
(Segmentt DE)
DE):
1
vO (vI Vt ) (vI Vt ) 2 (VDD Vt ) 2
r
Static Characteristics:
VOL (VDD Vt )(1 1 k p / k n )
VOH VDD
VIH Vt
2
3k n / k p
(VDD Vt )
NM H VOH VIH
VM Vt
VIL Vt
VDD Vt
(k n / k p )(k n / k p 1)
NM L VIL VOL
VDD Vt
kn / k p 1
15-4
Dynamic Operation
Determine tPLH:
The analysis is identical to the CMOS inverter and the output capacitance C is charged by PMOS
t PLH
pC
k pVDD
7 V V 2
where p 2 / 3 t t
4 VDD VDD
Determine tPHL:
The discharge current is iDN iDP while iDP is typically negligible as r is large
t PHL
nC
k nVDD
3 1 1 V V 2
where n 2 / 1 1 3 t t
r VDD VDD
4 r
15-5
Gate Circuits
Design of gate circuits refers to a standard pseudo-NMOS inverter
The approach to determine the PDN is identical to that of a complementary CMOS gate
The sizing of the PDN has to be taken into account to meet VOL and delay requirement
Concluding Remarks
In pseudo-NMOS, NOR gates are preferred over NAND gates in order to use minimum-size devices
Pseudo-NMOS is particularly suited for applications in which the output remains high most of the time
The static power dissipation can be reasonably low
The output transitions that matter would presumably be high-to-low ones where the propagation delay
can be made as short as necessary
NTUEE Electronics III
15-6
Y ABC
Y A( B C )
15-7
15-8
15-9
15-10
VDD vO
1
k n (VDD Vtn vO ) 2 and RNeq
1
2
k n (VDD Vtn vO ) 2
2
V v
1
d RPeq 1 DD O
k p (VDD | Vtp |) 2 and
2
k p (VDD | Vtp |) 2
2
For vO |Vtp |:
VDD vO
1
12.5
(k)
(W / L) n
15-11
15-12
Final Remarks
Advantages of CMOS transmission gate over pass-transistor logic with NMOS devices
Logic level: good 1 and 0
No level restoring technique needed
Disadvantages of CMOS transmission gate over pass-transistor logic with NMOS devices
Silicon area and complexity: an additional input requires one NMOS and one PMOS devices
Complementary control signal required
Propagation delay: more capacitive loading from the MOSFETs
15-13
15-14
Nonideal Effects
Noise margin:
Since VIL VIH Vtn , the resulting noise margins are NML Vtn and NMH VDD Vtn
Asymmetric noise immunity (poor NML)
Output voltage decay due to leakage effects:
Leakage current will slowly discharge the output node when PDN is off
The leakage is from the reversed-biased junctions and possibly the subthreshold conduction
Charge sharing:
Some of the internal nodes in PDN will share the charge in CL even the PDN path is off
Can be solved by adding a permanently turn-on
turn on transistor QL at the cost of static power dissipation
15-15
Evaluation
Y1
VM
Y2
t
Premature discharge
t
15-16
Concluding Remarks
Advantages of Domino logic: small silicon area, high-speed operation, and zero static power dissipation
Disadvantages of Domino logic:
Asymmetric noise margin
Leakage issue
Charge sharing
Dead time: unavailability of output during precharge phase
15-17
15-18
15-19
ECL Families
ECL 100K: tP 0.75ns and PD 40mW PDP = 30pJ
ECL 10K: tP 2ns and PD 25mW PDP = 50pJ
A variant of ECL (current-mode logic) has become popular in VLSI applications
NTUEE Electronics III
15-20
OR Transfer Curve
I E |Q R
I E |Q A
VOH 0.88V
4mA
RE
0.779
15-21
for vI = VOH:
VOL
IE
15-22
Manufacturers Specifications
VILmax = 1.475 V VIHmin = 1.105 V
VOLmax = 1.630 V VOHmin = 0.980 V
Fan-Out
IIL = (1.77+5.2)/50 = 69 A IIH = (0.88+5.2)/50 + 4/101 = 126 A
Input currents are small and output resistance is small fan-out of ECL is not limited by logic-level
The fan-out is limited by considerations of circuit speed
Operating Speed
The speed
p
is measured by
y the delayy of its basic ggate and by
y the rise and fall times of the output
p waveforms
Using emitter follower as the output stage, the ECL gate exhibit shorter rise time than its fall time
Signal Transmission
ECL is particularly sensitive to ringing because the signal levels are so small
One solution is to keep the wires very short with respect to the signal rise/fall time
the reflections return while the input is still rising/falling
If greater lengths are needed, then transmission lines must be used
the reflection is suppressed with proper termination
15-23
Power Dissipation
Gate power dissipation of unterminated ECL remain relatively constant independent of the logic state
No current spikes are introduced on the supply line
The need for supply-line bypassing in ECL is not as great as in TTL
Thermal Effects
The reference voltage VR is 1.32V at room temperature
VR is made to change with T in a predetermined manner so as to keep the noise margins almost constant
A demonstration of the high degree of design optimization of this gate circuit
Wired-OR Capability
p
y
The emitter follower output stage of the ECL family allows wired-OR for logic design
The OR function is implemented by wiring the output of several gates in parallel
15-24
15-25
15-26
15-27
Dynamic Operation
iB iD iR1
i (1 )iB iR1
t PLH
iD
CVDD / 2
i
1 W
2
k n VDD VBEon Vtn
2 L N
iR2 VBEon / R2
iB iD iR2
i iB iD
t PHL
CVDD / 2
i
15-28
15-29