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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 7, JULY 2012

A Low-Power Level Shifter With Logic Error

Correction for Extremely Low-Voltage Digital
CMOS LSIs
Yuji Osaki, Student Member, IEEE, Tetsuya Hirose, Member, IEEE, Nobutaka Kuroki, and
Masahiro Numa, Member, IEEE

AbstractThis paper presents a level shifter circuit capable of

handling extremely low-voltage inputs. The circuit has a distinctive current generation scheme using a logic error correction circuit that works by detecting the input and output logic levels. The
proposed level shifter circuit can convert low-voltage digital input
signals into high-voltage digital output signals. The circuit achieves
low-power operation because it dissipates operating current only
when the input signal changes. Measurement results demonstrated
that the circuit can convert a 0.23-V input signal into a 3-V output
signal. The power dissipation was 58 nW for a 0.4-V 10-kHz input
pulse.
Index TermsLevel converter, level shifter, low power, low
voltage, subthreshold.

I. INTRODUCTION

HE most effective and direct way to reduce power

dissipation in digital LSIs is to reduce their supply
voltage because of their quadratic dependence of the power
dissipation on the supply voltage. Several low-power design
techniques have been investigated. Subthreshold LSIsLSIs
whose supply voltage is lower than the threshold voltage
of a MOSFEThave attracted much attention for use in
power-aware LSI applications such as wireless sensor networks, implantable bio-medical systems, and environmental
monitoring devices [1][4]. However, there are a number of
design challenges, and several studies have been carried out.
Among them, one of big issues is in a level shifter (LS) circuit
design [5]. In this paper, we describe and demonstrate an LS
circuit suitable for extremely low-voltage digital LSIs [6], [7].
In low-voltage LSI systems, subthreshold digital LSIs will
be implemented with conventional circuits that operate at high
supply voltage. Therefore, an LS circuit is required to enable
correct communication with other circuits. Moreover, it is also
required when LSI designers must test the functionality of the

Manuscript received November 15, 2011; revised January 31, 2012; accepted
February 19, 2012. Date of publication May 11, 2012; date of current version
June 21, 2012. This paper was approved by Guest Editor Atila Alvandpour. This
work was supported in part by the VLSI Design and Education Center (VDEC),
The University of Tokyo with the collaboration with Cadence Design Systems,
Inc. and Mentor Graphics, Inc., STARC, KAKENHI (21680004), and the New
Energy and Industrial Technology Development Organization (NEDO).
The authors are with the Department of Electrical and Electronic Engineering, Kobe University, Nada, Kobe 657-8501, Japan (e-mail: hirose@eedept.kobe-u.ac.jp).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2012.2191320

low-voltage subthreshold digital circuits. However, communication and function tests are difficult when conventional LS circuits are used because the supply voltage of the subthreshold
digital circuits is below 0.5 V and that of the peripheral circuits is still high (e.g., the supply voltage of input/output (I/O)
peripheral circuits is 3.3 V). This is because the drive current of
the low-voltage circuit significantly lowers as the supply voltage
reduces and conventional LS circuits cannot pull down voltages.
To mitigate this problem, several level shifters and remedies
have been investigated [4], [8][13]. One approach has been to
increase the drive current of the level shifter by enlarging the
transistor channel width. Another is to use a multi-stage level
shifters [4] or inverters with multiple supply voltages. However,
these circuits still depend on the supply voltage difference, the
circuit configuration is complex, and it requires multiple reference voltages. The problem discussed above is thus basically
unresolved.
To solve this problem, we present an LS circuit with a logic
error correction circuit (LECC) capable of handling extremely
low-voltage inputs [6], [7]. The proposed LS circuit can convert extremely low-voltage signals into high-voltage signals.
The circuit is based on a conventional two-stage comparator circuit and has a distinctive feature in a current generation circuit
with an LECC [7].
This paper is organized as follows. Section II briefly describes
the problem with a conventional LS circuit and presents the operation principle of our proposed circuit. Section III shows the
simulation results, Section IV shows the experimental results
with a fabricated proof-of-concept chip, and Section V concludes the paper.
II. LEVEL SHIFTER CIRCUIT
A. Conventional
Fig. 1 shows the schematic of a conventional LS circuit. The
circuit consists of cross-coupled pMOSFETs (MP1 and MP2)
and two nMOSFETs (MN1 and MN2) driven by complementary
input signals IN and INB. The circuit has critical problems when
and
the voltage difference between low supply voltage
becomes large.
high supply voltage
When the voltages of IN and INB are Low and High, MN1
and MN2 are Off and On, respectively. MN2 then pulls down
node OUT, causing MP1 to turn On. Because node OUTB then
, MP2 turns off, and OUT drops to the GND
increases to
level. Note that the voltage of OUT is determined by the drive

0018-9200/$31.00 2012 IEEE

OSAKI et al.: A LOW-POWER LEVEL SHIFTER WITH LOGIC ERROR CORRECTION FOR EXTREMELY LOW-VOLTAGE DIGITAL CMOS LSIs

Fig. 1. Schematic of conventional LS circuit.

Fig. 2. Architecture of proposed LS circuit.

currents of pull-up transistor MP2 and pull-down transistor

MN2. Therefore, if the drive current of MP2 is larger than
that of MN2, OUT cannot be discharged. Moreover, when we
consider the case of extremely low-voltage subthreshold digital
LSIs, because the on-current of MN2 becomes quite low, the
drive currents of the nMOSFETs are significantly smaller than
those of the pMOSFETs, which operate in the strong inversion
region. Thus, OUT cannot be discharged. As a result, a conventional LS circuit cannot correctly operate in this situation.
B. Proposed
The architecture of the proposed LS circuit is shown in Fig. 2.
It consists of a level conversion circuit and a logic error correction circuit (LECC). The complementary input signals (IN and
INB) and the output signal (OUT) are applied to the LECC. The
LECC supplies the operating current for the level conversion
circuit only when the LECC detects a logic error. Fig. 3 shows
the complete schematic of the LS circuit. The operation principles of the circuits are described in the following sections.
1) Level Conversion Circuit: The level conversion circuit,
which is shown on the right in Fig. 3, is based on a conventional two-stage comparator circuit. The comparator generates
output voltage signal, OUT, according to the difference in the
voltage of IN and INB. Note that the voltage of OUT is determined by the drive currents of pull-up transistor MP6 and
pull-down transistor MN8, and that the currents flowing in MP6
and MN8 depend on current flowing through MP2. Therefore,
because both drive currents are determined by the same current,
the circuit is free from the limitations discussed in the conventional ones.
In the conventional comparator design, a current reference
circuit needs to operate steadily. However, because the current
reference circuit dissipates static current and increases power
dissipation, it cannot be used in our design. Therefore, we developed a logic error correction circuit (LECC) in which the
current flowing in the circuit is generated only when the input
signals change.
2) Logic Error Correction Circuit (LECC): The LECC,
which is shown on the left in Fig. 3, consists of two circuit
blocks: 1) a low logic error correction circuit (LLECC) and 2) a
high logic error correction circuit (HLECC). They are driven

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by IN, INB, and OUT. The LECC generates an operating

current such that IN and OUT correspond to each other. When
the output logic level of the LS circuit corresponds to the input
logic level, the LECC does not supply current . When they
do not correspond, the LECC detects the logic error, and the
LLECC or HLECC supplies an operating current. In other
words, because the LECC supplies an operating current only
when the input and output logic levels do not correspond to
each other, the power dissipation of the circuit is minimized.
The correction circuit operations are described below.
LLECC: The low logic error correction circuit, LLECC,
consists of two nMOSFETs (MN1 and MN2) connected
in series. The LLECC operates only when OUT does not
correspond to the Low logic of IN. Fig. 4(a) depicts the
waveforms of IN, INB, and OUT. When IN changes from
High to Low, or when INB changes from Low to High,
there is a period during which OUT does not correspond
to IN. During this period, the LLECC generates fall-transition current
until OUT corresponds to the Low logic
of IN.
When the logic levels of IN and OUT are Low, the LLECC
does not supply any current for the level conversion circuit
because MN2 is off due to the Low logic level of OUT.
However, when the logic levels of IN and OUT do not
correspond (i.e., IN, INB, and OUT are Low, High, and
High, respectively),
flows because the voltages of both
INB and OUT are High;
pulls OUT down to GND so
that the input and output logic levels correspond.
HLECC: The high logic error correction circuit, HLECC,
consists of three nMOSFETs (MN3, MN4 and MN5) and
a pMOSFET (MP1). In contrast to the LLECC, the circuit operates only when OUT does not correspond to the
High logic of IN. Fig. 4(b) depicts the waveforms of IN
and OUT. When IN changes from Low to High, there is
a period during which OUT does not correspond to IN.
During this period, the HLECC generates rise-transition
current
until OUT corresponds to the High logic of IN.
When the logic levels of IN and OUT are High, the
HLECC does not supply any current because the output
voltage of the first stage in the HLECC is Low. However,
when the logic levels of IN and OUT do not correspond
(i.e., IN, INB, and OUT are High, Low, and Low, respectively), the HLECC generates current
, and the
LS circuit operates so that the input and output logic
levels correspond. When IN and OUT are High and Low,
the output voltage of the first stage is High because the
overdrive voltage of the MP1 is larger than that of MN3.
This enables MN4 and MN5 to supply current
to the
level conversion circuit, and
pulls OUT up to
.
From the discussion above, current for the level conversion
circuit is expressed as
(1)
and
are not generated and the LECC does
Because
not supply current when the input and output logic levels
correspond, the power dissipation of the circuit is minimized.
The amount of
and
generated depends on lower supply
voltage of
.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 7, JULY 2012

Fig. 3. Schematic of proposed LS circuit.

Fig. 4. Waveforms (a) when fall-transition current for LS is generated and

(b) when rise-transition current for LS is generated.
TABLE I
TRANSISTOR SIZES OF OUR CIRCUIT

When IN and OUT correspond, the LECC does not supply

any current to the level conversion circuit. However, in fact,
leakage current flows in the circuit. Therefore, because the
voltage gain in the level conversion circuit is sufficient to keep
the output node, OUT is kept at a voltage, i.e.
or GND.
If some unexpected noise ever changes the OUT, the LECC
detects logic errors and supplies the operating current until IN
and OUT once again correspond. On the other hand, if the noise
changes the input logic levels of IN and INB, the LS circuit
cannot operate properly due to the disrupted logic inputs. This
means that the noise immunity of the proposed LS circuit is
limited by that of low-voltage digital circuit. In other words,
the noise margin of the proposed LS circuit is determined by
that of the low-voltage digital circuits themselves.
III. SIMULATION RESULTS
The performance of the proposed LS circuit was evaluated
using SPICE with a set of 0.35- m parameters.
was set
to 3 V. We used an inverter as a load circuit of the LS circuit and
calculated power dissipations including a charge and discharge
current for the load. Table I shows the transistor sizes of the
proposed LS circuit.

Fig. 5. Simulated waveforms of proposed LS circuit. Frequency of input signal

was set to 1 kHz: (a) input signal and output signal; (b)(d) currents flowing in
each circuit in Fig. 3.

A. Waveforms
Fig. 5 shows the simulated waveforms. The amplitude and
frequency
of the input signal were set to 0.4 V and 1 kHz,
respectively. As shown in Fig. 5(a), the 0.4-V input signal was
converted into a 3-V output signal. Fig. 5(b)(d) shows the current flowing in each logic error correction circuit in Fig. 3.
When the input signal of IN changed to High level of
,
there was a period when the logic level of OUT did not correspond to that of IN, as shown in Fig. 5(a). The HLECC detected this and generated current , as shown in Fig. 5(b). This
current was supplied to the level conversion circuit, which converted the 0.4-V input signal into a 3-V output signal. During
this period, the LLECC did not generate current , as shown
in Fig. 5(c). On the other hand, when the input signal of IN
changed to Low level of GND, the LLECC generated current

OSAKI et al.: A LOW-POWER LEVEL SHIFTER WITH LOGIC ERROR CORRECTION FOR EXTREMELY LOW-VOLTAGE DIGITAL CMOS LSIs

Fig. 6. Simulated (a) delays and (b) power dissipations of LS circuits as a function of
at
V.
LS circuits as a function of

while the HLECC did not generate current . This current

was supplied to the level conversion circuit, which converted
the 0.4-V input signal into a 3-V output signal. As shown in
and
were generated alFig. 5(b) and (c), the currents of
ternately in accordance with the logic transition of IN. Fig. 5(d)
generated and supplied to the
shows the current
level conversion circuit. It was generated only when the input
signal changed. Comparing Fig. 5(c) with Fig. 5(d), the current
supplied to the level conversion current was slightly higher
than . This was because the parasitic coupling capacitance between the drain and gate terminals in MP6 in Fig. 3 affected the
gate voltage of MP2 when OUT changed. This effect can be mitigated by reducing the parasitic capacitance (e.g., by changing
the transistor sizes) or by adding a bypass capacitor between the
(or GND).
gate voltage of MP2 and
B. Comparison With Other Level Shifter Circuits
The performance comparison of the proposed LS circuit was
performed using conventional circuit (Fig. 1) and other LS circuits published in [8], [10], [12]. In the conventional circuit
(Fig. 1), MN1 and MN2 were set 100 times larger than MP1
and MP2 so that the low-voltage signals would be converted
correctly. We designed the LS circuits so that they occupy almost same area as the proposed one for fair comparison [8],
[10], [12].
Fig. 6(a) and (b) shows delays and power dissipations of each
LS circuit as function of
at
V and
kHz. The conventional LS circuit could not operate correctly
at
V. This was because the drive current of the
pull-down transistors decreased drastically as
decreased.

at

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V. Simulated (c) delays and (d) power dissipations of

TABLE II
MAXIMUM NOISE VOLTAGE

NOTE:
at the

was set to 0.4 V and conventional LS circuit could not operate

.

The LS circuit in [12] dissipated more power than other ones

because it was based on a current mirror circuit to achieve balanced drive current between pull-down and pull-up transistors.
The power dissipation of the proposed LS circuit was comparable to other LS circuits. Fig. 6(c) and (d) shows delays and
power dissipations of each LS circuit as function of
at
V and
kHz. Compared with other LS
circuits, the proposed circuit showed almost the same performances as other ones.
We simulated input noise characteristics in each LS circuit.
and
were set to 0.4 and 3.0 V, respectively. We applied sine wave as a noise signal into IN and INB, respectively.
Because the delays of LS circuits operated at
V
are large as shown in Fig. 6(a), the LS circuits cannot respond
to high frequency signals. Therefore, we applied low frequency
noise signals of 1 Hz. Table II shows the maximum noise voltage
when LS could not operate correctly. When the input noise was
applied to IN, there was no difference among LS circuits. This

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 7, JULY 2012

TABLE III
CHIP AREA COMPARISON AND RESULTS OF MONTE CARLO SIMULATIONS FOR 500 RUNS

NOTE1:
is the simulated minimum supply voltage of Monte Carlo simulation results.
NOTE2: Numbers represent number of successes.

was because the switching voltage of the inverter determines the

noise immunity of the LS circuits. When the input noise was applied to INB, the proposed LS circuit was more tolerant to other
LS circuits because the proposed LS circuit generates OUT according to the difference in the voltage of IN and INB. In contrast, the output node of the other LS circuits were affected directly by the noise voltage at INB because the drive current of
the pull-down transistor for the output node was sensitive to the
noise voltage of INB.
To investigate circuit operation against process and temperature variations, we performed Monte Carlo statistical circuit
simulations assuming die-to-die (D2D) global variations and
within-die (WID) random mismatch variations in all MOSFETs
using the parameters provided by the manufacturer with various
temperature conditions [14]. We compared the performance of
the proposed circuit with those of a conventional circuit and
other circuits [8], [10], [12]. The amplitude of
was set
to 0.4 V, 0.5 V, or 0.6 V. The input pulse frequency
was
set to very slow frequency (i.e., 1 Hz) to evaluate correct level
conversion operation at lower
. Table III shows the evaluated results of each chip area, the number of success runs that
the LS circuits correctly converted the low-voltage signals into
high-voltage signals, and the minimum
, which each LS
circuit could convert all the inputs correctly, with Monte Carlo
simulations for 500 runs. Note that we calculated each chip area
from their transistor sizes and the areas were normalized with
that of the proposed circuit
The conventional and reported LS circuits could not operate
correctly under lower-temperature and lower-supply-voltage
conditions due to their poor drive current. In contrast, the
proposed LS circuit could operate robustly under all conditions because it does not depend on the balance between the
nMOSFET and pMOSFET drive currents. The minimum
of the proposed circuit was 0.35 V. The minimum
was
decided by functional errors either in the low-voltage digital
circuits or in the differential pair of the LS circuit.
In advanced CMOS process technologies, the impact of
process variations will increase [14]. However, from above
simulation results and discussions, it is proved that the proposed
LS circuit is more tolerant to the variations than other ones.
IV. EXPERIMENTAL RESULTS
We fabricated a proof-of-concept chip using a 0.35- m,
2-poly, 4-metal standard CMOS process. Fig. 7 shows a micro-

Fig. 7. Chip micrograph and partially enlarged view (area: 1880 m ).

Fig. 8. Measurement setup.

graph of the chip and a partial enlarged view of the proposed

LS circuit, which had occupied an area of 1880 m . The
transistor sizes of the fabricated LS circuit were the same as
those of the simulated LS circuit (see Table I). Fig. 8 shows a
measurement setup for the LS circuit. We used an inverter as a
load circuit of the LS circuit. The power dissipation of the LS
circuit was measured excluding a charge and discharge current
for the I/O buffer.
A. Logic Error Correction Circuit (LECC)
As discussed in Section II, the characteristics of the LECC depend on output voltage
. Therefore, we measured the circuit performance for various values of
.
and
were set to 0.4 and 3.0 V, respectively.
Fig. 9(a) shows current measured in the LECC shown in
Fig. 3 as a function of
. IN and INB were respectively
set to 0 and 0.4 V. When
increased from Low, the circuit

OSAKI et al.: A LOW-POWER LEVEL SHIFTER WITH LOGIC ERROR CORRECTION FOR EXTREMELY LOW-VOLTAGE DIGITAL CMOS LSIs

Fig. 9. Measured current

as function of

Fig. 10. Measured maximum current

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(a) when IN and INB were Low and High and (b) when IN and INB were High and Low.

as function of

(a) when IN and INB were Low and High and (b) when IN and INB were High and Low.

generated when
exceeded 0.5 V. That is, the increase in
under the condition
V caused the logic levels of
IN and OUT to no longer correspond, which caused the circuit
to generate current
(and not ), which pulled OUT down to
GND (Low level). The maximum current was about 20 nA.
Fig. 9(b) shows the measured current in the LECC shown
in Fig. 3 as a function of
. IN and INB were respectively
set to 0.4 and 0 V, the opposite of the case shown in Fig. 9(a).
When
decreased from High, the circuit generated when
dropped below 2.5 V. That is, the decrease in
under
the condition
V caused the logic levels of IN and
OUT to no longer correspond, which caused the circuit to generate current
(and not ), which pulled OUT up to
(High level). The sharp drop in
at 2.5 V was because the
first stage, consisting of MP1 and MN3 in the HLECC, is based
on of a common source amplifier, which leads to sharp current
transitions.
Fig. 10 shows the measured maximum in the LECC as a
function of
(a) when IN and INB were Low and High
and (b) when IN and INB were High and Low. The maximum
currents under both conditions had the same characteristics and
increased exponentially with
in the range 0.4 to 0.6 V.
When the voltage was higher than 0.6 V, they increased gradually with
because both maximum currents are determined
by
.

Fig. 11. Measured waveforms of proposed LS for 10-kHz input pulse.

B. Level Shifter Circuit

Fig. 11 shows the measured input and output waveforms of
the proposed LS circuit at 10 kHz. The circuit converted the
0.4-V signal into a 3-V signal.
Fig. 12 shows a shmoo plot of the operating frequency as a
function of
. The maximum operating frequency increased

Fig. 12. Shmoo plot.

exponentially with
in the range 0.4 to 0.6 V because the
current generated in the LECC increased exponentially with

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 7, JULY 2012

TABLE IV
PERFORMANCE SUMMARY AND COMPARISON

[12] , [13] : Simulation results.

and higher than the threshold voltage

currents are expressed as

of the MOSFET, the

(2)
(3)

Fig. 13. Measured power dissipations as a function of

frequencies of 0.1, 1, and 10 kHz.

at input pulse

respectively, where is the aspect ratio

of the transistor,
is the process-dependent parameter, is the carrier mobility,
is the gate-oxide
capacitance,
is the oxide permittivity,
is the oxide thickness, is the subthreshold slope factor,
is the
thermal voltage,
is the Boltzmann constant, is the absolute temperature, and is the elementary charge [15]. Because
period during which the LECC generates the current depends
on the propagation delay of the low voltage digital circuit, can
be expressed as
(4)

Fig. 14. Measured power dissipation as a function of

frequency of 10 kHz.

at the input pulse

, as shown in Fig. 10. When the voltage was higher than

0.6 V, the operating frequency increased gradually with
because the current when
is above the threshold voltage
also increases in the same manner.
Figs. 13 and 14 show the measured power dissipation as a
functions of
and
, respectively. For Fig. 13, the
power was measured at input pulse frequencies of 0.1, 1, and
10 kHz, and for Fig. 14, it was measured at 10 kHz. As shown
in Fig. 13, the power dissipation decreased as input pulse frequency
decreased and was independent of
at a fixed
pulse frequency. As shown in Fig. 14, the power dissipation increased with the square of
. These results can be explained
as follows.
The maximum current generated by the LECC is expressed
as different equations according to
. When
is lower

where is a constant and

is the next-stage load capacitance
of the LS circuit. Note that, from (2), (3), and (4), we can explain the performance characteristics of measured current and
operating frequency as shown in Figs. 10 and 12. The power
dissipation
of the proposed LS circuit can be expressed as
the sum of the internal power dissipation
of the LS circuit
and the power dissipation
for a charge and discharge current of the load capacitance
. Note that leakage power of the
circuit is ignored in this analysis and that the
includes the
power dissipation for a charge and discharge current of the internal node. Because the LECC generates operating current only
when IN and OUT do not correspond, the power dissipation of
the proposed LS circuit can be expressed as

(5)
where
is the average current flowing through the circuit.
Equation (5) shows that is independent of
and depends
on
and the square of
.
The active power dissipation of the LS circuit was extremely
low, 58 nW at an input frequency
of 10 kHz; the corresponding energy
was 5.8 pJ. Static power dissipation

OSAKI et al.: A LOW-POWER LEVEL SHIFTER WITH LOGIC ERROR CORRECTION FOR EXTREMELY LOW-VOLTAGE DIGITAL CMOS LSIs

without applying input pulses was 225 pW. The measured

minimum
, which the LS circuit converted into 3 V, was
0.23 V.
Table IV summarizes the performance of the proposed LS
circuit and compares it with that of other ones [8][13]. The
s and the input frequencies
for energy
are shown
in parentheses. The proposed circuit can convert low voltage
input signals in subthreshold digital circuits to high output signals independently of the supply voltage difference. In addition,
it reduces the static power dissipation because current is generated only when IN and OUT do not correspond.

[12] S. Ltkemeier and U. Rckert, A subthreshold to above-threshold

level shifter comprising a wilson current mirror, IEEE Trans. Circuits
Syst. II, Exp. Briefs, pp. 721724, 2010.
[13] O.-S. Kwon and K.-S. Min, Fast-delay and low-power level shifter for
low-voltage applications, IEICE Trans. Electron., vol. E90-C, no. 7,
pp. 15401543, 2007.
[14] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers,
Matching properties of MOS transistors, IEEE J. Solid-State Circuits, vol. 24, pp. 14331439, 1989.
[15] Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices.
Cambridge, U.K.: Cambridge Univ. Press, 2002.

Yuji Osaki (S09) received the B.E. and M.E.

degrees in electrical and electronic engineering from
Kobe University, Kobe, Japan, in 2008 and 2010,
respectively. He is currently working toward the
Ph.D. degree in electrical and electronic engineering
at Kobe University, Kobe, Japan.
His current research interests are in ultra-lowpower CMOS circuits.
Mr. Osaki is a member of the Institute of Electronics, Information and Communication Engineers
(IEICE).

V. CONCLUSION
We presented a level shifter circuit for extremely low-voltage
digital LSIs. The proposed circuit consists of a logic error correction circuit and a level conversion circuit. It can convert
low-voltage digital input signals into high-voltage digital
output signals and achieve low power operation because it
dissipates current only when the input signal changes. We
fabricated a proof-of-concept chip using a 0.35- m CMOS
process and demonstrated its operation by measurements. The
circuit converted a 0.23-V input signal into a 3-V output signal.
The power dissipation was 58 nW for a 0.4-V 10-kHz input
pulse. The proposed circuit is applicable to ultra-low-voltage
digital circuit systems co-existing with high-voltage digital
circuit systems.
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LSIs, in Dig. Symp. VLSI Circuits, 2000, pp. 202203.

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Tetsuya Hirose (M05) received the B.S., M.S., and

Ph.D. degrees from Osaka University, Osaka, Japan,
in 2000, 2002, and 2005, respectively.
From 2005 to 2008, he was a Research Associate at the Department of Electrical Engineering,
Hokkaido University, Japan. He is currently an
Associate Professor of the department of Electrical
and Electronics Engineering, Kobe University,
Kobe, Japan. His current research interests are in
the field of nano-watt-power analog/digital mixed
signal integrated circuits design and human-centric
intelligent electronic systems.
Dr. Hirose is a member of the Institute of Electronics, Information and
Communication Engineers (IEICE) and the Japan Society of Applied Physics
(JSAP).

Nobutaka Kuroki received the B.E., M.E., and

Dr. Eng. degrees in electronic engineering from
Kobe University, Japan, in 1990, 1992, and 1995,
respectively.
From 1995 to 2005, he was a Research Associate
in the Department of Electrical and Electronic
Engineering, Kobe University. He has been an Associate Professor since 2006. His research interests
include digital signal processing and digital image
processing.
Dr. Kuroki is a member of the IEEJ, IEICE, and
ITE.

Masahiro Numa (M96) received the B.E., M.E.,

and Dr. Eng. degrees in precision engineering from
the University of Tokyo, Tokyo, Japan, in 1983,
1985, and 1988, respectively.
He is currently a Professor with the Department of
Electrical and Electronic Engineering, Kobe University, Kobe, Japan. His research interests include CAD
and low-power design methodologies for VLSI, and
image processing.
Prof. Numa served as the Technical Program Committee Chair of the 17th Workshop on Synthesis And
System Integration of Mixed Information technologies (SASIMI 2012). He is a
member of the ACM, IPSJ, and IEICE.