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Pin diagram 0f 8086 Microprocessor or The hardware model of 8086

Friday, November 18, 2011 Microprocessor and Assembly Language Programming 2 Comments
Pin
diagram
of
8086 microprocessor
The 8086 is a 16-bit microprocessor intended to be used as the CPU in a microcomputer. The
8086 Microprocessor- Internal Architecture shows the details of internal architecture. Following
figure shows the logical pin diagram of 8086 microprocessor. All the signals can be classified
into six groups: 1. Power supply and frequency signals. 2. Clock signal 3. Address bus. 4. Data
bus. 5.Mode selection. 6. Control and status signals. 7. Externally initiated signals, including
interrupts.

Fig: 8086 and pin diagram


1.

Power supply and frequency signals


Vcc is on pin 40 supplies +5V power supply.
Pin 1 and 20 for ground reference.
2.
Clock signal
Pin 19 for clock input (CLK): an 8086 requires a clock signal from some external, crystalcontrolled clock generator to synchronize internal operations in the processor with maximum
frequencies ranging from 5 MHZ to 10 MHZ.
3. Multiplexed address/data Bus
AD0 through AD15 are used at the start of machine cycle to send out addresses and later in the
machine cycle they are used to send or receive data. (This is also known as multiplexing the
bus.) However, the-low order address bus can be separated from these signals by using a latch.
4. Multiplexed address bus
The 8086 has 4 signal lines A16/S3 through A19/S6. The double mnemonic on these pins
indicates that address bits A16 through A19 are sent out on these lines during the first part of a
machine cycle and the status information, which identifies the type of operation to be done in
that cycle, is sent out on these lines S3 through S6 during a later part of the cycle.
5. Mode selection
The operating mode of the 8086 is determined by the logic level applied to the

MNMX
input on pin 33. If pin 33 is asserted high, then the 8086 will function in minimum mode, and
pins 24 through 31 will have the functions shown in parentheses next to the pins i.e.
INTA,
ALE,
DEN,
DT/R,
M/IO,
WR,
HLDA, and HOLD. If the 8086 is in minimum mode in systems, it works as a single
microprocessor on the system buses.
If the
MNMX
pin is asserted low, then the 8086 is in maximum mode. In this mode pins 24 through 31 will
have the functions described by the mnemonics next to the pins i.e. QS1, QS0,
S0,
S1,
S2,
LOCK,
RQ/GT1,
and
RQ/GT0.
If the 8086 is in maximum mode in systems, it has two or more microprocessors sharing the
same buses and this mode is called multiprocessor mode.
6. Control and status signal
This group of signals is to identify the nature of the operations. These signals are as follows.
a.
ALE- Address Latch Enable (pin 25): this is a positive going pulse generated every time the
8086 begins an operation (machine cycle).This output signal indicates the availability of the
valid address is on the address/data lines.
b.
RD
(pin 32) Read: This is read control signal (active low). This signal indicates that the selected I/O or
memory device is to be read and data are available on the data bus.
c.
WR
(pin 29) Write: This is a write control signal (active low). This signal indicates that the data on the
data bus are to be written into a selected memory or I/O location.
d.
M/IO
(Pin 28): when it is high, reading from and writing to a memory location, and if it is low, reading
from and writing to a port.
e.
S0,S1,S2
(pins 26, 27 and 28): these control bus signals are sent out encoded form of data and an external bus
controller device decodes these signals to produce the control bus signals required for a system
which has two or more microprocessors sharing the same buses.

f.
DEN
(pin 26) Data Enable signal: it is used to enable bidirectional buffers on the data bus, when DEN is
low. i.e. it send data out on the data bus and read the data in on the data bus.
g.
DTR
(pin 27) Data transmit/receive signal: when
DTR
is high, the 8086 is used to decide the direction in which the buffers are enabled through
the DEN the 8086 transmit the data to ROM, RAM, or ports. when
DTR
is low, the buffers will allow data to come in from ROM, RAM, and ports.
h.
BHE/S7
(pin 34) Bus high enable: The bus high enable is used to indicate the transfer of data over the higher
order data bus If it goes low, the address that it will be writing to on AD0 - A19.
7. Interrupts and Externally initiated signals:
a.
NMI (Nonmaskable interrupt pin 17) and INTR (interrupt pin 18) input :A signal can be
applied to one of these inputs to cause the 8086 to interrupt the program it is executing and go
execute a specified procedure.
b.
HOLD input (pin 31): when the HOLD line is high , this signal indicates that a peripheral such
as a DMA (DMA Direct memory Access) controller is requesting the use of the address and data
buses.
c.
HLDA (pin 30) Hold Acknowledge: This signal acknowledges the HOLD request.
d.
READY input (pin 22): This signal is used to delay the microprocessor Read or Write cycles
until a slow responding peripheral is ready to send or accept data. When this signal goes low, the
microprocessor waits for an integral number of clock cycles until it goes high.
e.
RESET (pin 21): This signal indicates that the MPU (microprocessor) is being reset. The
signal can be used to reset other devices.

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8086 CPU ARCHITECTURE
The microprocessors functions as the CPU in the stored program model of the digital computer.
Its job is to generate all system timing signals and synchronize the transfer of data between
memory, I/O, and itself. It accomplishes this task via the three-bus system architecture previously
discussed.
The microprocessor also has a S/W function. It must recognize, decode, and execute program
instructions fetched from the memory unit. This requires an Arithmetic-Logic Unit (ALU) within

the CPU to perform arithmetic and logical (AND, OR, NOT, compare, etc) functions.
The 8086 CPU is organized as two separate processors, called the Bus Interface Unit (BIU) and
the Execution Unit (EU). The BIU provides H/W functions, including generation of the memory
and I/O addresses for the transfer of data between the outside world -outside the CPU, that isand the EU.
The EU receives program instruction codes and data from the BIU, executes these instructions,
and store the results in the general registers. By passing the data back to the BIU, data can also
be stored in a memory location or written to an output device. Note that the EU has no
connection to the system buses. It receives and outputs all its data thru the BIU.

The only difference between an 8088 microprocessor and an 8086 microprocessor is the BIU. In
the 8088, the BIU data bus path is 8 bits wide versus the 8086's 16-bit data bus. Another
difference is that the 8088 instruction queue is four bytes long instead of six.
The important point to note, however, is that because the EU is the same for each processor, the
programming instructions are exactly the same for each. Programs written for the 8086 can be
run on the 8088 without any changes.

FETCH AND EXECUTE


Although the 8086/88 still functions as a stored program computer, organization of the CPU into
a separate BIU and EU allows the fetch and execute cycles to overlap. To see this, consider what
happens when the 8086 or 8088 is first started.
1. The BIU outputs the contents of the instruction pointer register (IP) onto the address bus,
causing the selected byte or word to be read into the BIU.
2. Register IP is incremented by 1 to prepare for the next instruction fetch.
3. Once inside the BIU, the instruction is passed to the queue. This is a first-in, first-out storage
register sometimes likened to a "pipeline".
4. Assuming that the queue is initially empty, the EU immediately draws this instruction from the
queue and begins execution.
5. While the EU is executing this instruction, the BIU proceeds to fetch a new instruction.
Depending on the execution time of the first instruction, the BIU may fill the queue with several
new instructions before the EU is ready to draw its next instruction.

The BIU is programmed to fetch a new instruction whenever the queue has room for one (with

the 8088) or two (with the 8086) additional bytes. The advantage of this pipelined architecture is
that the EU can execute instructions almost continually instead of having to wait for the BIU to
fetch a new instruction.
There are three conditions that will cause the EU to enter a "wait" mode. The first occurs when
an instruction requires access to a memory location not in the queue. The BIU must suspend
fetching instructions and output the address of this memory location. After waiting for the
memory access, the EU can resume executing instruction codes from the queue (and the BIU can
resume filling the queue).
The second condition occurs when the instruction to be executed is a "jump" instruction. In this
case control is to be transferred to a new (nonsequential) address. The queue, however, assumes
that instructions will always be executed in sequence and thus will be holding the "wrong"
instruction codes. The EU must wait while the instruction at the jump address is fetched. Note
that any bytes presently in the queue must be discarded (they are overwritten).
One other condition can cause the BIU to suspend fetching instructions. This occurs during
execution of instructions that are slow to execute. For example, the instruction AAM (ASCII
Adjust for Multiplication) requires 83 clock cycles to complete. At four cycles per instruction
fetch, the queue will be completely filled during the execution of this single instruction. The BIU
will thus have to wait for the EU to pull over one or two bytes from the queue before resuming
the fetch cycle.
A subtle advantage to the pipelined architecture should be mentioned. Because the next several
instructions are usually in the queue, the BIU can access memory at a somewhat "leisurely" pace.
This means that slow-mem parts can be used without affecting overall system performance.
PROGRAMING MODEL
As a programmer of the 8086 or 8088 you must become familiar with the various registers in the
EU and BIU.

The data group consists of the accumulator and the BX, CX, and DX registers. Note that each
can be accessed as a byte or a word. Thus BX refers to the 16-bit base register but BH refers only
to the higher 8 bits of this register. The data registers are normally used for storing temporary
results that will be acted on by subsequent instructions.
The pointer and index group are all 16-bit registers (you cannot access the low or high bytes
alone). These registers are used as memory pointers. Sometimes a pointer reg will be interpreted
as pointing to a memory byte and at other times a memory word. As you will see, the 8086/88
always stores words with the high-order byte in the high-order word address.
Register IP could be considered in the previous group, but this register has only one function -to
point to the next instruction to be fetched to the BIU. Register IP is physically part of the BIU
and not under direct control of the programmer as are the other pointer registers.
Six of the flags are status indicators, reflecting properties of the result of the last arithmetic or
logical instructions. The 8086/88 has several instructions that can be used to transfer program
control to a new memory location based on the state of the flags.
Three of the flags can be set or reset directly by the programmer and are used to control the
operation of the processor. These are TF, IF, and DF.
The final group of registers is called the segment group. These registers are used by the BIU to
determine the memory address output by the CPU when it is reading or writing from the memory
unit. To fully understand these registers, we must first study the way the 8086/88 divides its
memory into segments.

SEGMENTED MEMORY
Even though the 8086 is considered a 16-bit processor, (it has a 16-bit data bus width) its
memory is still thought of in bytes. At first this might seem a disadvantage:
Why saddle a 16-bit microprocessor with an 8-bit memory?
Actually, there are a couple of good reasons. First, it allows the processor to work on bytes as
well as words. This is especially important with I/O devices such as printers, terminals, and
modems, all of which are designed to transfer ASCII-encoded (7- or 8-bit) data.
Second, many of the 8086's (and 8088's) operation codes are single bytes. Other instructions may
require anywhere from two to seven bytes. By being able to access individual bytes, these oddlength instructions can be handled.
We have already seen that the 8086/88 has a 20-bit address bus, allowing it to output 210, or
1'048.576, different memory addresses. As you can see, 524.288 words can also be visualized.
As mentioned, the 8086 reads 16 bits from memory by simultaneously reading an odd-addressed
byte and an even-addressed byte. For this reason the 8086 organizes its memory into an evenaddressed bank and an odd-addressed bank.
With regard to this, you might wonder if all words must begin at an even address. Well, the
answer is yes. However, there is a penalty to be paid. The CPU must perform two memory read
cycles: one to fetch the low-order byte and a second to fetch the high-order byte. This slows
down the processor but is transparent to the programmer.
The last few paragraphs apply only to the 8086. The 8088 with its 8-bit data bus interfaces to the
1 MB of memory as a single bank. When it is necessary to access a word (whether on an even- or
an odd-addressed boundary) two memory read (or write) cycles are performed. In effect, the
8088 pays a performance penalty with every word access. Fortunately for the programmer,
except for the slightly slower performance of the 8088, there is no difference between the two
processors.
MEMORY MAP
Still another view of the 8086/88 memory space could be as 16 64K-byte blocks beginning at
hex address 000000h and ending at address 0FFFFFh. This division into 64K-byte blocks is an
arbitrary but convenient choice. This is because the most significant hex digit increments by 1
with each additional block. That is, address 20000h is 65.536 bytes higher in memory than
address 10000h. Be sure to note that five hex digits are required to represent a memory address.

The diagram is called a memory map. This is because, like a road map, it is a guide showing how
the system memory is allocated. This type of information is vital to the programmer, who must
know exactly where his or her programs can be safely loaded.
Note that some memory locations are marked reserved and others dedicated. The dedicated
locations are used for processing specific system interrupts and the reset function. Intel has also
reserved several locations for future H/W and S/W products. If you make use of these memory
locations, you risk incompatibility with these future products.
SEGMENT REGISTERS
Within the 1 MB of memory space the 8086/88 defines four 64K-byte memory blocks called the
code segment, stack segment, data segment, and extra segment. Each of these blocks of memory
is used differently by the processor.
The code segment holds the program instruction codes. The data segment stores data for the
program. The extra segment is an extra data segment (often used for shared data). The stack
segment is used to store interrupt and subroutine return addresses.
You should realize that the concept of the segmented memory is a unique one. Older-generation
microprocessors such as the 8-bit 8086 or Z-80 could access only one 64K-byte segment. This
mean that the programs instruction, data and subroutine stack all had to share the same memory.
This limited the amount of memory available for the program itself and led to disaster if the

stack should happen to overwrite the data or program areas.


The four segment registers (CS, DS, ES, and SS) are used to "point" at location 0 (the base
address) of each segment. This is a little "tricky" because the segment registers are only 16 bits
wide, but the memory address is 20 bits wide. The BIU takes care of this problem by appending
four 0's to the low-order bits of the segment register. In effect, this multiplies the segment
register contents by 16.

The point to note is that the beginning segment address is not arbitrary -it must begin at an
address divisible by 16. Another way if saying this is that the low-order hex digit must be 0.
Also note that the four segments need not be defined separately. Indeed, it is allowable for all
four segments to completely overlap (CS = DS = ES = SS).
Memory locations not defined to be within one of the current segments cannot be accessed by
the 8086/88 without first redefining one of the segment registers to include that location. Thus at

any given instant a maximum of 256 K (64K * 4) bytes of memory can be utilized. As we will
see, the contents of the segment registers can only be specified via S/W. As you might imagine,
instructions to load these registers should be among the first given in any 8086/88 program.
LOGICAL AND PHYSICAL ADDRESS
Addresses within a segment can range from address 00000h to address 0FFFFh. This
corresponds to the 64K-byte length of the segment. An address within a segment is called an
offset or logical address. A logical address gives the displacement from the address base of the
segment to the desired location within it, as opposed to its "real" address, which maps directly
anywhere into the 1 MB memory space. This "real" address is called the physical address.
What is the difference between the physical and the logical address?
The physical address is 20 bits long and corresponds to the actual binary code output by the BIU
on the address bus lines. The logical address is an offset from location 0 of a given segment.

When two segments overlap it is certainly possible for two different logical addresses to map to
the same physical address. This can have disastrous results when the data begins to overwrite the
subroutine stack area, or vice versa. For this reason you must be very careful when segments are
allowed to overlap.
You should also be careful when writing addresses on paper to do so clearly. To specify the
logical address XXXX in the stack segment, use the convention SS:XXXX, which is equal to

[SS] * 16 + XXXX.
ADVANTAGES OF SEGMENTED MEMORY
Segmented memory can seem confusing at first. What you must remember is that the program
op-codes will be fetched from the code segment, while program data variables will be stored in
the data and extra segments. Stack operations use registers BP or SP and the stack segment. As
we begin writing programs the consequences of these definitions will become clearer.
An immediate advantage of having separate data and code segments is that one program can
work on several different sets of data. This is done by reloading register DS to point to the new
data. Perhaps the greatest advantage of segmented memory is that programs that reference
logical addresses only can be loaded and run anywhere in memory. This is because the logical
addresses always range from 00000h to 0FFFFh, independent of the code segment base. Such
programs are said to be relocatable, meaning that they will run at any location in memory. The
requirements for writing relocatable programs are that no references be made to physical
addresses, and no changes to the segment registers are allowed.

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8086 pin diagram description

8086 Pin diagram And Explanation


The 8086 can operate in two modes these are the minimum mode and maximum mode .For
minimum mode, a unique processor system with a single 8086 and for Maximum mode a multi
processor system with more than one 8086.
MN/MX- is an input pin used to select one of this mode .when MN/MX is high the 8086
operates in minimum mode .In this mode the 8086 is configured to support small single
processor system using a few devices that the system bus .when MN/MX is low 8086 is
configured to support multiprocessor system.
The AD0-AD15 lines are a 16bit multiplexed addressed or data bus. During the 1st clock cycle
AD0-AD15 are the low order 16Bit adders. The 8086 has a total of 20 address line ,the upper 4
lines are multiplexed with the state signal that is A16/S3 , A17/S4 , A18/S5 , A19 /S6.During the

first clock period of a best cycle the entire 20bit address is available on these line. During all
other clock cycles for memory and i/o operations AD15-AD0 contain the 16 bit data and
S3,S4,S5,S6 become the status line .S3 and S4 are decoded as follows
A17/S4 A16/S3 Function
0 0 Extra Segment
0 1 Stack Segment
1 0 code or No segment
1 1 Data Segment
There for the 1st clock cycle of an instruction execution the A17/S4 And A16/S3 pins Specify
which Segment register generate the segment portions of the 8086 address
BHE/S7 is used as best high enable during the 1st click cycle of an instruction execution .the
BHE can be used in conjunction with AD0 to select the memory
RD is low when the data is read from memory or I/O location .
TEST is an input pin and is only used by the wait instruction .the 8086 enter a wait state after
execution of the wait instruction until a low is Sean on the test pin.
INTR is a maskable interrupt input.
NIM is the non maskable interrupt input.
RESET is the system set reset input signal it terminates all the activities it clear
PSW,IP,DS,SS,ES and the instruction Queue.
DT/R(Data Transmit or receive ):is an o/p signal required in system that uses the data bus
transceiver
ALE is an address latch enable . Is an o/p signal provided by the 8086 and can be used to
demultiplexed AD0 to AD15 in to A10 toA15 and D0 to D15.
M/IO is an 8086 output signal to distinguish a memory access and i/o access.
WR is used by the 8086 for performing write memory or write i/o operation .
INTA(interrupt acknowledgement signal )
INTA is the interrupt acknowledgment signal

HOLD and HOLDA


a high on the HOLD pin indicates that another master is required to take over the S/M bus
CLK clock provides the basic timing signals for the 8086 and bus controls .
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Pin Diagram and Pin description of 8086

The following pin function descriptions are for the microprocessor 8086 in either minimum or
maximum mode.
AD0 - AD15 (I/O): Address Data Bus

These lines constitute the time multiplexed memory/IO address during the first clock cycle (T1)
and data during T2, T3 and T4 clock cycles. A0 is analogous to BHE for the lower byte of the
data bus, pins D0-D7. A0 bit is Low during T1 state when a byte is to be transferred on the lower
portion of the bus in memory or I/O operations. 8-bit oriented devices tied to the lower half
would normally use A0 to condition chip select functions. These lines are active high and float to
tri-state during interrupt acknowledge and local bus "Hold acknowledge".
A19/S6, A18/S5, A17/S4, A16/S3 (0): Address/Status

During T1 state these lines are the four most significant address lines for memory operations.
During I/O operations these lines are low. During memory and I/O operations, status information
is available on these lines during T2, T3, and T4 states.S5: The status of the interrupt enable flag
bit is updated at the beginning of each cycle. The status of the flag is indicated through this bus.
S6:

When Low, it indicates that 8086 is in control of the bus. During a "Hold acknowledge" clock
period, the 8086 tri-states the S6 pin and thus allows another bus master to take control of the
status bus.
S3 & S4:

Lines are decoded as follows:


A17/S4

A16/S3

Function

Extra segment access

Stack segment access

Code segment access

Data segment access

After the first clock cycle of an instruction execution, the A17/S4 and A16/S3 pins specify which
segment register generates the segment portion of the 8086 address. Thus by decoding these lines
and using the decoder outputs as chip selects for memory chips, up to 4 Megabytes (one Mega
per segment) of memory can be accesses. This feature also provides a degree of protection by
preventing write operations to one segment from erroneously overlapping into another segment
and destroying information in that segment.
BHE /S7 (O): Bus High Enable/Status

During T1 state theBHE should be used to enable data onto the most significant half of the data
bus, pins D15 - D8. Eight-bit oriented devices tied to the upper half of the bus would normally
use BHE to control chip select functions. BHE is Low during T1 state of read, write and interrupt
acknowledge cycles when a byte is to be transferred on the high portion of the bus.
The S7 status information is available during T2, T3 and T4 states. The signal is active Low and
floats to 3-state during "hold" state. This pin is Low during T1 state for the first interrupt
acknowledge cycle.
RD (O): READ

The Read strobe indicates that the processor is performing a memory or I/O read cycle. This
signal is active low during T2 and T3 states and the Tw states of any read cycle. This signal
floats to tri-state in "hold acknowledge cycle".
TEST (I)

TEST pin is examined by the "WAIT" instruction. If the TEST pin is Low, execution continues.
Otherwise the processor waits in an "idle" state. This input is synchronized internally during each
clock cycle on the leading edge of CLK.
INTR (I): Interrupt Request

It is a level triggered input which is sampled during the last clock cycle of each instruction to
determine if the processor should enter into an interrupt acknowledge operation. A subroutine is
vectored to via an interrupt vector look up table located in system memory. It can be internally
masked by software resetting the interrupt enable bit INTR is internally synchronized. This
signal is active HIGH.
NMI (I): Non-Muskable Interrupt

An edge triggered input, causes a type-2 interrupt. A subroutine is vectored to via the interrupt
vector look up table located in system memory. NMI is not maskable internally by software. A
transition from a LOW to HIGH on this pin initiates the interrupt at the end of the current
instruction. This input is internally synchronized.
Reset (I)

Reset causes the processor to immediately terminate its present activity. To be recognised, the
signal must be active high for at least four clock cycles, except after power-on which requires a
50 Micro Sec. pulse. It causes the 8086 to initialize registers DS, SS, ES, IP and flags to all
zeros. It also initializes CS to FFFF H. Upon removal of the RESET signal from the RESET pin,
the 8086 will fetch its next instruction from the 20 bit physical address FFFF0H. The reset signal
to 8086 can be generated by the 8284. (Clock generation chip). To guarantee reset from powerup, the reset input must remain below 1.5 volts for 50 Micro sec. after Vcc has reached the
minimum supply voltage of 4.5V.
Ready (I)

Ready is the acknowledgement from the addressed memory or I/O device that it will complete
the data transfer. The READY signal from memory or I/O is synchronized by the 8284 clock
generator to form READY. This signal is active HIGH. The 8086 READY input is not
synchronized. Correct operation is not guaranteed if the setup and hold times are not met.
CLK (I): Clock

Clock provides the basic timing for the processor and bus controller. It is asymmetric with 33%
duty cycle to provide optimized internal timing. Minimum frequency of 2 MHz is required, since
the design of 8086 processors incorporates dynamic cells. The maximum clock frequencies of
the 8086-4, 8086 and 8086-2 are4MHz, 5MHz and 8MHz respectively.
Since the 8086 does not have on-chip clock generation circuitry, and 8284 clock generator chip
must be connected to the 8086 clock pin. The crystal connected to 8284 must have a frequency 3
times the 8086 internal frequency. The 8284 clock generation chip is used to generate READY,
RESET and CLK.
MN/MX (I): Maximum / Minimum

This pin indicates what mode the processor is to operate in. In minimum mode, the 8086 itself
generates all bus control signals. In maximum mode the three status signals are to be decoded to
generate all the bus control signals.
Minimum Mode Pins The following 8 pins function descriptions are for the 8086 in minimum
mode; MN/ MX = 1. The corresponding 8 pins function descriptions for maximum mode is
explained later.
M/IO (O): Status line

This pin is used to distinguish a memory access or an I/O accesses. When this pin is Low, it
accesses I/O and when high it access memory. M / IO becomes valid in the T4 state preceding a
bus cycle and remains valid until the final T4 of the cycle. M/IO floats to 3 - state OFF during
local bus "hold acknowledge".
WR (O): Write

Indicates that the processor is performing a write memory or write IO cycle, depending on the
state of the M /IOsignal. WR is active for T2, T3 and Tw of any write cycle. It is active LOW,
and floats to 3-state OFF during local bus "hold acknowledge ".
INTA (O): Interrupt Acknowledge

It is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3, and
T4 of each interrupt acknowledge cycle.
ALE (O): Address Latch Enable

ALE is provided by the processor to latch the address into the 8282/8283 address latch. It is an
active high pulse during T1 of any bus cycle. ALE signal is never floated.
DT/ R (O): DATA Transmit/Receive

In minimum mode, 8286/8287 transceiver is used for the data bus. DT/ R is used to control the
direction of data flow through the transceiver. This signal floats to tri-state off during local bus
"hold acknowledge".
DEN (O): Data Enable

It is provided as an output enable for the 8286/8287 in a minimum system which uses the
transceiver. DEN is active LOW during each memory and IO access. It will be low beginning
with T2 until the middle of T4, while for a write cycle, it is active from the beginning of T2 until
the middle of T4. It floats to tri-state off during local bus "hold acknowledge".
HOLD & HLDA (I/O): Hold and Hold Acknowledge

Hold indicates that another master is requesting a local bus "HOLD". To be acknowledged,
HOLD must be active HIGH. The processor receiving the "HOLD " request will issue HLDA
(HIGH) as an acknowledgement in the middle of the T1-clock cycle. Simultaneous with the issue
of HLDA, the processor will float the local bus and control lines. After "HOLD" is detected as
being Low, the processor will lower the HLDA and when the processor needs to run another
cycle, it will again drive the local bus and control lines.
Maximum Mode The following pins function descriptions are for the 8086/8088 systems in

maximum mode (i.e.. MN/MX = 0). Only the pins which are unique to maximum mode are
described below.
S2, S1, S0 (O): Status Pins

These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during T3
or Tw (when ready is inactive). These are used by the 8288 bus controller to generate all memory
and I/O operation) access control signals. Any change by S2, S1, S0 during T4 is used to indicate
the beginning of a bus cycle. These status lines are encoded as shown in table 3.
S2

S1

S0

Characteristics

Interrupt acknowledge

Read I/O port

Write I/O port

Halt

Code access1 0 1 Read memory

Write memory

Passive State

Table 3
QS0, QS1 (O): Queue Status

Queue Status is valid during the clock cycle after which the queue operation is performed. QS0,
QS1 provide status to allow external tracking of the internal 8086 instruction queue. The
condition of queue status is shown in table 4.
Queue status allows external devices like In-circuit Emulators or special instruction set extension
co-processors to track the CPU instruction execution. Since instructions are executed from the
8086 internal queue, the queue status is presented each CPU clock cycle and is not related to the
bus cycle activity. This mechanism allows (1) A processor to detect execution of a ESCAPE
instruction which directs the co- processor to perform a specific task and (2) An in-circuit
Emulator to trap execution of a specific memory location.
QS1

QS1

Characteristics

No operation

First byte of opcode from queue

Empty the queue

Subsequent byte from queue

Table 4
LOCK (O)

It indicates to another system bus master, not to gain control of the system bus while LOCK is
active Low. The LOCK signal is activated by the "LOCK" prefix instruction and remains active
until the completion of the instruction. This signal is active Low and floats to tri-state OFF
during 'hold acknowledge'. Example:
LOCK XCHG reg., Memory ; Register is any register and memory GT0
; is the address of the semaphore.
RQ/GT0 and RQ/GT1 (I/O): Request/Grant

These pins are used by other processors in a multi processor organization. Local bus masters of
other processors force the processor to release the local bus at the end of the processors current
bus cycle. Each pin is bi-directional and has an internal pull up resistors. Hence they may be left
un-connected.