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Implementation Technology:
NMOS and PMOS Transistors,
CMOS logic gates
1
Transistor switches
• Logic circuits are built with transistors
• We will assume a transistor operates as a simple
switch controlled by a logic signal x
• The most popular type of transistor for implementing
a simple switch is the metal oxide semiconductor
field effect transistor (MOSFET)
• Two types of MOSFETs
– N-channel (NMOS)
– P-channel (PMOS)
• Early circuits relied on NMOS or PMOS transistors,
but not both
• Current circuits use both NMOS and PMOS
transistors in a configuration called complementary
MOS (CMOS)
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 13-3
x=“low” x=“high”
Gate
V
G
Source Drain
Substrate (Body) VS VD
2
NMOS transistor as a switch
• The transistor operates by
V = “low” controlling the voltage VG at
G the gate terminal
• If VG is low, there is no
VS VD connection between the
source and the drain
terminals. The transistor is
turned off.
• If VG is high, the transistor is
V = “high” turned on and acts as a
G
closed switch between the
source and drain terminals.
VS VD
x=“high” x=“low”
Gate
VG
Drain Source
V
Substrate (Body) DD VS VD
3
PMOS transistor as a switch
• The transistor operates by
VG = “high” controlling the voltage VG at
the gate terminal
• If VG is high, there is no
VS VD connection between the
source and the drain
terminals. The transistor is
turned off.
• If VG is low, the transistor is
VG = “low” turned on and acts as a
closed switch between the
source and drain terminals.
VS VD
NMOS transistor V
G
VS = 0 V
Closed switch Open switch
when VG=VDD when VG=0V
VS=VDD VDD VDD
PMOS transistor VG
VD=VDD
VD Open switch Closed switch
when VG=VDD when VG=0V
4
NMOS and PMOS in logic circuits
• When the NMOS transistor is turned on, its
drain is pulled down to Gnd
• When the PMOS transistor is turned on, its
drain is pulled up to VDD
• Because of the way transistors operate:
– An NMOS transistor cannot be used to pull its
drain terminal completely up to VDD
– A PMOS transistor cannot be used to pull its drain
terminal completely down to Gnd
• Therefore, NMOS and PMOS transistors are
commonly used in pairs in CMOS circuits
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 13-9
5
CMOS logic gates
• For any given valuation VDD
of the input signals,
either the PDN pulls Vf
Pull-up network
down to Gnd or the PUN (PUN)
pulls Vf up to VDD PMOS transistors
Vf
T1 V DD V DD
Vx Vf
T2
0 1 1 0
x T1 T2 f
0 On Off 1
1 Off On 0
2 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 13-12
6
CMOS NAND gate
VDD
T1 T2 X1 X2 T1 T2 T3 T4 f
0 0 On On Off Off 1
Vf
0 1 On Off Off On 1
VX1 T3
1 0 Off On On Off 1
1 1 Off Off On On 0
VX2 T4
4 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 13-13
VDD
T1 X1 X2 T1 T2 T3 T4 f
VX1
0 0 On On Off Off 1
Vf 1 0 Off On On Off 0
T3 T4 1 1 Off Off On On 0
4 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 13-14
7
CMOS AND gate
VDD VDD
T1 T2
Vf
VX1 T3
VX2 T4
6 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 13-15
CMOS OR gate
VDD VDD
VX1 T1
VX2 T2
Vf
T3 T4
6 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 13-16
8
CMOS non-inverting buffer
VDD
x f Vx Vf
f=x
A non-inverting buffer
4 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 13-17
s’
s’
s f
x f x f 0 Z
1 x
s
s
2 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 13-18
9
CMOS tri-state buffer
e e
x f x f
e x f
0 0 Z
0 1 Z
1 0 0
1 1 1
8 transistors
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 13-19
10