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I. I NTRODUCTION
Manuscript received October 27, 2013; revised March 23, 2014 and
June 15, 2014; accepted July 21, 2014. Date of publication August 26,
2014; date of current version January 7, 2015.
The authors are with the Department of Computer Engineering,
Sharif University of Technology, Tehran 11365-11155, Iran (e-mail:
mohammad_salehi@ce.sharif.edu; ejlali@sharif.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2014.2352215
In dealing with todays highly competitive embedded systems markets and time-to-market pressure and in order to
deliver correct-the-first-time products with multiple system requirements, the use of commercial off-the-shelf (COTS) devices [3], [5][7] is very beneficial in designing embedded
systems. Some vendors offer reconfigurable hardware solutions to accelerate the design process and provide a variety of
programmable logic device (PLD)-based evaluation kits (e.g.,
Xilinx [8] and many others). However, instead of focusing
on embedded systems, these platforms allow to functionally
test the SOC or ASIC devices to be produced. Embedded
systems usually consist of a microcontroller that contains a
microprocessor integrated with memory elements and peripherals in a single chip [4][7]. Reference [5] has reported a
laboratory activity on a microcontroller-based platform. Reference [25] has presented a prototyping platform for ARM-based
embedded systems. However, these platforms do not provide
facilities to experiment with energy management techniques.
Reference [23] has presented a platform for dynamic voltage
and frequency scaling (DVFS) [11] in an ARM-based processor. However, this work exploits DVFS only for the processor
(and not for the other parts, e.g., phase-locked loop (PLL),
memory, and I/O).
In this paper, to meet the design requirements of multiobjective embedded systems, we propose a hardware platform
for experimenting with energy management techniques (i.e.,
dynamic power management (DPM) [12] and DVFS) (see
Section III) and fault-tolerance techniques (see Section VI).
Compared with previous related works (that proposed platforms for embedded systems), our platform:
1) provides DVFS capability for the microcontrollers, including not only the processor cores but also PLL, memory, and I/O; it should be noted that many existing designs
either do not have DVFS or apply DVFS only to processor
cores [11], [13], [14], [23], whereas our study in this
paper (see Section V) shows that applying DVFS to PLL,
memory, and I/O is quite effective;
2) includes circuitry to accurately and separately measure
energy/power consumption of different parts of the microcontroller, including the processor core, PLL, memory, and I/O; this provides the ability to determine the
most energy-consuming part for a given application;
3) is general and based on an ARM-based COTS microcontroller; hence, it can be used for a wide range of
existing microcontrollers (e.g., [13], [14], and [18][20])
and many other COTS devices.
0278-0046 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
SALEHI AND EJLALI: HARDWARE PLATFORM TO EVALUATE EMBEDDED SYSTEMS BASED ON COTS DEVICES
Fig. 1.
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and its supply voltage that can vary in an allowed range can be
similarly used in our design.
A. Architecture Overview
Our design of the ARM7-based platform is founded on a
member of AT91SAM7x series of microcontrollers [9]. The
architecture of the microcontroller series is shown in Fig. 1.
The microcontroller is composed of an ARM7 processor core,
a system controller, memory elements, and peripheral devices. Most of ARM7-based microcontrollers adopt a similar architecture, e.g., [18][20]. As shown in Fig. 1, the
microcontroller consists of Flash, ROM, and SRAM internal
memory devices connected via the memory controller, and a
wide range of peripherals, including universal synchronous/
asynchronous receivertransmitter (USART), serial peripheral
interface (SPI), analog-to-digital converter (ADC), universal
serial bus (USB), Ethernet medium access control, controller
area network (CAN), two-wire interface (TWI), synchronous
serial controller (SSC), real-time timer (RTT), and pulsewidthmodulation controller (PWMC). Most I/O lines of the peripherals are multiplexed with the parallel I/O (PIO) controller. Each
PIO line may be assigned to a peripheral or used as generalpurpose I/O. These features provide flexibility to designers and
assure effective use of the components.
B. Platform Architecture
The architecture and physical implementation of the
hardware platform are shown in Fig. 2(a) and (b), respectively.
The platform contains two AT91SAM7x256 microcontrollers
connected via a bus. Based on the facilities provided by
AT91SAM7x series, this bus can be easily configured as SPI,
UART, CAN, or a 16-bit parallel bus. AT91SAM7x256 contains
an ARM7TDMI processor with in-circuit emulation (ICE),
debug communication channel support, 64-KB internal SRAM,
and 256-KB internal Flash memory. Two controllable power
supplies are included in the board to provide power to the peripherals and the processor core of each of the microcontrollers.
The power supplies receive commands from the processors and
control the power applied to each part of the microcontrollers
(see Section III-B). The use of separate supply voltages not only
helps conduct experiments with various DVFS schemes (where
different supply voltages can be applied to each processor
separately) but also can be used to shut off one processor
to switch into a single-processor configuration. We have also
provided the flexibility to users in choosing arbitrary DVFS or
DPM schemes. The platform also is equipped with circuitry
to measure the current drawn by the processor cores, PLLs,
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Fig. 2.
Fig. 3. Power management unit. (a) Clock generator. (b) Power management controller [9].
TABLE I
P OWER M ANAGEMENT T ECHNIQUES IN AT91SAM7 X
(1)
SALEHI AND EJLALI: HARDWARE PLATFORM TO EVALUATE EMBEDDED SYSTEMS BASED ON COTS DEVICES
1265
TABLE II
P OWER R EQUIREMENTS IN AT91SAM7 X
Fig. 5.
Fig. 4. Power supply setup. (a) Typical power supply. (b) Proposed
controllable power supply.
voltage for the VCORE and VPLL pins. As Table II shows, the
USB transceiver, Flash memory, and I/O lines power supply can
range from 3.0 to 3.6 V, and in addition, the processor core and
PLL power supply can range from 1.65 to 1.95 V. This provides
the possibility for the device to vary the supply voltage rather
than using just a single fixed voltage.
To provide voltage scaling capability for this device, the
dc/dc converter and embedded voltage regulator in Fig. 4(a) is
replaced with a controllable power supply in Fig. 4(b) to feed
the power pins with variable voltages. As shown in Fig. 4(b),
variable supply voltage is provided for the power inputs of the
microcontroller, except the embedded voltage regulator input,
which remains unconnected, to disable the internal voltage
regulator. The schematic of the proposed controllable power
supply to provide dynamically scalable power supply is shown
in Fig. 5. In this architecture, an adjustable version of a lowdropout linear voltage regulator (e.g., LM1117) is used. This
regulator can provide an output voltage from 1.25 to 13.8 V
with exploiting only two external resistors (i.e., Rref and Radj
in Fig. 5). This device makes a 1.25-V reference voltage Vref
between the output Vout and the adjust pin. As shown in Fig. 5,
this voltage is applied across the resistor Rref to produce a
constant current that flows through the adjustment resistor Radj
and fixes the output voltage Vout to the desired level as
Radj
(2)
Vout = VREF 1 +
+ Iadj Radj .
Rref
Based on (2), to set Vout to a new voltage level, we need to
change the adjustment resistor Radj . To provide the capability
of dynamically adjusting the resistor, a digital potentiometer
(e.g., AD8403) is used to provide a digitally controlled variable resistor that performs the same adjustment function as
a potentiometer or variable resistor. As we aim at controlling the voltage of the four power pins of AT91SAM7x256
[see Fig. 4(a)], a digital potentiometer, which includes four
independent variable resistors, is used. Each resistor can
be set separately by a digital code transferred into the device. The code is loaded into the device via the standard threewire SPI digital interface. The data bits clocked into the device
are decoded to determine the resistor and its value.
In summary, to dynamically scale the supply voltage of a
power pin of the microcontroller at run time, a digital code
indicating the resistor and its desired value is loaded by the
microcontroller into the digital potentiometer; after changing
the adjustment resistor, the voltage regulators output is scaled
and set to the desired voltage value. Therefore, by the use of
the proposed architecture, at run time, the microcontroller can
dynamically set the voltage of the peripherals and the processor
core power pins. Generally, the proposed technique can be used
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N1 /fmax + N2 /fmax
.
S
(3)
N1 /fmax
S
fDP,2 =
N2 /fmax
.
S
(4)
Fig. 7.
Fig. 8.
Similarly, the minimum energy consumption of the dualprocessor system can be written as (VDP,1 and VDP,2 are the
minimum voltages that allow fDP,1 and fDP,2 , respectively)
VDP,1
2
+ Ce VDP,1
N1
EDP = ILeakage
fDP,1
VDP,2
2
+ ILeakage
+ Ce VDP,2
N2 . (6)
fDP,2
In (3) and (4), it is shown that fDP,1 < fSP and fDP,2 < fSP
(for N1 and N2 = 0). Therefore, the minimum voltages that are
used in the dual-processor system can be less than the minimum
voltage that is used in the single-processor system. Therefore,
we have VDP,1 < VSP and VDP,2 < VSP . In addition, assuming
an almost linear relationship between the voltage and frequency [1], [3], [11], we can write VSP /fSP VDP,1 /fDP,1
VDP,2 /fDP,2 . Therefore, from (5) and (6), it can be concluded
that EDP < ESP . This means that when DVFS is used in
executing parallel tasks, a dual-processor system could provide
more energy saving compared with a single-processor system.
IV. P OWER M EASUREMENT, D EBUG , AND T EST U NITS
A. Power Measurement Unit
To provide power measurement equipment to the platform, a
resistor is placed between each microcontroller power pin and
the power supply line, and the voltage drop across the resistor is
measured. The measured value gives the current drawn by the
power pin. The power measurement setup is shown in Fig. 7.
As the current drawn by the power pins of the microcontroller
is less than 100 mA and this value cannot be digitized by the
ADC of microcontrollers, the voltage value is amplified using
an operational amplifier. The amplified value is digitized by a
10-bit ADC, and the data are sent to the host computer.
B. Debug Units
The AT91SAM7x microcontrollers have a number of debug
and test features, shown as a block diagram in Fig. 8. The
UART debug unit provides a two-pin (i.e., TXD and RXD)
UART interface that can be employed for various purposes, e.g.,
debug, trace the running application, and upload an application
into internal SRAM. A general JTAG/ICE (see [9]) port is
employed for commonly used operations, such as loading program code, and for standard debugging functions, such as single
stepping through programs. IEEE 1149.1 JTAG Boundary Scan
SALEHI AND EJLALI: HARDWARE PLATFORM TO EVALUATE EMBEDDED SYSTEMS BASED ON COTS DEVICES
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TABLE III
P OWER S UPPLY R EQUIREMENTS FOR S OME
W IDELY U SED M ICROCONTROLLERS
Fig. 10. High-to-low and low-to-high voltage scaling delays. (a) I/O.
(b) Processor. Coupling: ac.
memory voltages could be any value from the set {3.0, 3.1, 3.2,
3.3, 3.4, 3.5, and 3.6 V}. Like the works [1], [11], and [23], we
have a set of voltagefrequency pairs to perform DVFS. Each
voltage has a corresponding frequency level, and hence, there
are seven levels, i.e., {36, 40, 45, 51, 55, 58, and 61 MHz}.
The corresponding frequency for each voltage was empirically
determined by measuring the highest frequency at which the
processor still worked correctly and then subtracting 5% safety
margin (similar to [23]). It should be noted that this measurement is carried out only once (by the board development team)
and the end users just use the provided set and they do not
need to repeat such measurements (although they can do it if
they require). Although we provided only seven different levels
of voltage, the platform can provide 256 voltage levels. As
an example to show how the four voltages can independently
vary, Fig. 9(b) shows the voltage of the processor and I/O when
switching, respectively, between 1.75, 1.8 and 1.85 V, and 3.2,
3.3 and 3.4 V.
We conducted a set of experiments to analyze the voltage
scaling delay in the proposed platform. For example, Fig. 10
shows a timing diagram of voltage scaling between two consecutive voltage levels, i.e., 1.75 and 1.8 V for the processor core
and 3.2 and 3.3 V for I/O. In Fig. 10, the high-to-low voltage
scaling delay is 34 and 118 s, and the low-to-high voltage
scaling delay is 23 and 55 s for the processor core and I/O,
respectively. In our experiments, we obtained almost the same
result for the other voltage levels. An interesting observation
from these experiments is that the high-to-low voltage scaling
delay is greater than the low-to-high voltage scaling delay (i.e.,
about 45% for the processor core and PLL and about 110%
for memory and I/O). To analyze the power consumption of
different parts of the microcontroller (including the processor
core, PLL, memory, and I/O) when working on different voltage
levels, we executed a matrix multiplication task on the Keil
RTX operating system [27]. This task multiplies two randomly
generated matrices and sends the result to the host computer via
USB. Based on the power consumption results that are shown
in Fig. 11, for all the parts, lower supply voltage leads to lower
power consumption. In addition, Fig. 11 shows that voltage
scaling is very effective in reducing the power consumption of
both the processor and the other parts of the microcontroller.
Another set of experiments has been performed on the
MiBench benchmarks [21] (as real applications) to determine
the contribution of each part of the microcontroller in the total
power consumption, execution time, and energy consumption.
The results are shown in Fig. 12. In this experiment, the 1.8-V
voltage is used for the processor and PLL, and the 3.3-V
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TABLE IV
E NERGY C ONSUMPTION ( IN M ILLIJOULES ) OF DPM, CVFS, AND MVFS
Fig. 12. Contribution of parts of AT91SAM7x in: (a) power consumption, (b) execution time, and (c) energy consumption.
voltage is used for memory and I/O. As PLL is always operational during the application execution, it is not included
in Fig. 12(b), and when we calculate energy consumption [in
Fig. 12(c)], applications execution time is considered for PLL.
From Fig. 12, we make two main observations: 1) Although the
power consumption of PLL, memory, and I/O is less than that
of the processor, they have energy consumption comparable
with that of the processor; 2) although PLL has a very small
contribution in the total power, as it is always operational, its
energy consumption is comparable in most cases with that of
the others.
To evaluate the effectiveness of applying voltage scaling
on the whole microcontroller, we measured and compared the
energy consumption of the microcontroller when using three
types of energy management techniques.
1) DPM: When there is an idle time, the microcontroller
enters the low-power mode, which is provided by the
microcontroller [9], as: memory is standby (is not accessed at all), processor core is idle (its clock is switched
off), main clock = 500 Hz, and all peripheral clocks are
deactivated.
2) Core voltage and frequency scaling (CVFS): DVFS is
used only for the processor core, and DPM is used for
the other parts. In this case, the processor frequency is set
to the slowest frequency (and its corresponding voltage)
necessary to finish the application, selected from the set
of available voltagefrequency pairs.
3) Microcontroller voltage and frequency scaling (MVFS):
DVFS is used for the whole microcontroller, including
the processor core, PLL, memory, and I/O.
In this experiment, we analyzed the MiBench benchmarks,
and the results are shown in Table IV. This experiment shows
that, for the applications in this experiment, using MVFS results
in energy savings in average of about 35% and 11% (at least
31% and 10%), as compared with the sole use of DPM and to
TABLE V
E NERGY C ONSUMPTION ( IN M ILLIJOULES ) FOR E XECUTING THE
D UPLICATION T ECHNIQUE ON A S INGLE P ROCESSOR
OR ON T WO P ROCESSORS
SALEHI AND EJLALI: HARDWARE PLATFORM TO EVALUATE EMBEDDED SYSTEMS BASED ON COTS DEVICES
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