Abstract- This work generic purpose solution of highly power efficient adaptive bias pole zero

cancellation circuit are proposed. ,which is suitable for analog baseband with wide bandwidth
range (MHz to 100 Hz) by using a standard 0.18 m process to demonstrate versatile solution.
Gain is 30to35 db. by using push-pull opamp with adaptive biased and pole cancellation pushpull source follower technology.[1]
The pervious approach becomes cmos 0.35 m cmos
technology with 3v supply output current derive capability for large input voltage restricted by
using these technology the buffer slew rate to increase by more than 100% [2] Implemented in
AMS 0.6 cmos process . the micro graph of the current mirror amplifier with the current
detection SRE circuit occupies less then 25% of the total chip area of amplifier .[3] A High slew
rate low power rail buffer amplifier which is suitable for thin film liquid transistor Liquid
crystal display date driver application is proposed . previous dynamic approach becomes buffer
amplifier was fabricate in a 035m cmos Technology with 303 v supply [4]

CHAPTER 1
INTRODUCTION
An operational amplifier (op-amp) is a DC-coupled high-gain electronic voltage amplifier with
a differential input and, usually, a single-ended output.[1]In this configuration, an op-amp
produces an output potential (relative to circuit ground) that is typically hundreds of thousands of
times larger than the potential difference between its input terminals.
Operational amplifiers had their origins in analog computers, where they were used to do
mathematical operations in many linear, non-linear and frequency-dependent circuits.
Characteristics of a circuit using an op-amp are set by external components with little
dependence on temperature changes or manufacturing variations in the op-amp itself, which
makes op-amps popular building blocks for circuit design.
Op-amps are among the most widely used electronic devices today, being used in a vast array of
consumer, industrial, and scientific devices. Many standard IC op-amps cost only a few cents in

moderate production volume; however some integrated or hybrid operational amplifiers with
special performance specifications may cost over $100 US in small quantities.[3] Op-amps may
be packaged as components, or used as elements of more complex integrated circuits.
The op-amp is one type of differential amplifier. Other types of differential amplifier include
the fully differential amplifier the instrumentation amplifier the isolation amplifier and negative
feedback amplifier.

The circuit symbol for an op-amp is shown below

Fig (1)

Circuit Notation

V+: non-inverting input

V: inverting input

Vout: output

VS+: positive power supply

VS: negative power supply

The power supply pins (VS+ and VS) can be labeled in different ways (See IC power supply pins).
Often these pins are left out of the diagram for clarity, and the power configuration is described
or assumed from the circuit.

Input Offset Voltage (Vio)

If no external input signal is applied to the op-amp at the inverting and non-inverting input
terminals the output must be zero. That is, if Vi = 0, V0 = 0. But as a result of the given biasing
supply voltages, +Vcc and Vcc, a finite bias current is drawn by the op-amp, and as a result of
unsymmetry on the differential amplifier configuration, the output will not be zero. This is
known as offset. Since V0 must be zero when Vi = 0, the input-signal must be applied such that
the output offset is cancelled and V0 is made zero. This is known asinput offset voltage. It is the
voltage that must be applied between the two input terminals of an op-amp to nullify
output. Vio = 0 V. Practical value

100 V (typical).

Input Offset Current (Iio)

Though for an ideal op-amp, the input impedance is , it is not so practically. So the IC
draws current from the source of the voltage, however small it may be.
The algebraic difference between the currents into the inverting and non-inverting terminals is
referred to as input offset current Iio.
Iio = |IB1 IB2|

Output Bias Current (IB)

This is the average of the currents that flow into the inverting and non-inverting input terminals
of the op-amp
For an ideal op-amp IB = 0 Amps
For a practical op-amp IB = 500 nA
For a precision op-amp, IB is typically 10 nA.

Input Resistance (Ri)

This is the equivalent resistance of the IC measured at either the inverting or non-inverting
input terminal, with the other terminal connected to the ground.
Ideal value = , Practical value = 2 M
For JFET op-amps, typical value of Rt is 1012.
Input Capacitance (Ci)
This is the equivalent capacitance, Ci, that can be measured at either the inverting or noninverting terminal, with the other terminal connected to the ground.
Ideal value of Ci = 0 pf, Practical value = 1.5 pf
Due to change in the Q point of the biasing circuits in the internal circuits of an op-amp., the
input offset voltage and input offset current Iio parameters, change with temperature. The
term drift is used to indicate the same.
Input Offset Voltage Drift [Vio(drift)]
This is the rate of change of Vio with temperature (T).

Input Offset Current Drift [Iio(drift)]

This is the rate of change of Iio with temperature (T).

Common Mode Rejection Ratio [CMRR ()]

This parameter indicates the capability of the op-amp to reject noise. The higher the value of
mode) CMRR, the better it is.
CMRR is defined as the ratio of the differential voltage gain, Ad, to the common mode voltage
gain, Acm. (cm = common mode).
The op-amp has a differential voltage amplifier configuration. Ad is usually large. Acm is small.
Hence, the value of CMRR is large. CMRR is expressed in decibels.
In the differential amplifier configuration, the noise signals which are common to the two inputs
of the differential amplifier will also get amplified. If the common mode gain of the amplifier is
less, then the noise will not get amplified, but will be altered. So only the differential input will
be amplified and the output V0 will have less noise. This is the advantage of the differential
amplifier which is used in op-amps. Thus, the CMRR value is high.
Ideal value = , Practical value = 90 db
The CMRR value is determined under test conditions with Rs = 10 k.
Power Supply Rejection Ratio (PSRR)
The input offset voltage Vio of the op-amp changes if the bias power supply of the op-amp.
changes. The change of Vio with + Vcc or Vcc is called the power supply rejection ratio. The term
is also called the Supply Voltage Rejection Ratio (SVRR) or Power Supply Sensitivity (PSS).
PSRR is defined as the ratio of change in the input offset voltage Vio with a change in one of the
bias power supplying Vcc, when the other power supply is held constant.
This is the bandwidth of the op-amp when the voltage gain is 1 (unity).

As the frequency increases, the gain decreases because as f increases, decreases. So ZL also
decreases. Hence, V0 = IL ZL also decreases. So the gain Avdecreases. The gain BW product
indicates the capability of the op-amp to amplify the input signals of larger frequency.
The other terms used to describe Av. BW are closed loop bandwidth, unity gain bandwidth.

Slew Rate (SR)

This is defined as the maximum rate of change of output voltage per unit time.The Slew rate is
dynamic parameter of the Op-AMP is define as the propagation delay time in comparators
generally varies as a function of the amplitude of the input. A large Input will results in a smaller
delay time. There is an upper limit at which a further increase in the input voltage will no large
effect the delay this mode of operation is called slewing or slew rate. Means maximum output
change with respect to the time in s.

slew rate=

dVout
dt

CHAPTER 2
Literature Survey

A Compact rail-to-rail class AB amplifier buffer slew Rate Enhancement

In this section to drive a large capacitive load an analog buffer implemented by a

transconductance amplifier gm connected in negative feedback as shown in fig (a) is the most
fundamental and widely used driving scheme are LCD driver, low dropout regulators and analog
testing and signal monitoring . and the Class AB buffer are used for the purpose of high power
efficiency and low harmonic distortion.

Fig (2)

(A) Rail -To-Rail analog buffers :

Fig (c) and (d) show the DFVF transconduction have been used as the basic circuit cell in the
buffer designs [a] and their CMR limitations. refer fig( b) after settling. In rail-to rail buffer the
minimum and maximum CM voltage can be derived using the square-law function of the MOS
transistor in the strong inversion saturation. Region since transistor M 1 and M2 have the same
gate source voltages (Vgs) neglecting channel length modulation they conduct the same drain
current Id1.

V CMmin=Vss+ Vtn+

2 I B1 I
I B1
+
3
1,2

V CMmax(c)=V SS+ 2V tn +

2 I B1
3

Where V tn and i represent the threshold voltage of an N mos device and the process
transconductance of each device respectively.

(B) Compact adaptive Biasing:In the fig [2] a M3 and M10 directly connected to output terminal. Now the adaptive
mechanism for each DFVF transconductor is handled single transistor. When Vin goes
high and condition is met, all transistors of the lower part will be cut off And upper part goes
low condition and these part shut down. this alteration yield a rail-to-rail operation with a more
compact design and less power consumption, while similar settling and slew rate performances.
In slew rate enhancement scheme for rail-to-rail class-AB CMOS buffer increase the slew rate
more than 100% with only a small increase in static power consumption and silicon area. With
same harmonic distortion ,bandwidth , and offset to the other buffer.

Fig (3) Compact adaptive Bias circuit

Measured dc transfer characteristics of the buffers. The input signal is

also shown. For clarity, the line graphs are offset by 250 mV.

(B)Design of low power analog Drivers based on slew rate Enhancement

Circuits for CMOS Lo power regulator:Low power dropout linear regulator are widely used in the portable battery powered device as
LDOs can convert decaying battery voltages to low noise and accurate voltage for noise sensitive
system. Since integrated CMOS LDOs only occupy small chip area. in [2] also adopted to power
up sub blocks of a system individually in the system on a chip designs in order to tackle the the
crosstalk problem reduce , both board space and external pins can be minimized. by design of
high performance CMOS LDO is necessary.
The new current efficient analog driver for the CMOS LDO is implemented by a single stage
non inverting unity gain configuration with an embedded enhancement circuit as shown in fig the
operating principle, systematic design method and circuit implementation of the current detection
SRE discussed in[3].in analog driver the open loop low frequency gain of the core amplifier is
over 70 db. With the unite gain feedback configuration, the output resistance of the analog driver
is reduce by its open loop gain .the parasitic pole at the gate driver of the power transistor is then
shifted to a higher frequency, thereby improving the loop gain bandwidth of the LDO. The load
transient response of the LDOs is originally limited by the slew rate at the gate driver of the
power transistor by the embedded SRE circuit analog driver [3]. The SRE circuit provide the
dynamic current to charge and discharge capacitor of the power transistor during transient and
completely turned off in the static state. Consequently the quiescent current of the analog driver
is minimized while the slew rate at the gate drive can still be enhanced. the SRE circuit consist of
a sensing and driving circuit from the previous research work.

(B)

Current deduction SRE circuits:-

The current detection SRE circuit for the current mirror amplifier, are shown in fig. in which
transistor Ma1 and Ma2 represent the active load of the current mirror amplifier Md1 and Md3
are sensing transistors and transistor Md4 and Md6 Mp and Mn from the driving circuit. Md4,
Md5 and Mp are responsible for charging the capacitive load while Md2,Md6 and Mn are

responsible for discharging the load. in this section transistor Md4 and Md and Md5 operate in
saturation region their drain current equal to I1 and I2 .
When the amplifier is connected in unity gain feedback configuration a positive input voltage
step at the main amplifier leads to an increase in I in and I2. When I2 is greater than I1 the
voltge at node n1 decrease and cause Mp to be heavily turned on. As result a large dynamic
current is produced to charge up the lode capacitance. When the output voltage reaches
approximately the final value.

Response time of SRE circuit :The response time of the SRE circuit is determined by the time required to turn on or turn
Off the drive transistor Mp and Mn when a signal is applied at the input of the main Amplifier.
It is noted that the minimum signal amplitude to trigger the SER circuit is v.During the positive
output slewing transistor Md4 is in the saturation region and provides A constant current to
discharge the parasitic capacitor. Therefore the response time
t resp,n and t resp,p of the SER circuit for positive and negative slewing periods is
Approximately given by
th, mpV ov, md 4
V CP1

t res, p =
th , mnV ov ,md 6
V C P2

t res. n=

(for positive slewing)

(for negative slewing)

Where gm is the tranconductance of the input differential pair of the main amplifier, Vov is
The overdrive voltage of MOS transistor and b1,b2 are transistor ratios, the transistor are
given by following equations

W
(
L)
b=
( WL )

Md 5

Md 3

and

W
(
L)
b=
( WL )

Md 2

Ma2

By above (positive slewing) and (negative slewing) equation increases with the value of
Cp1 and Cp2. Increasing the size of transistor Mp and Mn thus slows down the response
time of the SRE circuit.

(D)Adaptive biased pole cancellation

In source follower one problem are generate because source follower work in linear mde
means other parameter varies linearly. So reduce that problem by using another technology that
technology is known as adaptive pole cancellation .according to the basic principle of the
propose APP-SF we construct three different types of the APP-SF ,as The schematic of the
adaptive bias circuit for the adaptive biased pole-cancellation push-pull source follower [1]

Fig (4) Adaptive biased pole cancellation Circuit diagram without op-amp

Fig (5) Adaptive biased pole cancellation circuit with op-amp

Table of Literature Survey

Parameter
[1]
Technolog 0.18
y
m
CMO
S
Power
4.1
(mw)
Bandwidth 240(MHz)
500
Area (mm 0.23
2)
Slew rate NA
(s)

[2]
0.35
m
CMO
S
-

[3]
[4]
0.6
m 0.35
CMOS
m
CMO
S
-

5.8

57

0.014

0.027

81

Power
supply
(Volt)

1.5/1.73
2.75
Cl=470 Pf,
0.7/0.81C
L =1nF
3
3.3

1.8

60480

CHAPTER 3
Proposed Identification
Parameter
Technology

[1]
0.18 m
CMOS

[2]
0.35 m
CMOS

[3]
0.6
m
CMOS

[4]
0.35 m
CMOS

Proposed
0.18 m
CMOS

Power (mw)
Bandwidth
(MHz)
Area (mm 2)
Slew rate (s)

4.1
240-500

5.8

57

60-480

Increase

0.23
NA

0.014
81

2.75

Increase

Power supply
(Volt)

1.8

0.027
>1.5/1.73
Cl=470 Pf,
0.7/0.81CL
=1nF
3

3.3

Implementation Time Chart

(start from According to session of III Semester)
Example below

MONTH (S)
July, 2013
August, 2013
September, 2013

WORK
cided to be in OP-AMP
Topic Extended to CMOS OP-AMP
Publications studied specific to decided topic;

October, 2013
Exact area of work identified in the broad fields of
Design of low power high gain broad band op-

amp CMOS amplifier.

November, 2013

Review paper prepared.

December, 2013

Review paper prepared

March, 2013

Proposed time of circuit implementation

completion

April, 2013

Proposed time of validation completion

May, 2013

Final submission

REFERENCE:[1] Le Ye ,Congyin Shi ,Huailin Liao, Ru Huang, Yangyuan Wang A high power efficient active
RC- filters with wide bandwith-range using puss-pull opamp,in IEEE Transaction on circuit and
system, January 2013.
[2] Chutham Sawigun,Andreas Demosthenous, xiao Liu and Woutre A. Serdijn . A Compact railto-rail class AB CMOS buffer with slew rate Enhancement. In IEEE Transaction on circuit and
systems, august 2012.
[3] Hoi Lee, Philip K.T Mok and Ka Nang Leung A Design of low power analog drivers based
on slew rate enhancement circuit for CMOS low dropout regulators, In IEEE transaction on
circuit system, September 2005.
[4] J.S Kim , J.Y Lee and B.D Choi, A slew rate enhanced rail-to-rail buffer amplifier for TFT
LCD data Drivers. In ELECTRONICS LETTERS july 2012.