A 25-31 GHz Positive Slope Gain LNA with

Propesed Noise Figure Reduction Technique

Esref Turkmen
Sabanci University, Faculty of Engineering and Natural Sciences FENS,
Orhanli Tuzla, 34956 Istanbul, Turkey
turkmenesref@sabanciuniv.edu

AbstractThis work presents the design of a 25-31 GHz

positive slope gain low noise amplifier (LNA) with proposed noise
figure reduction technique. The achieved positive slope gain is
from 12.2 dB to 21.5 dB on bandwidth from 25 to 31 GHz. The
slope of the gain is about 1.5dB/GHz. The gain value is 17.4 dB at
the center frequency 28 GHz. The input 1 dB compression point
(I-P1dB) is -12.7 dB at the center frequency 28 GHz. The total
power consumption is 9.04 mW. S11 and S22 are less than -10 dB
at the whole operating frequency (25-31 GHz). The noise figure is
2.88 dB at 28 GHz.

using of a high-pass filter at the inter-stage causes dramatically

increased noise figure because of decreasing gain of the first
stage. The Friiss equation (1) presents the effect of the first
stage gain on noise performance, where is noise factor of the
first stage,
is noise factor of the second stage and
is the
gain of the first stage [1]. These problems can be solved by
using topologies which have more than two stage but the
multistage topologies suffer from oscillation problems.
(1)

Keywords positive slope gain, low noise amplifier (LNA),

noise reduction.

I. INTRODUCTION
This paper presents the design of a 25-31 GHz positive
slope gain low noise amplifier (LNA) with proposed noise
figure reduction technique. The proposed noise figure
reduction technique reduces the noise figure of the designed
LNA from 3.17 dB to 2.88 dB at 28 GHz. The desired
specifications were determined by considering the potential
requirements of a 5G mobile device. So, the power
consumption should be as small as possible while still
providing the competitor noise and gain performance.
Therefore, the designed LNA circuit should meet the following
specifications: less than 10 mW power consumption, more than
15 dB gain at the center frequency 28 GHz, less than 3 dB
noise figure, better than 10 dB matching bandwidth from 25
GHz to 31 GHz at both of input and output.
This paper is organized as follows. Section II is mainly
focused on the topology selection, technology information,
basic formulations, hand calculations, first and second stages
designs, layout and optimizations. Section III presents the
simulation results and comparison to other similar studies.
Finally, Section IV is conclusion.
II. DESIGN METHODOLOGY
A. Topology
There are two solutions to obtain positive slope gain. First
solution includes a high-pass filter which can be used at the
inter-stages or output of the LNA. If the high-pass filter is used
at the output of the LNA, there will be a limitation to realize
wideband impedance matching at the output. Because, the most
of the high-pass lumped element filter topologies only provide
narrow-band impedance matching. However, there are also
high-pass lumped element filters which can provide wideband
impedance matching. In the two stage LNA topologies, the

In addition to the using of a high-pass filter, the positive

slope gain can be obtained by shaping the gains of each stage.
In this study, two cascode stages were used to achieve high
gain and better stability. The positive slope gain was obtained
by shaping the gains of each two stage. Figure 1 shows the
schematic of the designed LNA.

Fig. 1. Schematic of the designed LNA

B. Proposed Technique To Reduce Minimum Noise Figure of
the Cascode Configuration
As can be seen from Fig. 1, there is a shunt inductor (Ln)
between the driver and the load transistor to improve noise
performance of the cascode structure. Cn is only used as DCBlocking. The noise figure of the cascode structure can be
analyzed by Friiss equation (1). The load transistor has an
optimum source impedance to provide its minimum noise
figure performance. Therefore, the shunt inductor is used to
manipulate the impedance value seen by the emitter of the load
transistor. There is an optimum inductor value to reduce
minimum noise figure of the cascode configuration because the

low inductor values causes the signal loss to ground. It means

that the gain of the driver transistor is decreasing and the noise
figure of the cascode configuration is increasing. The
mathematical analysis of this technique will be investigated by
using Friiss equation and noise model of heterojunction
bipolar transistor.
C. Technology
In this study, a 0.25-m SiGe BiCMOS technology
developed by IHP-Microelectronics, SG25H3, was used to
design the LNA. This technology offers three different
heterojunction
bipolar
transistors:
high-performance
(npnH3PI), medium voltage (npnH3MV) and high voltage
(npnH3HV). The high voltage transistor cannot be used at this
work because of its maximum transit frequency, 25 GHz. In
this study, only the high performance transistor with 2.1 V
common emitter breakdown voltage and peak value ft/fmax of
110/180 GHz was used to achieve the desired specifications
because of its noise and gain performance at the operating
frequency range. The back-end of the technology has three thin
aluminum layers and two thick metal layers for high quality on
chip inductor.
D. First Stage Design
The gain and noise performance of the first cascode stage
should be carefully investigated to achieve a good noise
performance in the two-stage LNA topologies. The effect of
the gain and noise performance of the first cascode stage is
presented by Friiss equation (1). The optimum bias point
which provides a minimum noise figure with enough gain
performance is required to obtain a LNA design with minimum
noise performance.
The noise figure of the cascode structure is largely
controlled by the noise figure of the common emitter transistor.
Minimum noise figure of the common emitter HBT device is
given by [2]

(2)

where is the operating frequency,

is the unity current gain
frequency, and are the base and emitter ohmic resistances,
is the current gain, is the collector current density. As
can be seen from (2), the collector current density
is the
main parameter which can be manipulated. The collector
current density is the function of the base-emitter voltage
(VBE) and independent from the size or number of the
transistor. So, first step is to determine the optimum baseemitter voltage of the common emitter transistor and VBE is
chosen as 0.84 V.
Noise figure of a two port network is given by (3), where
is the noise matching source resistance,
is the
minimum noise figure and
is the noise resistance. The
impedance of the input port of the LNA is constant and 50 .
The optimum source resistance (
) should be set equal to
50 to achieve the minimum noise figure (
) with a
simultaneous power match in the first stage.
of HBT is
given by (4), where WE is the emitter width and LE is the

emitter length of the HBT [3].

can be setting to 50 by
changing the number of the transistors. The unit size transistors
value can be calculated by using (4).
was set to
equal 50 by using 8X device size.
|

(3)

(4)

The input impedance of the common emitter configuration

with emitter degeneration inductor ( ) is given by (5), where
is emitter degeneration inductor and
is base inductor.
The emitter degeneration inductor improves the stability of the
cascode structure because of its negative feedback effect. As
can be seen from (5), the real part of the input impedance can
be controlled by value of the emitter degeneration inductor
and the imaginary part of the input impedance can be
controlled by value of the base inductor
. It was desired that
the value of the base inductor should be as small as possible
since the parasitic resistance of this inductor directly increases
the noise figure. It also was desired that the value of the emitter
inductor should be as small as possible because of its negative
effect on the gain. Therefore, the input impedance was set to a
suitable value to provide more than 15 dB return loss on
operating bandwidth (25-31 GHz). So, the values of the emitter
and base inductors are calculated as 80pH and 135pH,
respectively.
(5)
It was desired that the peak gain of the first stage should be
at 32 GHz, so positive slope gain was obtain between 25 31
GHz for the first stage. The output impedance of the first stage
was set equal to 30 , it means that the input impedance of the
second stage should be equal to 30 .
E. Second Stage Design
Design steps of the second stage are similar to the
methodology presented for the first stage. The input impedance
of the second stage was set equal to 30 by using (5). The
emitter degeneration inductor ( ) and the base inductor ( )
were calculated as 55pH and 135pH, respectively. Bias point of
the second stage was adjusted for low power consumption and
suitable gain performance to meet desired specifications
(VBE=0.84 V and Ic= 2.666 mA). A wideband output
matching was realized by using a shunt inductor , a shunt
resistor
and series capacitor
which can also be
considered as DC blocking capacitor. The output impedance of
the second stage was set equal to 50 at 28 GHz. It also
provides a wideband flat gain for the second stage.
F. Optimization and Schematic
The presented equations were used to calculated
approximate values for devices. After hand calculations, the
element values can be optimized by using schematic results.
By-pass capacitors were used to filter noise from power

supplies as well as to provide RF ground at the operating

frequency. Inductors were designed and EM simulations were
performed by using Sonnet EM program. S2p files of the
inductor exported from Sonnet EM simulations were imported
to Cadence. The schematic of the designed circuit with real
components is seen in Figure 1. Table I. shows the comparison
of the hand calculations and optimized values of the passive
elements.

III. SIMULATION RESULTS

A. Schematic and Post-Layout Results
Noise performances of the schematic and post-layout
circuit are represented in Fig. 3. As can be seen from figure,
there is a about 0.15 dB at the center frequency. This
difference is caused by parasitic resistances extracted from
layout.

TABLE I
CALCULATED AND OPTIMIZED VALUES OF LNA SCHEMATIC

Calculated

Optimized

115 pH

135 pH

80 pH

60 pH

245 pH

260 pH

31 fF

34 fF

145 pH

135 pH

55 pH

55 pH

250

250

340 pH

300 pH

80 fF

70 fF

43 fF

27 fF

750 pH

750 pH

Fig. 3. Noise Figure: Schematic and Post-Layout

G. Post-Layout
After the layout of the cascode structures generated, the
simulations were run with their extracted models. The values of
the inductors and capacitors were again optimized to
compensate the effects of the parasitic elements caused by the
layout. DC, Ground and RF pads and GDSII files of the
inductors exported from Sonnet were putted to the layout. The
post-layout of the designed circuit is seen in Fig. 2. Small
capacitor values are custom designed by using metal2 and
metal3. Layout includes 10 inductors and the total chip area is
0.680 m x 0.600 m = 0.480 m2, including pads.

Fig. 4. Input Return Loss: Schematic and Post-Layout

Fig. 2. Layout of the designed LNA

Fig. 5. Output Return Loss: Schematic and Post-Layout

Input and output return loss performances of the designed

circuit can be seen in Fig. 4. and Fig. 5.As can be seen from
these figures, the designed LNA circuit has better than 10 dB
return loss at both of input and output. Fig. 6. shows the gain
performance of the schematic and post-layout circuits. The
gain value of the post-layout simulation is 17.4 dB at the center
frequency 28 GHz.

As can be seen from Fig. 8, the input 1-dB compression point

is -12.7 dBm at 28GHz. Table II represents comparison of
presented LNA circuit with similar works. Using a Figure-ofMerit (FOM);
[

]
(

[
[
[

]
]

]
(6)

would simplify comparison.

TABLE II
PERFORMANCE COMPARISON WITH OTHER WORKS IN THE
LITERATURE
[4]
[5]
[6]
[7]
This Work
Frequency

NF (dB)

I-P1dB (dBm)

24

30

26

30

28

2.7

2.9

6.4

2.0

2.88

-15

-28

-11

-12.7

14.3

23.5

10.3

11.4

17.4

11

7.9

98

9.04

65 nm
CMOS

120
nm
SiGe

0.25
um
SiGe

0.25 um
SiGe

0.25 um

-3.25

-6.23

-3.60

+8.46

Fig. 6. S21 of the Schematic and Post-layout Circuits

Gain (dB)

Pdiss (mW)

Technology

FOM [dBm]

SiGe

IV. CONCLUSION
Fig. 7. S12 of the Schematic and Post-layout Circuits

A two-25-31 GHz Positive Slope Gain LNA is designed

using IHP Microelectronics 0.25m SiGe BiCMOS
technology. The achieved positive slope gain is from 12.2 dB
to 21.5 dB on bandwidth from 25 to 31 GHz. The slope of the
gain is about 1.5dB/GHz. The gain value is 17.4 dB at the
center frequency 28 GHz. The input 1 dB compression point (IP1dB) is -12.7 dB at the center frequency 28 GHz. The total
power consumption is 9.04 mW. S11 and S22 are less than -10
dB at the whole operating frequency (25-31 GHz). The noise
figure is 2.88 dB at 28 GHz.
The proposed noise figure reduction technique reduces the
noise figure of the designed LNA from 3.17 dB to 2.88 dB at
28 GHz. An analysis method is presented and it will be
mathematically investigated later. The desired specifications
determined by considering the potential requirements of a 5G
mobile device are successfully achieved.
REFERENCES

Fig. 8. Input Referred 1-dB Compression Point

[1]

H. T. Friis, Noise figure of radio receivers, in Proceedings of IRE, vol.

32, no. 7, pp. 419-422, 1944.

[2]

[3]
[4]

[5]

O. Shanaa, I. Linscott, and L. Tyler, Frequency-scalable SiGe bipolar

RF front-end design, IEEE Journal of Solid-State Circuits, vol. 36, no.
6, pp. 888-895, 2001.
J. D. Cressler and G. Niu, Silicon-Germanium Heterojunction Bipolar
Transistors. Norwood, MA: Wrtech House, Inc., 2003.
Tsai, M.-H.; Hsu, S. S. H.; Hsueh, F.-L.; Jou, C.-P.; , "ESDProtected KBand Low-Noise Amplifiers Using RF Junction Varactors in 65-nm
CMOS," Microwave Theory and Techniques, IEEE Transactions on ,
vol.PP, no.99, pp.1, Oct. 2010.
Byung-Wook Min; Rebeiz, G.M.; , "Ka-Band SiGe HBT Low Noise
Amplifier Design for Simultaneous Noise and Input Power Matching,"

[6]

[7]

Microwave and Wireless Components Letters, IEEE , vol.17, no.12,

pp.891-893, Dec. 2007.
Fortes, F.; Costa Freire, J.; Leenaerts, D.; Mahmoudi, R.; van
Roermund, A.; , "A 28.5 GHz monolithic cascode LNA with 70GHz fT
SiGe HBTs," Solid-State Circuits Conference, 2005. ESSCIRC 2005.
Proceedings of the 31st European , vol., no., pp. 93- 96, 12-16 Sept.
2005.
Qian Ma; Leenaerts, D.; Mahmoudi, R., "A 30GHz 2dB NF low noise
amplifier for Ka-band applications, " Radio Frequency Integrated
Circuits Symposium (RFIC), 2012 IEEE, vol.25, no.28, pp.17-19, Jun.
2012