library IEEE;

use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
entity \base de tiempo\ is
port(
inicio: in std_logic;
reloj : in STD_LOGIC;
reinicio : in STD_LOGIC;
q : out STD_LOGIc
);
end \base de tiempo\;

architecture \base de tiempo\ of \base de tiempo\ is

signal count,ctap,ctaf: STD_LOGIC_VECTOR(24 downto 0); --cuenta presente y cuenta
futura
signal qp, qf: STD_LOGIC; --selector de multiplexor
begin
mux:process(inicio,ctap,qp)
begin
if (inicio='1' ) then
if(qp='0') then
ctaf<=ctap+1;
if(ctap>= "1011111010111100001000000") then
qf<='1';
else
qf<=qp;
end if;
else
ctaf<=(others => '0');
qf<='0';
end if;
else
ctaf<=(others => '0');
qf<='0';
end if ;
end process;
q<= qp;
ff:process(reloj,reinicio,qf,ctaf)
begin
if(reinicio='1') then
ctap<=(others=>'0');
qp<='0';
elsif(reloj'event and reloj='1') then
ctap<=ctaf;

qp<=qf;
end if;
end process;

end \base de tiempo\;

library IEEE;

use IEEE.STD_LOGIC_1164.all;
entity contador9 is
port(
reloj : in STD_LOGIC;
rein : in STD_LOGIC;
p : in STD_LOGIC;
Tc : out STD_LOGIC;
q : out STD_LOGIC_VECTOR(3 downto 0);
acarreo:out std_logic
);
end contador9;

architecture contador9 of contador9 is

signal Qp, Qf:std_logic_vector(3 downto 0):="0000";
SIgnal Tp, Tf:std_logic :='0';
begin
conta: process(p, Qp, Tp)
begin
if p = '1' then
case Qp is
when
when
when
when
when
when
when
when
when
when
end case;
else
Qf <= Qp;
Tf <= '0';
end if;

"0000" => Qf <= "0001"; Tf <= '0';

"0001" => Qf <= "0010"; Tf <= '0';
"0010" => Qf <= "0011"; Tf <= '0';
"0011" => Qf <= "0100"; Tf <= '0';
"0100" => Qf <= "0101"; Tf <= '0';
"0101" => Qf <= "0110"; Tf <= '0';
"0110" => Qf <= "0111"; Tf <= '0';
"0111" => Qf <= "1000"; Tf <= '0';
"1000" => Qf <= "1001"; Tf <= '0';
others => Qf <= "0000"; Tf <= '1';

end process;
q <= Qp;
Tc <= Tp;
acarreo <= Tp;
ff: process(reloj, rein, Tf, Qf)
begin
if (rein = '1' and tf= '1') then
Qp <= "0000";
Tp <= '0';
elsif (reloj'event and reloj = '1') then
Qp <= Qf;

Tp <= Tf;
end if;
end process;

end contador9;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity contador6 is
port(
reloj : in STD_LOGIC;
rein : in STD_LOGIC;
p : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(3 downto 0)

);
end contador6;
--}} End of automatically maintained section
architecture contador6 of contador6 is
signal Qp, Qf:std_logic_vector(3 downto 0):="0000";
signal Tp, Tf:std_logic;
begin
conta: process(p, Qp)
begin
if p = '1' then
case Qp is
when
when
when
when
when
when
when

"0000" => Qf <= "0001";

"0001" => Qf <= "0010";
"0010" => Qf <= "0011";
"0011" => Qf <= "0100";
"0100" => Qf <= "0101";
"0101" => Qf <= "0110";
others => Qf <= "0000";

end case;
else
Qf <= Qp;
end if;
end process;
q <= Qp;
ff: process(reloj, rein,Qf)
begin
if (rein = '1') then
Qp <= "0000";
elsif (reloj'event and reloj = '1') then
Qp <= Qf;
end if;
end process;
end contador6;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity final is
port(
inicio : in STD_LOGIC ;
seg: out std_logic_vector(6 downto 0);
trans: out std_logic_vector(3 downto 0);
reloj : in STD_LOGIC;
reinicio : in STD_LOGIC;
acarreo: out std_logic

);
end final;
--}} End of automatically maintained section
architecture final of final is
component \base de tiempo\
port(
inicio : in STD_LOGIC;
reloj : in STD_LOGIC;
reinicio : in STD_LOGIC;
q : out STD_LOGIC);
end component;
component contador9
port(
reloj : in STD_LOGIC;
rein : in STD_LOGIC;
p : in STD_LOGIC;
Tc : out STD_LOGIC;
q : out STD_LOGIC_VECTOR(3 downto 0);
acarreo:out std_logic
);
end component;
component contador6
port(
reloj : in STD_LOGIC;
rein : in STD_LOGIC;
p : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(3 downto 0));
end component;
for all: contador6 use entity work.contador6(contador6);
component deco
port(
bcd : in STD_LOGIC_VECTOR(3 downto 0);
seg : out STD_LOGIC_VECTOR(6 downto 0));
end component;
component \base trans\
port(
inicio : in STD_LOGIC;
reloj : in STD_LOGIC;
reinicio : in STD_LOGIC;
q : out STD_LOGIC);
end component;
component multiplexor
port(
u : in STD_LOGIC_VECTOR(3 downto 0);
d : in STD_LOGIC_VECTOR(3 downto 0);

ct : in STD_LOGIC;
salc : out STD_LOGIC_VECTOR(3 downto 0);
salt : out STD_LOGIC_VECTOR(3 downto 0));
end component;
component contador1
port(
reloj : in STD_LOGIC;
rein : in STD_LOGIC;
p : in STD_LOGIC;
q : out STD_LOGIC);
end component;
signal q,aca:std_logic;
signal u,d,bcd:STD_LOGIC_VECTOR(3 downto 0);
signal contt,ct: std_logic ;
begin
base:\base de tiempo\ port map ( inicio,reloj,reinicio,q) ;
conta9:contador9 port map ( reloj,reinicio,q,aca,u,acarreo) ;
conta6:contador6 port map( reloj,reinicio,aca,d);
decodificador:deco port map (bcd,seg);
baset:\base trans\ port map (inicio,reloj,reinicio,contt);
mux:multiplexor port map (u,d,ct,bcd,trans);
cont1:contador1 port map(reloj,reinicio,contt,ct);
end final;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity deco is
port(
bcd : in STD_LOGIC_VECTOR(3 downto 0);
seg : out STD_LOGIC_VECTOR(6 downto 0)
);
end deco;
--}} End of automatically maintained section
architecture deco of deco is
begin
with bcd select

seg<= "1111110" when "0000" ,

"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"1111111" when others;
end deco;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
entity \base trans\ is
port(
inicio: in std_logic;
reloj : in STD_LOGIC;
reinicio : in STD_LOGIC;
q : out STD_LOGIc
);
end \base trans\;
--}} End of automatically maintained section
architecture \base trans\ of \base trans\ is
signal count,ctap,ctaf: STD_LOGIC_VECTOR(17 downto 0); --cuenta presente y cuenta
futura
signal qp, qf: STD_LOGIC; --selector de multiplexor

begin
mux:process(inicio,ctap,qp)
begin
if (inicio='1' ) then
if(qp='0') then
ctaf<=ctap+1;
if(ctap>= "1100001101010000") then
qf<='1';
else
qf<=qp;
end if;
else
ctaf<=(others => '0');
qf<='0';
end if;
else
ctaf<=(others => '0');
qf<='0';
end if ;
end process;
q<= qp;
ff:process(reloj,reinicio,qf,ctaf)
begin
if(reinicio='1') then
ctap<=(others=>'0');
qp<='0';
elsif(reloj'event and reloj='1') then
ctap<=ctaf;
qp<=qf;
end if;
end process;
end \base trans\;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity multiplexor is
port(
u:in std_logic_vector(3 downto 0);
d:in std_logic_vector(3 downto 0);
ct: in std_logic;
salc:out std_logic_vector(3 downto 0);
salt:out std_logic_vector(3 downto 0)
);
end multiplexor;
--}} End of automatically maintained section
architecture multiplexor of multiplexor is
begin
process (ct)
begin
case ct is
when '0'=>
salc<=u;
salt<="1110";
when others=>
salc<=d;
salt<="1101";
end case;
end process;
end multiplexor;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity contador1 is
port(
reloj : in STD_LOGIC;
rein : in STD_LOGIC;
p : in STD_LOGIC;
q : out STD_LOGIC
);
end contador1;
--}} End of automatically maintained section
architecture contador1 of contador1 is
signal Qp, Qf:std_logic;
begin
conta: process(p, Qp)
begin
if p = '1' then
case Qp is
when '0' => Qf <= '1';
when others => Qf <= '0';
end case;
else
Qf <= Qp;
end if;
end process;
q <= Qp;
ff: process(reloj, rein,Qf)
begin
if (rein = '1') then
Qp <= '0';
elsif (reloj'event and reloj = '1') then
Qp <= Qf;
end if;
end process;
end contador1;