10EC751

USN

Seventh Semester B.E. Degree Examination, Dec.20l4/Jan.20l5

DSP Algorithms &

Architecture

Time: 3 hrs.
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(03 Marks)

1,.)

Derive tne''iilatonship between DFT and frequency responseijffii'also define frequency

resolution and'signpl record length.
(06 Marks)
An FFT is emplo,pd for determining the frequency co,q,pbfints of a random signal. It is
required that the iesotution of FFT to be <:5 Hz,,for;oa signal with fn,'u* : 1.25 kHz.
Determine i) Sampling."ialprval, TS.
ii) FFT length(,N) as a power of 2. i"j1';r',t
iii) Minimum sr$n4l pecord length. ' ,
(04 Marks)
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2 a.
b.
c.

Drawthestructureofa 4x4 Bram,,n'lqhiil[erandalsoexplainitsoperation. (08Marks)

Explain the pointer updating algorithm fbr circular addressing mode.
(08 Marks)
Compute the sequence in which th ,,.-i put data should be ordered for a 16 point DIT FFT
using Bit reversed addressing mode.
(04 Marks)

3 a.

Describe the following units of fffrfs:ZOC54XX processor: i) Barrel shifter iD Central

processing unit.
(0g Marks)
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What is meant by addibssing mode? Explain the absolute,.accumulator, direct and indirect
addressing modes of fMS:ZOC54XX DSP processor.
(12 Marks)

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Max. Marks:100
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I a. Eiplainp digital signal processing system with the help of a block diagragr:'" (07 Marks)
b. List ih:,ihajor unique architecturil features
in any proqiqr-uble DSP devices.
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Note: Answer FIVE full questions, selecting

at least TWO questions from each part.

4 a. Describe ,l::l.rilio1 .of tfe following instructions'

i) MAC *AR3-. xAR4+. B. A
ii) MAs

b.

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*AR3-, *AIt+, B, A

iii),RpTZ and RPTB.

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E*filain the hardware timer of TMS320C54XX DSP with logical block diagr4m.
the pipe line operation of

TMS32}C54xxprocessor.

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b.

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iii)
iv)

v)

c.

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PART_B
What is the significance of Q-notation in DSP?
Represent each of the following numbers in desired Q-notation format:

ii)

(.)

(06 Marks)
(07 Marks)

-352 as Qs number.
3.125 as Q7 number.
BDAFh in Q7 and Q15 number.
-0.160123 as Qrs number.

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4400h as Q6 number.

(06 Marks)

Explain with the help of block diagram and mathematical equations implementation of
decimation filter on TMS320C54XX processor.
(10 Marks)

I of2

10EC751

6 a.
b.
c.

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What minimum size FFT must be used to compute 500 points DFT? What must be done tc
(04 Marks)
the samples before the chosen FFT is applied?
(08 Marks)
FFT
butterfly.
for
the
DIT
factor
scaling
Derive the optimum
Write an assernbly language program for implementing following on TMS320C54XX

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Bit reversed address

generation

"r;;=;",f;,1 ii) Spectrum of the transformed

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b.

data.

is an intemrpt? With a

processor.

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$MSSz0C54XX
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fitlw.does DMA help in increasing the speed of a DSP processor andplffiexnlain register
(10 Marks)
sub dffifpssing technique for configuring

DMA.

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reggffii
bio^telemetry
DSP
based
the
8 a. With nearblbbk diagram explain
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With neat

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explain the CODEC interface

(10 Marks)

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(10 Marks)

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