Name

Regd. No.
SANT LONGOWAL INSTITUTE OF ENGINEERING & TECHNOLOGY, LONGOWAL
DEPARTMENT OF ELECTRONICS & COMMUNICATION
Subject Code: EC-7104
Subject: Software Tools & Electronic Design
Class: GEC/13
Time Allowed: 3 Hours
Maximum Marks: 50
Note: Section-A is compulsory. Attempt any two questions each from Section-B and Section-C.
Section-A
Q1) All carry equal marks except VI carry two marks
I.
What information about a design entity does an architecture body provide?
II.
Into what two parts is an architecture body divided? What is the purpose of each part?
III.
What information does an entity declaration provide about a design entity?
IV.
List three kinds of Library units.
V.
What do you mean by signed and unsigned numbers and how these are defined in VHDL Library?
VI.
Fill the blanks to complete user defined data package to complete constant declaration (here package name
is sliet_my_data,constant initial value is 15 and range is defined from 10 to 1000)
Library ieee;
Use ieee.std_logic_...........all;
Package..is
Constant x:integer:=..
Type vector_array is array(..)
Std_logic_vector(..down to..);
End;
Vii Write syntax to create 1Dx1D array and corresponding signal
Viii What code is used to convert parameter of any type to an integer.
Ix Write at least two difference between data flow and behavioral style of modelling.
Section-B
Q1(a)Write structural VHDL description of 3 to 8 decoder using two 2 to 4 decoders and an inverter b)What are
the different operators used in VHDL.Explain any four in details.
5+5]
Q2.Write a short notes on any of two
[10]
(a)Exit and Next Statement (b) Transport Delay Model (c) Data types used in VHDL.
Q3.a) Write VHDL Code for Four bit parallel adder
[5+5]
b)Write VHDL Code to convert binary to grey code..
Section-C
Q5.Define LabVIEW. What are the features and advantages of LabVIEW? With the help of block diagram explain
the front panel of LabVIEW in detail.
[10]
Q6.a) what do you mean by sequential statements. Explain multiple process and postponed process in detail.
b)Write entity declaration for J-K Flip-Flop.
[8+2]
Q7.Figure shows the intersection of a main highway with a secondary access road. Vehicles detection sensors are
placed along lanes C and D(main road) and lanes A and B (access road).These sensors outputs are low(0) when no
vehicles is present and high(1) when a vehicles is present The intersection traffic light is controlled according to
the following logic
[10]
1. The east-west traffic light will be green whenever both lanes C and D are occupied.
2. The E-W light will be green whenever either C or D is occupied but lanes A and B are not both occupied.
3. The north-south (N-S) light will be green whenever both lanes A and B are occupied but C and D are not both
occupied.
4. The N-S light will also be green when either A or B is occupied while C and D are both vacant.
5. The E-W light will be green when no vehicles are present.
Using sensors outputs A, B, C and D as inputs, design a logic circuit to control the traffic light and write VHDL
code for obtained logic circuit.