CSE/ESE 260M Introduction to Digital Logic and Computer Design

Practice Problems 4

1. Draw a diagram for a circuit that implements the VHDL module shown below. Your
diagram may include gates, muxes and one or more 8 bit subtractors (that is, a circuit with
two 8-bit inputs x and y and an 8 bit output equal to the difference xy). Assume that the
type of word is an 8 bit std_logic_vector.
entity foo is port(A, B: in word; U, V: out word); end foo;
architecture bar of foo is
function negate(en: std_logic; x: word) return word is begin
if en = '0' then return x;
else return (x'range => '0') - x;
end if;
end function negate;
function absVal(x: word) return word is begin
return negate(x(x'high),x);
end function absVal;
function absDiff(x, y: word) return word is begin
return absVal(x-y);
end function absDiff;
begin
U <= absVal(A); V <= absDiff(absVal(A),B);
end bar;

-1-

2. An abbreviated testbench for the priority queue circuit that we discussed in class is shown
below. Recall, the circuit can store eight (key,value) pairs. The testbench applies a sequence of
test inputs to the circuit and checks the circuit output using assertions. Fill in the blanks in
the test data.
architecture a1 of testPriQueue
type testVector is record
key,val: std_logic_vector(3 downto 0); insert,delete: std_logic;
smallVal: std_logic_vector(3 downto 0); empty, full: std_logic;
end record inVec;
type testData is array(natural range <>) of testVector;
constant td: testData := (
-- key
val insert delete smallVal empty full
(x"4", x"f", 1,
0,
xf,
0, 0),
(x"3", x"e", 1,

0,

xe,

0,

0),

(x"5", x"d", 1,

0,

),

-- fill blanks

(x"6", x"c", 1,

0,

),

-- fill blanks

(x"2", x"b", 1,

0,

),

-- fill blanks

(x"1", x"a", 1,

0,

),

-- fill blanks

(x"7", x"d", 1,

0,

),

-- fill blanks

(x"8", x"9", 1,

0,

),

-- fill blanks

(x"0", x"0", 0,
1,
,
,
)); -- fill blanks
...
begin
priq: priQueue port map(clk, reset, insert, delete, key, value,
smallVal, busy, empty, full);
process begin
wait for pause;
reset <= '1'; wait for clkPeriod;
reset <= 0; wait for clkPeriod;
for i in td'low to td'high loop
key <= td(i).key; value <= td(i).value;
insert <= td(i).insert; delete <= td(i).delete;
wait for clkPeriod;
assert (busy = 1) report ...
wait for clkPeriod;
assert (smallVal = td(i).smallVal and empty = td(i).empty
and full = td(i).full and busy = 0) report ...
end loop;
end process;
end a1;

-2-

3. Complete the block diagram on the next page so that it implements the VHDL specification
shown below. You may add gates or multiplexors to the diagram. The body of the
architecture is reproduced on the next page for your convenience.
entity tripleUpCount is port
clk, reset: std_logic;
A: std_logic_vector(7 downto 0);
event: out std_logic;
eventCount: out std_logic_vector(7 downto 0)
end tripleUpCount;
architecture a1 of tripleUpCount begin
type stateType is (s0, s1, s2); signal state: stateType;
signal ev: std_logic;
signal prevA, count: std_logic_vector(7 downto 0);
begin
process(clk) begin
if rising_edge(clk) then
prevA <= A;
if reset = 1 then
state <= s0; count <= (others => 0);
else
case state is
when s0 => if A > prevA then state <= s1; end if;
when s1 => if A < prevA then state <= s0;
elsif A > prevA then state <= s2;
end if;
when s2 => if A < prevA then state <= s0; end if;
when others =>
end case;
end if;
end if;
end process;
ev <= 1 when state = s2 and A > prevA else 0;
count <= count+1 when ev = 1 else count;
event <= ev; eventCount <= count;
end a1;

-3-

begin
process(clk) begin
if rising_edge(clk) then
prevA <= A;
if reset = 1 then
state <= s0; count <= (others => 0);
else
case state is
when s0 => if A > prevA then state <= s1; end if;
when s1 => if A < prevA then state <= s0;
elsif A > prevA then state <= s2;
end if;
when s2 => if A < prevA then state <= s0; end if;
when others =>
end case;
end if;
end if;
end process;
ev <= 1 when state = s2 and A > prevA else 0;
count <= count+1 when ev = 1 else count;
event <= ev; eventCount <= count;
end a1;

-4-

4. Convert the expression shown below to sum-of-products form, then use the K-map to get
the simplest sum-of-products expression you can find.
ABC + (A + B(C + D)) + BC

Use the K-map below to simplify the specified expression (the first summation lists the
minterms, the second lists the dont cares).
m(1,2,4,5,8,13)

d(0,6,9,10,12,15)

-5-