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a)
b)
c)
d) None of the mentioned
View Answer
Answer: c
Explanation: In an ideal op-amp when the inverting terminal is zero. The output will be in-phase
with the input signal.
6. Find the output voltage of an ideal op-amp. If V1 and V2 are the two input voltages
a) VO= V1-V2
b) VO= A(V1-V2)
c) VO= A(V1+V2)
d) VO= V1V2
View Answer
Answer: b
Explanation: The output voltage of an ideal op-amp is the product of gain and algebraic
difference between the two input voltages.
7. How will be the output voltage obtained for an ideal op-amp?
a) Amplifies the difference between the two input voltages
b) Amplifies individual voltages input voltages
c) Amplifies products of two input voltage
View Answer
Answer: a
Explanation: In a non-inverting comparator a fixed reference voltage Vref of 1v is applied to
positive inverting input terminal and the other time vary in signal voltage is applied to noninverting input terminal of the op-amp.
4. How the op-amp comparator should be choosen to get higher speed of operation?
a) Large gain
b) High slew rate
c) Wider bandwidth
d) None of the mentioned
View Answer
Answer: c
Explanation: The bandwidth of the op-amp comparator must be wider so that the output of
comparator can switch rapidly between saturation levels. Also, the op-amp responds instantly to
any change in condition at the input.
5. How to obtain high rate of accuracy in comparator?
a) All of the mentioned
b) High voltage gain
c) High CMRR
d) Input offset
View Answer
Answer: a
Explanation: High voltage gain causes comparator output voltage to switch between saturation
levels. High CMRR rejects noise at input terminal and input offset (voltage & current) help to
keep changes in temperature variation very slight.
6. How to keep the output voltage swing of the op-amp comparator within specific limits?
a) External resistors or diodes are used
b) External zeners or diodes are used
c) External capacitors or diodes are used
d) External inductors or diodes are used
View Answer
Answer: b
Explanation: To keep the output voltage swing within specific limit, op-amps are used with
external wired components such as zeners or diodes. In the resulting circuit, the outputs are
limited to predetermined values.
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7. Zero crossing detectors is also called as
a) Square to sine wave generator
b) Sine to square wave generator
c) Sine to triangular wave generator
View Answer
Answer: b
Explanation: The output of the zero crossing detector is differentiated by an RC circuit (RC>>1).
So, the voltage at V2 is a series of positive and negative pulses.
13. Mention the application areas of time marker generator can be used
a) Monoshots
b) SCR
c) Sweep voltage of CRT
d) All of the mentioned
View Answer
Answer: d
Explanation: A diode connected at the output of time marker generator circuit converts the
sinusoidal signal into a train of positive pulses. So, these pulses are used in triggering the
monoshot, SCR, sweep voltage of CRT, etc.
14. Which among the following is used to increase phase angle between different voltages?
a) Phase detector
b) Window detector
c) Zero crossing detector
d) None of the mentioned
View Answer
Answer: a
Explanation: Phase angle between different voltages can be measured using phase detector
circuit. The corresponding voltage to be measured is converted into spikes and the time interval
between the pulse spikes is measured, which is proportional to the phase difference.
15. For the comparator shown below, determine the transfer curves if an ideal op-amp with VZ1=
VZ2=9v.
View Answer
Answer: a
Explanation: The open loop voltage gain of an ideal op-amp AOl=, even a small positive or
negative voltage at the input drives the output to Vsat. So, the output voltage VO = ( V2 +Vsat)
Therefore, VO = (VZ+VSat) = (9+0.7) = 9.7 v.
Find the input and output resistance for the circuit shown.
Specification for 741 op-amp : A=400000 ; Ri = 33M; Ro = 60;
RF = 11k; R1 = 2k; Supply voltage = 15v; Maximum output voltage swing = 13v.
d) io =[A*(Vo-Vid)]/Ro
View Answer
Answer: b
Explanation: The output current in voltage series feedback amplifier is given as io ={[Vo(A*Vid)]/Ro}.
4. Find the unity gain bandwidth for voltage series feedback amplifier?
a) UBG = Afo
b) UBG = AfF
c) UBG = Afo fF
d) UBG = AFfo
View Answer
Answer: a
Explanation: The unity gain bandwidth is given as product of open loop voltage gain and break
frequency of an op-amp.
5. The bandwidth of a non-inverting amplifier with feedback is equal to
a) fo(AB)
b) fo(AB-1)
c) fo(1+AB)
d) fo(1-AB)
View Answer
Answer: c
Explanation: The bandwidth of the non-inverting amplifier with feedback is equal to its
bandwidth without feedback times (1+AB). i.e. fF=fo(1+AB).
6. How are the saturation voltage specified on the manufactures datasheet?
a) Negative voltage
b) Output voltage swing
c) Supply voltage
d) None of the mentioned
View Answer
Answer: b
Explanation: In an open loop op-amp, the total output offset voltage (i.e. output voltage swing) is
equal to either the positive or negative saturation voltage.
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7. What is the formula for total output offset voltage with feedback?
a) VooT = Vo/(1+AB)
b) VooT = Vsat*(1+AB)
c) VooT = Vsat/(1+AB)
d) VooT = Vo*(1+AB)
View Answer
Answer: c
Explanation: The total output offset voltage with feedback = (Total output offset voltage witput
feedback) / (1+AB). i.e. VooT = Vsat/(1+AB).
8. Which of the following has the same characteristic as that of non-inverting amplifier with
feedback?
a) Perfect feedback amplifier
b) Voltage follower
c) Perfect voltage amplifier
d) All of the mentioned
View Answer
Answer: c
Explanation: A perfect voltage amplifier has very high input resistance, very low output
resistance, stable voltage gain, large bandwidth and very little output offset voltage.
From the analysis of the characteristic of non-inverting amplifier with feedback, it is clear that it
exhibits the characteristics of a perfect voltage amplifier.
9. What is the gain of voltage follower?
a) Gain >
b) Gain >1
c) Gain <1
d) Gain -->
View Answer
Answer: b
Explanation: Voltage follower is non-inverting amplifier configured for unity gain. Such that the
output voltage is equal to and in phase with the input.
10. Which is preferred to attain higher input resistance and the output amplitude equal to input?
a) Voltage follower
b) Voltage series feedback amplifier
c) Voltage shunt feedback amplifier
d) Inverter
View Answer
Answer: a
Explanation: In the voltage follower the output follow the input due to unity gain. Therefore, it is
attained to get higher input resistance and output amplitude equal to input.
11. Find the input and output voltage in voltage follower circuit?
a) Vin=2v and Vout = 3v
b) Vin=10v and Vout = 11v
c) Differential amplifier
d) None of the mentioned
View Answer
2. Find the bias current from the given circuit
a) 30mA
b) 3mA
c) 0.30mA
d) 0.03mA
View Answer
Answer: c
Explanation: The bias current is given as Iin =Vin/Rin = 3v/10k.
Where, Iin= Ib =0.3mA.
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3. How to choose an op-amp when working with high input source resistance?
a) Op-amp with low bias current
b) Op-amp with higher slew rate
c) Buffer or voltage follower
d) All of the mentioned
View Answer
Answer: d
Explanation: When the op-amp is driven by a high input source resistance, the output and input
voltage will not be equal due to error at the input. A remedy to this problem is an op-amp with
low input bias current and high slew rate should be chosen as a voltage follower.
4. What must be done to block the ac input voltage riding on a dc level?
a) Use RC network
2. Find the circuit that is used to compress the dynamic range of a signal?
View Answer
Answer: a
Explanation: Log amps are used to compress the dynamic range of a signal. The fundamental log
amp circuit consists of a grounded base transistor in the feedback path.
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3. Find the output voltage of the log-amplifier
a) VO = -(kT)ln(Vi/Vref)
b) VO = -(kT/q)ln(Vi/Vref)
c) VO = -(kT/q)ln(Vref/Vi)
d) VO = (kT/q)ln(Vi/Vref)
View Answer
Answer: b
Explanation: the output voltage is proportional to the logarithm of input voltage.
VO =-(kT/q)ln(Vi / Vref).
4. How to provide saturation current and temperature compensation in log-amp?
a) Applying reference voltage alone to two different log-amps
b) Applying input and reference voltage to same log-amps
c) Applying input and reference voltage to separate log-amps
d) None of the mentioned
View Answer
Answer: c
Explanation: The emitter saturation current varies from transistor to transistor with temperature.
Therefore, the input and reference voltage are applied to separate log-amps and two transistors
are integrated close together in the same silicon wafer. This provides a close match of the
saturation currents and ensures good thermal tracking.
5. The input voltage, 6v and reference voltage, 4 v are applied to a log-amp with saturation
current and temperature compensation. Find the output voltage of the log-amp?
a) 6.314(kT/q)v
b) 0.597(kT/q)v
c) 0.405(kT/q)v
d) 1.214(kT/q)v
View Answer
Answer: c
Explanation: The output voltage of saturation current and temperature compensation log-amp, VO
= (kT/q)ln(Vi / Vref) =(kT/q)ln(6v/4v) =(kT/q)ln(1.5)
VO = 0.405(kT/q)v.
6. Find the circuit used for compensating dependency of temperature in the output voltage?
View Answer
Answer: c
Explanation: The temperature dependence on the output voltage is compensated by connecting
an op-amp which provide a non-inverting gain of [1+ (R2/ RTC)] at the output of the log-amp with
saturation current compensation.
Now the output voltage becomes,VO = [1+ (R2/ RTC)][(kT/q)ln(Vi / Vref)]
Where, RTC > temperature sensitive resistance with a positive co-efficient of temperature.
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7. Determine the output voltage for the given circuit
a) VO = Vref/(10-kvi)
b) VO = Vref+(10-kvi)
c) VO = Vref(10-kvi)
d) VO = Vref-(10-kvi)
View Answer
Answer: c
Explanation: The output voltage of an antilog amp is given as, VO = Vref (10-kvi)
Where k = 0.4343 (q/kt)[(RTC/ (R2 +RTC)].
8. Calculate the base voltage of Q2 transistor in the log-amp using two op-amps?
a) 8.7v
b) 5.3v
c) 3.3v
d) 6.2v
View Answer
Answer: c
Explanation: The base voltage of Q2 transistor, VB = [RTC / (R2 +RTC)](Vi) = [10k/
(5k+10k)]5v =3.33v.
9. Compute the reference voltage for a fundamental log-amp, if its internal resistance=5M.
a) 0.5v
b) 0.05v
c) 5v
d) None of the mentioned
View Answer
Answer: a
Explanation: Reference voltage, Vref = R1 Is
Where, Is~10-13A (for an emitter saturation current).
Vref = 10-13 5M = 510-7 = 0.5v.
This set of Linear Integrated Circuit Multiple Choice Questions & Answers (MCQs) focuses on
Very High Input Impedance Circuit.
1. Which among the following circuit has the highest input resistance?
a) Voltage follower
b) Inverting amplifier
c) Differential amplifier
d) None of the mentioned
View Answer
Answer: a
Explanation: Voltage follower has the highest positive input resistance of any op-amp circuit. For
this reason it is used to reduce voltage error caused by source loading.
2. Find the bias current from the given circuit
a) 30mA
b) 3mA
c) 0.30mA
d) 0.03mA
View Answer
Answer: c
Explanation: The bias current is given as Iin =Vin/Rin = 3v/10k.
Where, Iin= Ib =0.3mA.
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3. How to choose an op-amp when working with high input source resistance?
a) Op-amp with low bias current
b) Op-amp with higher slew rate
c) Buffer or voltage follower
d) All of the mentioned
View Answer
Answer: d
Explanation: When the op-amp is driven by a high input source resistance, the output and input
voltage will not be equal due to error at the input. A remedy to this problem is an op-amp with
low input bias current and high slew rate should be chosen as a voltage follower.
4. What must be done to block the ac input voltage riding on a dc level?
a) Use RC network
b) Use coupling capacitor
c) Use resistive transducer
d) None of the mentioned
View Answer
Answer: b
Explanation: In order to block the dc level a coupling capacitor must be used in series with the
input of the voltage follower.
5. To get higher input resistance in AC coupled voltage follower,
a) The output resistance is bootstrapped
b) The input resistance is bootstrapped
c) The bias resistance is bootstrapped
d) The feedback resistance is bootstrapped
View Answer
Answer: c
Explanation: Bias resistor connected to ground to provide path in an AC coupled voltage
follower, drastically reduces the input resistance of the circuit. Therefore, to get high input
resistance, the bias resistance is bootstrapped.
View Answer
Answer: b
Explanation: An AC coupled voltage follower consists of coupling capacitor at the input of noninverting terminal.
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7. Voltage follower circuit are used in
a) Active filter
b) All of the mentioned
c) Sample and hold circuit
d) Bridge circuit with transducer
View Answer
Answer: b
Explanation: Voltage followers are useful for all the above mentioned applications, because they
involve working with high-input source resistance.
View Answer
Answer: b
Explanation: An AC coupled voltage follower consists of coupling capacitor at the input of noninverting terminal.
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7. Voltage follower circuit are used in
a) Active filter
b) All of the mentioned
c) Sample and hold circuit
d) Bridge circuit with transducer
View Answer
Answer: b
Explanation: Voltage followers are useful for all the above mentioned applications, because they
involve working with high-input source resistance.
Which type of amplifier has output voltage equal to the average of all input voltages?
a) Inverting averaging amplifier
b) Non-inverting averaging amplifier
c) Non-inverting summing amplifier
d) Inverting scaling amplifier
View Answer
Answer: b
Explanation: In non-inverting averaging amplifier, the non-inverting input voltage is the average
of all inputs, with a positive sign.
2. Expression for output voltage of non-inverting summing amplifier with five input voltage?
a) Vo = 5( Va + Vb+ Vc+ Vd+ Ve)
b) Vo = [1+( Rf/R1)] ( Va + Vb+ Vc+ Vd+ Ve)
c) Vo = Va + Vb+ Vc+ Vd+ Ve
d) Vo = ( Va + Vb+ Vc+ Vd+ Ve) /5
View Answer
Answer: c
Explanation: The output voltage of non-inverting summing amplifier is (1+ ( Rf / R1 )) times the
average of all input voltages in the circuit.
Since there are five input voltages => (1+ ( Rf / R1 )) =5
Therefore, Vo = 5( Va + Vb+ Vc+ Vd+ Ve) /5
=> Vo = (Va + Vb+ Vc+ Vd+ Ve).
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a) Vo 3v , RiF=6.67M
b) Vo 3v , RiF= 7M
c) Vo 3v , RiF=9.2M
d) Vo 3v , RiF= 3.5M
View Answer
Answer: a
Explanation: The output voltage Vo= [1 + (RF/R1)] [ (Va+Vb+Vc/3)] = [1+(2k/1k)] [(34+5)/3]= 2.67 3v.
Internal resistance of circuit, RiF =R i [AR1/ (R1+ RF)] = 100[(2000001k)/(1k+2k)]
=> RiF= 6.67 M.
6. Find the type of amplifier that cannot be constructed in differential configuration?
a) Summing amplifier
b) Scaling amplifier
c) Averaging amplifier
d) Subtractor
View Answer
Answer: c
Explanation: In differential op-amp configuration, an amplifier produces sum or difference
between two input terminals of op-amp. So, averaging is not possible in this type of
configuration.
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7. Calculate the output voltage, when a voltage of 12mv is applied to the non-inverting terminal
and 7mv is applied to inverting terminal of a subtractor.
a) 19mv
b) 5mv
c) 1.7mv
d) 8.4mv
View Answer
Answer: b
Explanation: Output voltage of a subtractor Vo = Vnon-inverting terminal Vinverting terminal = 12mv-7mv
=5mv.
8. In differential op-amp configuration a subtractor is called as
a) Summing amplifier
b) All of the mentioned
c) Scaling amplifier
d) Difference amplifier
View Answer
Answer: c
Explanation: In a subtractor input signals can be scaled to the desired values by selecting
appropriate values for the external resistors. Therefore, this circuit is referred to as scaling
amplifier.
9. Find the differential amplifier configured as a subtractor from the given circuit.
View Answer
10. How many additional sources are connected to each input terminal to obtain an eight input
summing amplifier?
a) Six
b) Three
c) Four
d) Eight
View Answer
Answer: b
Explanation: An eight input summing amplifier can be constructed using basic differential
amplifier, if six additional input sources are used by connecting three input sources to inverting
and non-inverting input terminal through resistors.
11. Calculate the output voltage for the summing amplifier given below, where R=2k and RL
=10k.
a) 4v
b) 18v
c) 8v
d) None of the mentioned
View Answer
Answer: a
Explanation: The output voltage for summing amplifier is given Vo =-Va -Vb +Vc +Vd =3-4+6+5
=4v.
12. The output voltage of a summing amplifier is equal to (assume sum of input voltage as Vn )
a) Vn (non-inverting terminal)+ Vn (inverting terminal)
b) Vn (non-inverting terminal)+ (-Vn (inverting terminal)
c) -Vn (non-inverting terminal)+ (-Vn (inverting terminal)
Answer: b
Explanation: In an averaging amplifier, the gain by which each input is amplified must be equal
to lower number of input.
=> RF /R =1/n , where n=number of inputs
RF /R=1/4 = 0.25 (Four inputs)
So, each input in the averaging amplifier must be amplified by 0.25.
8. 3v, 5v and 7v are the three input voltage applied to the inverting input terminal of averaging
amplifier. Determine the output voltage?
a) -5v
b) -10v
c) -15v
d) -20v
View Answer
Answer: a
Explanation: The output voltage, Vo = -[(Va+Vb+Vc)/3] = -[(3+5+7)/3] =-5v.
9. When does the offset voltage compensating network must be used in inverting configuration?
a) When the input is AC voltage
b) When the input is DC voltage
c) When the input is either AC or DC voltage
d) None of the mentioned
View Answer
Answer: b
Explanation: To reduce the output offset voltage to zero, the offset minimizing resistor is used to
minimize the effect of input bias currents on the output offset voltage. However, when the inputs
are DC voltages, the offset compensating network must be used.
10. State the application in which summing, scaling or averaging amplifiers are used?
a) Multiplexers
b) Counters
c) Audio mixers
d) All of the mentioned
View Answer
Answer: c
Explanation: Summing, scaling or averaging amplifiers are commonly used in audio mixers, in
which a number of inputs are added up to produce a desired output.
11. The following circuit represents an inverting scaling amplifier. Compute the value of RoM and
VO?
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3. The value of emitter resistance in Emitter Biased circuit are RE1=25k & RE2=16k. Find
RE
a) 9.756k
b) 41k
c) 9.723k
d) 10k
View Answer
Answer: a
Explanation: In emitter biased circuit, RE1 & RE2 is connected in parallel combination.
RE = RE1 II RE2 = (RE1 RE2)/(RE1+RE2) = (25k16k)/(25k+16k) = 9.7561k.
4. If output is measured between two collectors of transistors, then the Differential amplifier with
two input signal is said to be configured as
a) Dual Input Balanced Output
b) Dual Input Unbalanced Output
c) Single Input Balanced Output
d) Dual Input Unbalanced Output
View Answer
Answer: a
Explanation: When two input signals are applied to base of transistor, it is said to be Dual Input.
When both collectors are at same DC potential with respect to ground, then it is said to be
Balance Output.
5. A differential amplifier is capable of amplifying
a) DC input signal only
b) AC input signal only
c) AC & DC input signal
d) None of the Mentioned
View Answer
Answer: c
Explanation: Direct connection between stages removes the lower cut off frequency imposed by
coupling capacitor; therefore it can amplify both AC and DC signal.
6. In ideal Differential Amplifier, if same signal is given to both inputs, then output will be
a) Same as input
b) Double the input
c) Not equal to zero
d) Zero
View Answer
Answer: d
Explanation: In ideal amplifier, Output voltage
Vout = Vin1-Vin2.
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7. Find the Single Input Unbalance Output configuration in following circuit diagrams :
a)
b)
c)
d)
View Answer
Answer: c
Explanation: Circuit c has only single input (V1) and output is measure only at one of the
collector with respect to ground.
8. An emitter bias Dual Input Balanced Output differential amplifier has VCC=20v, =100,
VBE=0.7v, RE=1.3k. Find IE
a) 7.42mA
b) 9.8mA
c) 10mA
d) 8.6mA
View Answer
9. Find IC, given VCE=0.77v, VCC=10v, VBE=0.37v and RC=2.4k in Dual Input Balanced
Output differential amplifier
a) 0.4mA
b) 0.4A
c) 4mA
d) 4A
View Answer
Answer: c
Explanation: Substitute the values in collector to emitter voltage equation,
VCE= VCC+ VBE-RC IC
IC = (VCC-VCE+VBE)/RC = (10v-0.77v+0.37v)/2.4k = 4mA
10. Find the correct match
Configuration
1. Single Input Unbalanced Output
2. Dual Input Balanced Output
3. Single Input Balanced Output
4. Dual Input Unbalanced Output
c) 0.555v
d) None of the mentioned
View Answer
12. For the circuit shown below, determine the Output voltage (Assume =5, differential input
resistance=12 k)
a) 4.33v
b) 2.33v
c) 3.33v
d) 1.33v
View Answer
Answer: c
Explanation: From the circuit dig, RC=10k, Vin1= 1.3v and Vin2=0.5v,
Differential input resistance = 2 re,
12k = 25Re
Re = 1.2 k
Output voltage Vo = RC/2Re(Vin1-Vin2)
Vo = 10k/(2 1.2k) (1.3v-0.5v)
Vo = 3.33v.
13. In a Single Input Balanced Output Differential amplifier, given VCC=15v, RE = 3.9k,
VCE=2.4 v and re=250. Determine Voltage gain
a) 26
b) 56
c) 38
d) 61
View Answer
Answer: a
Explanation: In single Input Balance Output amplifier,
IE = (VEE-VBE)/2RE
=(15v-0.7v)/(23.9kom)= 1.83mA (VCC=VEE)
From the equation, VCE = VCC +VBE-RCIC
a) Vo = 7v
b) Vo = 5.9v
c) Vo = 12v
d) Vo = 11.4v
View Answer
Answer: c
Explanation: The output voltage, Vo = A*(Vin1-Vin2).(Since, Rin1 and Rin2 are negligible compared
to input resistance in open loop differential amplifier).
=> Vo = 4*(12v-9v) = 12v.
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10. Find the non-inverting amplifier configuration from the given circuit diagram?
View Answer
Answer: c
Explanation: In a non-inverting amplifier, the input is applied to the non-inverting input terminal
and the inverting terminal is connected to ground.
11. What happen if any positive input signal is applied to open-loop configuration?
a) Output reaches saturation level
b) Output voltage swings peak to peak
c) Output will be a sine waveform
d) Output will be a non-sinusoidal waveform
View Answer
Answer: a
Explanation: In open-loop configuration, due to very high gain of the op-amp, any input signal
slightly greater than zero drives the output to saturation level.
12. Why open-loop op-amp configurations are not used in linear applications?
a) Output reaches positive saturation
b) Output reaches negative saturation
c) Output switches between positive and negative saturation
View Answer
Answer: a
Explanation: Log amps are used to compress the dynamic range of a signal. The fundamental log
amp circuit consists of a grounded base transistor in the feedback path.
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3. Find the output voltage of the log-amplifier
a) VO = -(kT)ln(Vi/Vref)
b) VO = -(kT/q)ln(Vi/Vref)
c) VO = -(kT/q)ln(Vref/Vi)
d) VO = (kT/q)ln(Vi/Vref)
View Answer
Answer: b
Explanation: the output voltage is proportional to the logarithm of input voltage.
VO =-(kT/q)ln(Vi / Vref).
4. How to provide saturation current and temperature compensation in log-amp?
a) Applying reference voltage alone to two different log-amps
b) Applying input and reference voltage to same log-amps
c) Applying input and reference voltage to separate log-amps
d) None of the mentioned
View Answer
Answer: c
Explanation: The emitter saturation current varies from transistor to transistor with temperature.
Therefore, the input and reference voltage are applied to separate log-amps and two transistors
are integrated close together in the same silicon wafer. This provides a close match of the
saturation currents and ensures good thermal tracking.
5. The input voltage, 6v and reference voltage, 4 v are applied to a log-amp with saturation
current and temperature compensation. Find the output voltage of the log-amp?
a) 6.314(kT/q)v
b) 0.597(kT/q)v
c) 0.405(kT/q)v
d) 1.214(kT/q)v
View Answer
Answer: c
Explanation: The output voltage of saturation current and temperature compensation log-amp, VO
= (kT/q)ln(Vi / Vref) =(kT/q)ln(6v/4v) =(kT/q)ln(1.5)
VO = 0.405(kT/q)v.
The center frequency of a band-pass filter is always equal to the
A
bandwidth
.
B.3 dB frequency
C.bandwidth divided by Q
D
geometric average of the critical frequencies
.
Answer & Explanation
Answer: Option D
Explanation:
No answer description available for this question. Let us discuss.
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2.
The formula
shows that for a given capacitor, if the voltage changes at a
constant rate with respect to time, the current will
A
increase
.
B.decrease
C.be constant
D
decrease logarithmically
.
Answer & Explanation
Answer: Option C
Explanation:
No answer description available for this question. Let us discuss.
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3.
A zero-level detector is a
A
comparator with a sine-wave output
.
B.comparator with a trip point referenced to zero
C.peak detector
D
limiter
.
Answer & Explanation
Answer: Option B
Explanation:
No answer description available for this question. Let us discuss.
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4.
A digital-to-analog converter is an application of the
A
scaling adder
.
B.voltage-to-current converter
C.noninverting amplifier
D
adjustable bandwidth circuit
.
Answer & Explanation
Answer: Option A
Explanation:
No answer description available for this question. Let us discuss.
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5.
If the value of resistor Rf in an averaging amplifier circuit is equal to the value of one input
resistor divided by the number of inputs, the output will be equal to
A
the average of the individual inputs
.
B.the inverted sum of the individual inputs
C.the sum of the individual inputs
D
the inverted average of the individual inputs
.
Answer & Explanation
Answer: Option D
If the input to a comparator is a sine wave, the output is a
A ramp voltage
.
B.sine wave
C.rectangular wave
D
sawtooth wave
.
Answer & Explanation
Answer: Option C
Explanation:
No answer description available for this question. Let us discuss.
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7.
A basic series regulator has
A
an error detector
.
B.a load
C.a reference voltage
D
both an error detector and a reference voltage
.
Answer & Explanation
Answer: Option D
Explanation:
No answer description available for this question. Let us discuss.
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8.
A comparator is an example of a(n)
A
active filter
.
B.current source
C.linear circuit
D
nonlinear circuit
.
Answer & Explanation
Answer: Option D
Explanation:
No answer description available for this question. Let us discuss.
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9.
Initially, the closed-loop gain (Acl) of a Wien-bridge oscillator should be
A
A <3
. cl
B.Acl > 3
C.0
D
A
1
. cl
Answer & Explanation
Answer: Option B
Explanation:
No answer description available for this question. Let us discuss.
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10.
In an averaging amplifier, the input resistances are
A
equal to the feedback resistance
.
B.less than the feedback resistance
C.greater than the feedback resistance
D
unequal
.
Answer & Explanation
Answer: Option C
A triangular-wave oscillator can consist of an op-amp comparator, followed by a(n)
A
differentiator
.
B.amplifier
C.integrator
D
multivibrator
.
Answer: d
Explanation: Any undesired noise, common to both of the input terminal is suppressed by
differential amplifier.
5. Which of the following is not preferred for input stage of Op-amp?
a) Dual Input Balanced Output
b) Differential Input Single ended Output
c) Cascaded DC amplifier
d) Single Input Differential Output
View Answer
Answer: c
Explanation: Cascaded DC amplifier suffers from major problem of drift of the operating point,
due to temperature dependency of the transistor.
6. What will be the emitter current in a differential amplifier, where both the transistor are biased
and matched? (Assume current to be IQ)
a) IE = IQ/2
b) IE = IQ
c) IE = (IQ)2/2
d) IE = (IQ)2
View Answer
Answer: a
Explanation: Due to symmetry of differential amplifier circuit, current IQ divides equally through
both transistors.
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7. From the circuit, determine the output voltage (Assume F=1)
a) VO1=3.9v , VO2=12v
b) VO1=12v , VO2=3.9v
c) VO1=12v , VO2=0v
d) VO1=3.9v , VO2=-3.9v
View Answer
Answer: b
Explanation: The voltage at the common emitter E will be -0.7v, which make Q1 off and the
entire current will flow through Q2.
VO1 = VCC VO2= VCC-FIQRC,
VO1 = 12v , VO2=12v-13mA2.7k = 3.9v.
8. At what condition differential amplifier function as a switch
a) 4VT < Vd < -4VT
b) -2VT Vd 2VT
c) 0 Vd < -4VT
d) 0 Vd 2VT
View Answer
Answer: a
Explanation: For Vd > 4VT, the output voltage are VO1 = VCC, VO2= VCC-F IQRC. Therefore, a
transistor Q1 will be ON and Q2 will be OFF. Similarly for Vd> -4VT, both transistors Q2 & Q1
will be ON.
9. For Vd > 4VT, the function of differential amplifier will be
a) Switch
b) Limiter
c) Automatic gain control
d) Linear Amplifier
View Answer
Answer: b
Explanation: At this condition, input voltage of the amplifier is greater than 100mv and thus
acts as a limiter.
10. Change in value of common mode input signal in differential pair amplifier make
a) Change in voltage across collector
b) Slight change in collector voltage
c) Collector voltage decreases to zero
d) None of the mentioned
View Answer
Answer: a
Explanation: In differential amplifier due to symmetry, both transistors are biased and matched.
Therefore, Voltage at each collector will be same.
11. Find collector current IC2, given input voltages are V1=2.078v & V2=2.06v and total current
IQ=2.4mA. (Assume =1)
a) 0.8mA
b) 1.6mA
c) 0.08mA
d) 0.16mA
View Answer
Answer: a
Explanation: Collector current, IC2=FIQ/(1+eVdVT),
VT = Volts equivalent of temperature = 25mv,
Vd = V1-V2 =2.078v-2.06v=0.018v (equ1)
Substituting equation 1,
Vd/VT = 0.018v/25mv = 0.72v (equ2)
Substituting equation 2,
IC2= 12.4mA/(1+e0.72) = 2.4mA/(1+2.05) = 0.8mA.
12. A differential amplifier has a transistor with 0= 100, is biased at ICQ = 0.48mA. Determine
the value of CMRR and ACM, if RE =7.89k and RC = 5k.
a) 49.54 db
b) 49.65 d
c) 49.77 db
d) 49.60 db
View Answer
Answer: b
Explanation: Differential mode gain, ADM= -gmRC and Common mode gain,
ACM= -(gmRC)/(1+2gmRE)
(for 01).
Substituting the values,
gm= ICQ/VT = 0.48mA/25mv=19.210-3-1
ADM= -gmRC= -19.210-3-15k= -96
ACM= -(gmRC)/(1+2gmRE)= -(19.210-3-15k) /(1+2- 19.210-3-17.89k) = -0.3158
CMRR = -96/-0.3158= 303.976
=20log303.976
=49.65db
Choose the compensating network design for non-inverting amplitude
View Answer
Answer: a
Explanation: If an op-amp is used as an non-inverting amplifier, the compensating network
should be connected to the inverting input terminal of the op-amp.
a) Ra =4.6k ; Rb= 9k
b) Ra =7.3k ; Rb= 3.4k
c) Ra =2.5k ; Rb= 5.1k
d) Ra =4k ; Rb= 10k
View Answer
Answer: d
Explanation: We know that input offset voltage, Vio =(Rc*Vmax)/ Rb
=> Rb = Vmax*(Rc / Rb ) = (10v/10mv)*10 ( Vio specified on the datasheet is 10mv for LM307
op-amp).
=> Rb =10000 = 10k.
Since Rb > Rmax let us choose Rb = 10*Rmax. (Where Rmax = Ra/4).
Rb = (10*Rb)/4 and Ra = Rb/2.5 = 10k/2.5=4k.
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7. Why does an op-amp without feedback is not used in linear circuit application?
a) Due to high current gain
b) Due to high voltage gain
c) Due to high output signal
d) All of the mentioned
View Answer
Answer: b
Explanation: In an op-amp without feedback, the voltage gain is extremely high (ideally infinite).
Because of the high risk of distortion and clipping of the output signal, an op-amp in open loop
configuration is not used in linear circuit application.
8. When the input voltage is reduced to zero in a closed loop configuration the circuit acts as
a) Inverting amplifier
b) Non-inverting amplifier
c) Inverting and non-inverting amplifier
d) None of the mentioned
View Answer
Answer: c
Explanation: Since, the input signal voltage is reduced to zero, the internal resistance is
negligibly small. The output offset voltage is expressed in terms of external resistance and the
specified input offset voltage for a given op-amp.
If the non-inverting input terminal is connected to ground, it acts as inverting op-amp and vice
versa.
9. How the value of output offset voltage is reduced in closed loop op-amp?
a) By increasing gain
b) By reducing gain
c) By decreasing bandwidth
d) By reducing bandwidth
View Answer
Answer: b
Explanation: The output offset voltage is a product of gain and specified input offset voltage for
a given op-amp. Voo= Aoo*Vio. So, the value of output offset voltage can be reduced by reducing
the gain value.
Input bias current is defined as
a) Average of two input bias current
b) Summing of two input bias current
c) Difference of two input bias current
d) Product of two input bias current
View Answer
Answer: a
Explanation: Input bias current is the average of two input bias current flowing into the noninverting and inverting input of an op-amp.
2. Although the value of input bias current is very small, it causes
a) Output voltage
b) Input offset voltage
c) Output offset voltage
d) All of the mentioned
View Answer
Answer: c
Explanation: Even a very small value of input bias current can cause a significant output offset
voltage in circuits using relatively large feedback resistors.
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3. The formula for output offset voltage of an op-amp due to input bias current
a) VOIB= RF*IB
b) VOIB= (RF+R1)/IB
c) VOIB= (1+RF)*IB
d) VOIB= [1+(RF/R1)]*IB
View Answer
Answer: a
Explanation: The output offset voltage due to input bias current is VOIB = RF*IB.
4. Find the input bias current for the circuit given below
a) 10mA
b) 2mA
c) 5mA
d) None of the mentioned
View Answer
Answer: c
Explanation: Input bias current, IB=(IB1+ IB2)/2
=> IB =(4mA+6mA)/2 = 5mA.
5. Mention a step to reduce the output offset voltage caused due to input bias current?
a) Use small feedback resistor and resistance at the input terminal
b) Use small feedback resistors
c) Reduce the value of load resistors
d) None of the mentioned
View Answer
6. Given below is a differential amplifier in which V1=V2. What happens to VOIB at this
condition?
a) VOIB= 0
b) VOIB= VOIB10-10
c) VOIB= VOIB/2
d) VOIB= -1
View Answer
Answer: a
Explanation: The voltage V1 and V2 are caused by the current IB1 and IB2. Although this bias
current are very small, if they are made equal, then there will be no output voltage VOIB.
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7. Name the resistor that is connected in the non-inverting terminal of op-amp which is in
parallel combination of resistor connected in inverting terminal and feedback resistor.
a) Random minimizing resistor
b) Offset minimizing resistor
c) Offset reducing resistors
d) Output minimizing resistors
View Answer
Answer: b
Explanation: The voltage is product of resistors and input bias current. Therefore, the value of
the resistors are adjusted such that the resistors are connected at the inverting input terminal is
made equal to resistor connected in non-inverting input terminal. The use of this resistors
minimize the amount of output offset voltage and therefore, they are referred to as offset
minimizing resistors.
a) 1173.11
b) 171.31
c) 1171.43
d) 1071.43
View Answer
Answer: d
Explanation: Offset minimizing resistor, ROM =(R1* RF)/( R1+RF).
=> ROM = (1.2k*10k)/(1.2k+10) = 1071.43.
9. Calculate the output voltage for the given circuit using the specification: R1 = 820;
ROM=811.882; Vin=10mVpp; VOIB0.
a) 1.025Vpp
b) 1.8Vpp
c) 1Vpp
d) 2Vpp
View Answer
Answer: c
Explanation: Offset minimizing resistor, ROM = (R1*RF)/(R1+ RF)
=> RF = (ROM* R1)/( R1- ROM) = (812*811.882)/(820-811.882) = 82k.
Vo = -(RF/ R1)* Vin = -(82k/820)*10mVpp = 1Vpp.
10. Analyse the given circuit and determine the correct option
a) Voo VIOB
b) Voo = VIOB
c) Voo >> VIOB
d) Voo << VIOB
View Answer
Answer: c
Explanation: 741op-amp has Vio = 6mvdc and IB =500nA.
The output offset voltage due to input offset voltage is given as Voo =[1+(RF/R1)]*Vio =
[1+(4.7k/47)]*6mv = 0.606v.
The output offset voltage due to input bias current is given as VIOB = RF*IB =4.7k*500nA =
2.35mv.
=> Voo >> VIOB.
11. The specification for LM101A op-amp is given as IB =75nA. Determine the value of VIOB- V1.
a) 0.112v
b) 0.750v
c) 0.374v
d) 0.634v
View Answer
Answer: a
Explanation: The voltage at non-inverting terminal is given as V1 = ROM*IB1 = 148*7.5nA =
1.11v.
=> ROM = (R1*RF)/(R1+ RF) = (15k*150)/(15k+150) =148
The output offset voltage is given as VIOB = RF*IB
=> VIOB = 15k*7.5nA = 112.5mv
=> VIOB- V1 = 0.112v.
The maximum amount by which the two input bias current may differ is known as
a) Input null current
b) Average input bias current
c) Input offset current
d) None of the mentioned
View Answer
2. A 741 type op-amp has a maximum input offset current of 200nA dc. What conclusion can be
derived from this statement?
{ IB1 Input bias current at inverting input terminal and IB2 Input bias current at non-inverting
input terminal}
a) IB1 may be larger than IB2 by 200nA
b) IB2 may be larger than IB1 by 200nA
c) Iio and IB2 may be equal to 200nA
Gain, A=1+(RF/R1)
=> R1 = RF/(A-1) = 15k/(8.5-1) = 2k.
=> ROM =(R1* RF)/( R1+RF) = 1.76k.
The output offset voltage, VOIB1= VOIB= RF*IB
=> VOIB1= 1.76k*200nA*8.5 = 2.910-6 3 v.
a) Iio = |IBA*IBC|
b) Iio = |IBA+ IBC|
c) Iio = |IBA/ IBC|
d) Iio = |IBA- IBC|
View Answer
Answer: d
Explanation: the input offset current is Iio = |IBA- IBC|.
6. Determine the maximum output offset voltage caused by input offset current
a) 5.4mv
b) 7.3mv
c) 6.9mv
d) 8.1mv
View Answer
Answer: a
Explanation: For a 741 op-amp, Iio = 200nA(Maximum).
=> Therefore, VOIio = RF*Iio = 27k*200nA =5.4mv.
Which factor affect the input offset voltage, bias current and input offset current in an op-amp
a) Change in temperature
b) Change in supply voltage
c) Change in time
d) All of the mentioned
View Answer
Answer: d
Explanation: Any change in the mentioned parameters affect the values of input offset voltage,
bias current and input offset current from remaining constant.
2. Thermal voltage drift is defined as
a) Vio/T
b) VF/T
c) Iio/T
d) IB/T
View Answer
Answer: a
Explanation: The average rate of change of input offset voltage per unit change in temperature is
called thermal voltage drift, i.e. Vio/T.
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3. A completely compensated inverting amplifier is nulled at room temperature 25oC, determine
the temperature at which the total output offset voltage will be zero?
a) 50oC
b) 25oC
c) 75oC
d) 125oC
View Answer
Answer: b
Explanation: When amplifier is nulled at room temperature, the effect of input offset voltage and
current is reduced to zero. Change in the total output offset voltage occurs only, if there is any
change in the value of Vio and Iio. Therefore, the total output offset voltage will be zero at room
temperature.
4. How the effect of voltage and current drift on the performance of an amplifier is determined?
a) VooT/T = {[1-RF/R1)](Vio/T)} + RF(Iio/t)
b) VooT/T = {(-RF/R1)(Vio/T)} + RF(Iio/t)
c) VooT/T = {[1+(RF/R1)](Vio/T)} + RF(Iio/t)
a) +0.53v or -0.68v
b) +0.52v or -0.78v
c) +0.54v or -0.90v
d) +0.51v or -0.86v
View Answer
Answer: d
Explanation: Change in temperature T = 50oC-27oC = 23oC.
=> Error voltage, Ev =[1+(RF/R1)](Vio/T)T + RF(Iio/T)T =
[1+(100k/1k)](30v/1oC) 23oC + 100k(300pA/1oC) 23oC = 0.06969+ 6.910-9
=> Ev= 0.0704 = 70.4mv.
For an input voltage of 6.21mv dc, the output voltage,
Vo=-(RF/R1)VinEv = -(100k/1k)6.21mv70.4mv = +0.69v or -0.55v.
8.
The error voltage for the above circuit is 0.93v. Compute the output voltage?
a) None of the mentioned
b) +17v or -15v
c) -17v or +15v
d) +15v to +17v
View Answer
Answer: b
Explanation: The output voltage for the non-inverting amplifier is
Vo=[1+(RF/R1+R2)]VinEv
= [1+(50k/3k+10k)]3.30.93v = 15.990.93
=> Vo = +16.92v or -15.06v +17v or -15v.
How to obtain a desired amount of multiplication in frequency multiplier?
a) By decreasing the multiplication factor
b) By increasing the input frequency
c) By selecting proper divide by N-network
d) None of the mentioned
View Answer
Answer: c
Explanation: The desired amount of multiplication can be obtained by properly selecting a divide
by N-network. For example, to obtain the output frequency fout=5fin, a divide by N = 5 network
is needed.
2. Calculate the output frequency in a frequency multiplier if, fin = 200Hz is applied to a 7 divide
by N-network.
a) 1.2kHz
b) 1.6kHz
c) 1.2kHz
d) 1.9kHz
View Answer
Answer: c
Explanation: Since the VCO is actually running at a multiple of input frequency. fout=divide by
N-network x fin=7x200Hz=1400Hz
=>fout=1.4kHz.
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3. For what kind of input signal, the frequency divider can be avoided frequency multiplier?
a) Triangular waveform
b) Square waveform
c) Saw tooth waveform
d) Sine waveform
View Answer
Answer: a
Explanation: VCO can be directly locked to the nth harmonic of the input signal without
connecting any frequency divider in between the input signal rich in harmonics like square wave.
4. What must the typical value of n for a frequency multiplication / division? (n->order of
harmonics)
a) n 12
b) n >11
c) n <10
d) n =7
View Answer
Answer: d
Explanation: As the amplitude of the higher order harmonics becomes less, effective locking may
not take place for high values of n. So, the typical value of n is less than 10 for frequency
multiplication / division.
5. Determine the offset frequency of frequency translation, when the output and input frequency
are given as 75kHz and 1000Hz.
a) 35 kHz
b) 20 kHz
c) 29 kHz
d) 14 kHz
View Answer
Answer: b
Explanation: The output of the frequency translation fo= fs+f1
=> f1 = fo- fs= 75kHz-55kHz =20kHz.
6. The frequency corresponding to logic 1 state in FSK is called
a) Space frequency
b) Mark frequency
c) Both mark and space frequency
d) None of the mentioned
View Answer
Answer: b
Explanation: Frequency shift is usually accomplished by dividing a VCO with binary data signal.
Therefore, the logic 1 state of the binary data signal corresponds to mark frequencies.
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7. Find the frequency shift in FSK generator?
a) 230 Hz
b) 250 Hz
c) 180 Hz
d) 200 Hz
View Answer
Answer: d
Explanation: Frequency shift is the difference between FSK signals of 1070 Hz and 1270 Hz
frequency, which is 200 Hz.
8. Which filter is chosen to remove the carrier component in the frequency shift keying?
a) Three stage filter
b) Two stage filter
c) Single stage filter
d) All of the mentioned
View Answer
Answer: a
Explanation: The high cut-off frequency of ladder filter is chosen to be approximately halfway
between the maximum keying rate of 150Hz & twice the input frequency ( 2200Hz) which can
be obtained using three stage filters.
What is the conversion ratio of the phase detector in 565 PLL?
a) 0.14
b) 0.35
c) 0.4458
d) 0.7
View Answer
Answer: c
Explanation: The conversion ratio of the phase detector of 565 PLL (Monolithic PLL) K = 1.4/
= 0.4458.
2. Given fo = 1.2kHz and V = 13v, find the lock-in range of monolithic Phase-Locked Loop.
a) 575Hz
b) 720Hz
c) 150Hz
d) 1kHz
View Answer
Answer: b
Explanation: The lock-in range of monolithic PLL, fL = (7.8fo)/V = (7.81.2kHz)/13 =
720Hz.
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3. Find out the incorrect statement.
Monolithic phase detector is preferred for critical applications as it is:
1. Independent of variation in amplitude
2. Independent of variation in duty cycle of the input waveform
3. Independent of variation in response time
a) 1 & 2
b) 1 & 3
c) 2 & 3
d) 1, 2 & 3
View Answer
Answer: a
Explanation: Monolithic phase detectors are not sensitive to harmonics of the input signal and
change in duty cycle of input and output frequency.
4. Determine the capture range of IC PLL 565 for a lock-in range of 1kHz.
a) fc = 31.453Hz
b) None of the mentioned
c) fc = 87.653Hz
d) fc = 66.505Hz
View Answer
Answer: d
Explanation: The capture range is fc = [fL/ (23.6103C]0.5 = [1kHz/
(23.6k10F)]0.5 = [1kHz/226.08-6]0.5 = [4423]0.5 = 66.505Hz.
5. Find the lock-in range of monolithic Phase-Locked Loop from the given diagram.
a) -fo-fL to fo-fL
b) -fo-fL to -fo-fC
c) fo-fL to fo-fC
d) -fo-fC to fo-fC
View Answer
Answer: a
Explanation: Lock-in range of monolithic PLL is from -fo-fL to fo-fL.
Variation in the operating frequency of op-amp causes
a) Variation in gain amplifier
b) Variation in gain phase angle
c) Variation in gain amplitude and its phase angle
d) None of the mentioned.
View Answer
Answer: c
Explanation: The gain of the op-amp is a function of frequency. It will have a specific magnitude
as well as a phase angle.
2. A graph of the magnitude of the gain versus frequency is called
a) Break frequency
b) Frequency response plot
c) Frequency stability plot
d) Transient response plot
View Answer
Answer: b
Explanation: A frequency response plot is obtained by plotting the gain of the op-amp responding
to different frequencies.
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3. In the frequency response plot, the frequency is expressed in
a) Anti-logarithmic scale
b) Logarithmic scale
c) Linear scale
d) Exponential scale
View Answer
Answer: b
Explanation: To accommodate large frequency ranges the frequency is assigned to a logarithmic
scale.
4. Why the gain magnitude in frequency response plot is expressed in decibels (dB)
a) To obtain gain > 105
b) To obtain gain < 105
c) To obtain gain = 0
d) To obtain gain =
View Answer
Answer: a
Explanation: In frequency response plot, gain magnitude is assigned a linear scale and is
expressed in decibels to accommodate very high gain ( of the order 105 or higher).
5. Which technique is used to determine the stability of op-amp?
a) Frequency response plot
b) Transient response plot
c) Bode plot
d) All of the mentioned
View Answer
Answer: c
Explanation: Although frequency response and bode plots indicate the effect of frequency
variation on gain, the Bode plot is generally used for stability determination and network design.
6. How many types of plots can be obtained in the AC analysis of network using Bode plot?
a) Five
b) Four
c) three
d) Two
View Answer
Answer: d
Explanation: Two types of plots can be obtained using Bode plot. They are magnitude versus
frequency and phase angle versus frequency plots.
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7. What happens when the operating frequency of an op-amp increase?
a) Gain of the amplifier decrease
b) Phase shift between output and input signal decrease
c) Gain and phase shift of amplifier decreases.
d) Op-amp 741
View Answer
Answer: c
Explanation: Op-amp 709 is a first generation op-amp. Generally first generation op-amp are
required for external compensating network.
12. IC 741c op-amp belongs to
a) None of the mentioned
b) Uncompensated op-amp
c) Non-compensated op-amp
d) Compensated op-amp
View Answer
Answer: d
Explanation: 741c belongs to later generation op-amp and it has internal compensating network.
In internal compensated op-amp, the compensating network is designed into the circuit to control
the gain and phase shift of the op-amp and they are called as compensating op-amp.
13. Find out the non-compensating op-amp from the given circuit
View Answer
Answer: c
Explanation: Non-compensating op-amp has external compensating components, that is ,
resistors and / or capacitors, are added at designated terminals. The mentioned op-amp has three
compensating components: a resistor and two capacitors.
Open loop op-amp configuration has
a) Direct network between output and input terminals
b) No connection between output and feedback network
c) No connection between input and feedback network
d) All of the mentioned
View Answer
Answer: a
Explanation: In an open loop configuration, the output signal is not fed back in any form as part
of the input signal and the loop that would have been formed with feedback is open.
2. In which configuration does the op-amp function as a high gain amplifier?
a) Differential amplifier
b) Inverting amplifier
c) Non-inverting amplifier
d) All of the mentioned
View Answer
Answer: d
Explanation: An op-amp functions as a high gain amplifier when connected in open loop
configuration. These three are the open loop configuration of an op-amp.
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3. How does the open loop op-amp configuration classified?
a) Based on the output obtained
b) Based on the input applied
c) Based on the amplification
d) Based on the feedback network
View Answer
Answer: b
Explanation: Open loop configurations are classified according to the number of inputs used and
the terminal to which the input is applied when a single input is used.
4. What will be the voltage drop across the source resistance of differential amplifier when
connected in open loop configuration?
a) Zero
b) Infinity
c) One
d) Greater than one
View Answer
Answer: a
Explanation: The source resistances are normally negligible compared to the input resistance.
Therefore, the voltage drop across input resistors can be assumed to be zero.
5. The output voltage of an open-loop differential amplifier is equal to
a) Double the difference between the two input voltages
b) Product of voltage gain and individual input voltages
c) Product of voltage gain and the difference between the two input voltages
d) Double the voltage gain and the difference between two input voltages
View Answer
Answer: c
Explanation: The output voltage is equal to the voltage gain times the difference between the two
input voltages.
Which filter type is called a flat-flat filter?
a) Cauer filter
b) Butterworth filter
c) Chebyshev filter
d) Band-reject filter
View Answer
Answer: b
Explanation: The key characteristic of the butterworth filter is that it has a flat pass band as well
as stop band. So, it is sometimes called a flat-flat filter.
2. Which filter performs exactly the opposite to the band-pass filter?
a) Band-reject filter
b) Band-stop filter
c) Band-elimination filter
d) All of the mentioned
View Answer
Answer: d
Explanation: A band reject is also called as band-stop and band-elimination filter. It performs
exactly the opposite to band-pass because it has two pass bands: 0 < f < fL and f > fH.
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3. Given the lower and higher cut-off frequency of a band-pass filter are 2.5kHz and 10kHz.
Determine its bandwidth.
a) 750 Hz
b) 7500 Hz
c) 75000 Hz
d) None of the mentioned
View Answer
Answer: b
Explanation: Bandwidth of a band-pass filter is Bandwidth= fH- fL=10kHz2.5kHz=7.5kHz=7500Hz.
4. In which filter the output and input voltages are equal in amplitude for all frequencies?
a) All-pass filter
b) High pass filter
c) Low pass filter
d) All of the mentioned
View Answer
Answer: a
Explanation: In all-pass filter, the output and input voltages are equal in amplitude for all
frequencies. This filter passes all frequencies equally well and with phase shift and between the
two function of frequency.
5. The gain of the first order low pass filter
a) Increases at the rate 20dB/decade
b) Increases at the rate 40dB/decade
c) Decreases at the rate 20dB/decade
d) Decreases at the rate 40dB/decade
View Answer
Answer: c
Explanation: The rate at which the gain of the filter changes in the stop band is determined by the
order of filter. So, for a low pass filter the gain decreases at the rate of 20dB/decade.
6. Which among the following has the best stop band response?
a) Butterworth filter
b) Chebyshev filter
c) Cauer filter
d) All of the mentioned
View Answer
Answer: c
Explanation: The cauer filter has a ripple pass band and a ripple stop band. So, generally cauer
filter gives the best stop band response among the three.
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7. Determine the order of filter used, when the gain increases at the rate of 60dB/decade on the
stop band.
a) Second-order low pass filter
b) Third-order High pass filter
c) First-order low pass filter
d) None of the mentioned
View Answer
Answer: b
Explanation: The gain increases for high pass filter. So, for a third order high pass filter the gain
increases at the rate of 60dB/decade in the stop band until f=fL.
8. Name the filter that has two stop bands?
a) Band-pass filter
b) Low pass filter
c) High pass filter
d) Band-reject filter
View Answer
Answer: a
Explanation: A band-pass filter has two stop bands: 1) 0 < f < fL and 2) f > fH.
9. The frequency response of the filter in the stop band.
i. Decreases with increase in frequency
ii. Increase with increase in frequency
iii. Decreases with decrease in frequency
iv. Increases with decrease in frequency
a) i and iv
b) ii and iii
c) i and ii
d) ii and iv
View Answer
Answer: c
Explanation: The order of frequency of the filter in the stop band determines either steady
decreases or increases or both with increase in frequency.
How many types of band elimination filters are present
a) Three
b) Two
c) Four
d) None of the mentioned
View Answer
Answer: b
Explanation: Band-reject filters are also called as band elimination filters. They are classified
into two types.
i) Wide band-reject filter and
ii) Narrow band-reject filter.
A narrow band-reject filter is commonly called as
a) Notch filter
c) Telephone wire
d) None of the mentioned
View Answer
Answer: c
Explanation: When signals are transmitted in transmission lines like telephone wire, they
undergo change in phase, all-pass filters are used to compensate these phase changes.
9. Determine the output voltage for all the all-pass filter and express it in complex form?
a) VO =Vin/ [(1-j2fRC) /(1+ j2fRC)]
b) VO =Vin [(1+j2fRC) /(1- j2fRC)]
c) VO =Vin [(1- j2fRC) /(1+ j2fRC)]
d) None of the mentioned
View Answer
Answer: c
Explanation: The output voltage of all-pass filter is given as VO =Vin [(1-j2fRC) /(1+j2fRC)] .
10. Determine the input frequency for all-pass filter with phase angle as 62o. Consider the value
of resistor and capacitor are 3.3k and 4.7F.
a) Input frequency= -7.65Hz
b) Input frequency= -6.77Hz
c) Input frequency= -3.89Hz
d) Input frequency= -9.65Hz
View Answer
Answer: d
Explanation: The phase angle is given as = -2tan-1(2fRC)
=> f=-tan/4RC =-tan(62o)/(43.3k4.7F)= -1.88/0.1948 =-9.65Hz.
The voltage gain magnitude of all-pass filter is
a) Zero
b) One
c) Infinity
d) None of the mentioned
View Answer
Answer: b
Explanation: The magnitude of voltage gain of all-pass filter |VO /Vin| = (1+(2/RC)2) / (1+(2
/RC)2) =1
Choose the incorrect statement In wide band-reject filter .
a) Low cut-off frequency of low pass filter must be larger than the high cut-off frequency of the
high pass filter.
b) Low cut-off frequency of high pass filter must be equal than the high cut-off frequency of the
8. Compute the quality factor of the wide band-pass filter with high and low cut-off frequencies
equal to 950Hz and 250Hz.
a) 0.278
b) 0.348
c) 0.696
d) 0.994
View Answer
Answer: c
Explanation: Quality factor Q=(fhfL)/(fh-fL) = (950Hz250Hz)/(9950Hz-250Hz) =0.696.
9. The details of low pass filter sections are given as fh =10kHz, AF= 2 and f=1.2kHz. Find the
voltage gain magnitude of first order wide band-pass filter, if the voltage gain magnitude of high
pass filter section is 8.32dB.
a) 48.13dB
b) 10.02dB
c) 14.28dB
d) 65.99dB
View Answer
Answer: c
Explanation: |VO/Vin|(high pass filter) = 8.32dB=10(8.32/20) =2.606.
Therefore, the voltage gain of wide band-pass filter |VO/Vin|= AFt(f/fL)/[1+(f/fh)2)][1+(f/fL)2)]
={Af/[(1+(f/fh)2]}{(Aff/fL)/[1+(f/fL)2]} =Aft /[1+(f/fh)2](2.606)
= [2/(1+(1.2kHz/10kHz)2]( 2.606) = 1.9862.606 =5.17 =20log(5.17) =14.28dB.
10. The quality factor of a wide band-pass filter can be
a) 12.6
b) 9.1
c) 14.2
d) 10.9
View Answer
Answer: b
Explanation: A wide band-pass filter has quality factor less than 10.
If the gain at center frequency is 10, find the quality factor of narrow band-pass filter
a) 1
b) 2
c) 3
d) None of the mentioned
View Answer
Answer: c
Explanation: The gain of the narrow band-pass filter must satisfy the condition, AF= 2Q2
When Q=3,
Answer: a
Explanation: At audio frequencies, inductor becomes problematic, as the inductors become large,
heavy and expensive.
4. The problem of passive filters is overcome by using
a) Analog filter
b) Active filter
c) LC filter
d) A combination of analog and digital filters
View Answer
Answer: b
Explanation: The active filters enclose as a capacitor in the feedback loop and avoid using
inductors, this way inductorless active filter are obtained.
5. What happens if inductors are used in low frequency applications?
a) Enhance inductor usage
b) No losses occurs
c) Degrades inductor performance
d) Low power dissipation
View Answer
Answer: c
Explanation: For low frequency applications more number of turns of wire must be used, which
in turn adds to the series resistance degrading inductors performance.
6. Find out the incorrect statement about active and passive filters.
a) Gain is not attenuated in active filter
b) Passive filters are less expensive
c) Active filter does not cause loading of source
d) Passive filters are difficult to tune or adjust
View Answer
Answer: b
Explanation: Typically active filters are more economical than passive filters. This is because of
the variety of cheaper op-amp and the absence of inductors.
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7. What are the most commonly used active filters?
a) All of the mentioned
b) Low pass and High pass filters
c) Band pass and Band reject filters
d) All-pass filters
View Answer
Answer: a
Explanation: All the mentioned filters use op-amp as active element and capacitors & resistors as
passive elements.
8. Choose the op-amp that improves the filter performance.
a) A741
b) LM318
c) LM101A
d )MC34001
View Answer
Answer: b
Explanation: LM318 is a high speed op-amp that improves the filters performance through
increased slew rate and higher unity gain-bandwidth.
9. Ideal response of filter takes place in
a) Pass band and stop band frequency
b) Stop band frequency
c) Pass band frequency
d) None of the mentioned
View Answer
Answer: c
Explanation: The ideal response indicates the practical filter response and it lies within the pass
band frequencies.
10. Find out the low pass filter from the given frequency response characteristics.
View Answer
Answer: a
Explanation: A low pass filter has a constant gain from 0Hz to high cut-off frequency fH.
Select the specifications that implies the inverting amplifier?
a) V1 = -3v, V2 = -4v
b) V1 = -2v, V2 = 3v
c) V1 = 5v, V 2 = 15v
d) V1 = 0v, V2 = 5v
View Answer
Answer: d
Explanation: In inverting amplifier, the input is applied to the inverting terminal and the noninverting terminal is grounded. So,the input applied to inverting amplifier can be V1 = 0v, V2 =
5v.
10. Find the non-inverting amplifier configuration from the given circuit diagram?
View Answer
Answer: c
Explanation: In a non-inverting amplifier, the input is applied to the non-inverting input terminal
and the inverting terminal is connected to ground.
11. What happen if any positive input signal is applied to open-loop configuration?
a) Output reaches saturation level
b) Output voltage swings peak to peak
c) Output will be a sine waveform
d) Output will be a non-sinusoidal waveform
View Answer
Answer: a
Explanation: In open-loop configuration, due to very high gain of the op-amp, any input signal
slightly greater than zero drives the output to saturation level.
12. Why open-loop op-amp configurations are not used in linear applications?
a) Output reaches positive saturation
b) Output reaches negative saturation
c) Output switches between positive and negative saturation
a) i and iv
b) ii and iii
c) i and ii
d) ii and iv
View Answer
Answer: c
Explanation: The order of frequency of the filter in the stop band determines either steady
decreases or increases or both with increase in frequency.
Free running multivibrator is also called as
a) Stable multivibrator
b) Voltage control oscillator
c) Square wave oscillator
d) Pulse stretcher
View Answer
Answer: b
Explanation: Free running multivibrator operates at a frequency which is determined by an
external tuning capacitor and a resistor. On applying a dc control voltage the frequency can be
shifted on either sides. This frequency deviation is directly proportional to the dc control voltage
and hence it is called as voltage controlled oscillator.
2. The output voltage of phase detector is
a) Phase voltage
b) Free running voltage
c) Error voltage
d) None of the mentioned
View Answer
Answer: c
Explanation: The phase detector compares the input frequency with the feedback frequency and
produces output dc voltage called as error voltage.
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3. At which state the phase-locked loop tracks any change in input frequency?
a) Free running state
b) Capture state
c) Phase locked state
d) All of the mentioned
View Answer
Answer: c
Explanation: In the phase-locked, the output frequency is exactly same as the input signal
frequency. So the circuit tracks any change in the input frequency through its repetitive action.
Answer: d
Explanation: The pull-in time depends on the above mentioned characteristics to establish lock in
the PLL circuit.
Open loop bandwidth of an op-amp extend its bandwidth from
a) 0Hz to fo
b) 20dB to fo
c) 3dB to fo
d) 0.704dB to fo
View Answer
Answer: a
Explanation: The gain of the op-amp remains essentially constant from 0 to the break frequency
fo and therefore rolls off at a constant rate of 20dB per decade. Thus, the open-loop bandwidth is
the frequency band extending from 0Hz to fo.
2. What happens if 741 op-amp is configured as a closed loop inverting amplifier?
a) Gain increases
b) Gain roll-off at a rate 20dB/decade
c) No gain roll-off takes place
d) Gain decreases
View Answer
Answer: b
Explanation: Whether the op-amp is inverting / non-inverting the gain will always roll-off at a
rate of 20dB/decade, using only resistive components regardless of the value of its closed loop
gain.
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3. Op-amp requiring external compensating components is called as
a) Tailored frequency response op-amp
b) Compensating op-amp
c) Transient op-amp
d) High frequency op-amp
View Answer
Answer: a
Explanation: Op-amp using external components like resistor and capacitor to form the
compensating network are sometimes called tailored frequency response op-amps because the
user has to provide the compensation if it is needed to tailor the response.
4. In the first generation op-amp 709c, the open loop bandwidth of gain versus frequency curve
a) Increases from the innermost compensated curve to the outermost
b) Decrease from the innermost compensated curve to the outermost
c) Increases from the outermost compensated curve to the innermost
View Answer
Answer: a
Explanation: In VCO, the output of Schmitt trigger is fed to the input of inverter. Therefore, the
output at pin3 would be an inverted output. As the input is a square wave, the output obtained
will be an inverted square wave.
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3. Write the equation for time period of VCO?
a) (2VccCT)/i
b) (Vcc CT)/(2i)
c) (VccCTi)/2
d) (2Vcc)/(iCT)
View Answer
Answer: b
Explanation: The time period of VCO is given as T=2t =(20.25Vcc CT)/i =(0.5 VccCT)/i
= (VccCT)/(2i).
4. Determine the value of current flow in VCO, when the NE566 VCO external timing resistor
RT =250 and the modulating input voltage Vc=3.25V.(Assume Vcc=+5v).
a) 3mA
b) 12mA
c) 7mA
d) 10mA
View Answer
Answer: c
Explanation: Current flowing in VCO, i =(Vcc- Vc)/ RT = (5V-3.25V)/250 = 1.75/250
=>i =7mA.
a) 178.484 Hz
b) 104.84 Hz
c) 145.84 Hz
d) 110.88 Hz
View Answer
Answer: b
Explanation: Output frequency, fo =[2(Vcc- Vc) ]/(CTRTVcc )= [2x(8-1.5)]/(0.47Fx33kx8v)
=13/0.124
=> fo=104.84 Hz.
6. The output frequency of the VCO can be changed by changing
a) External tuning resistor
b) External tuning capacitor
c) Modulating input voltage
d) All of the mentioned
View Answer
Answer: d
Explanation: The output frequency of VCO, fo = [2(Vcc- Vc)]/(CTRTVcc).
From the equation, it is clear that the fo is inversely proportional to CT & RT and directly
proportional to Vc.Therefore, the output frequency can be changed by changing either voltage
control, CT or RT.
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7. Calculate the value of external timing capacitor, if no modulating input signal is applied to
VCO. Consider fo=25 kHz and RT=5 k.
a) 6nF
b) 100F
c) 2nF
d) 10nF
View Answer
Answer: c
Explanation: When modulating input signal is not applied to VCO, the output frequency
becomes fo=1/(4RTCT)
=> CT =1/(4RTfo) =1/(45k25kHz) = 210-9 =2nF.
8. What is the advantage of using filter?
a) High noise immunity
b) Reduce the bandwidth of PLL
c) Provides dynamic range of frequencies
d) None of the mentioned
View Answer
Answer: a
Explanation: The charge on the filter capacitor gives a short time memory to the PLL. So, even if
the signal becomes less than the noise for a few cycles, the dc voltage on the capacitor continues
to shift the frequency of VCO, till it picks up the signal again. This produces high noise
immunity.
View Answer
Answer: d
Explanation: The loop filter used in the VCO can be one of the three types of filter shown above.
10. Choose the VCO for attaining higher output frequency.
a) NE566
b) SE566
c) MC4024
d) All of the mentioned
View Answer
Answer: c
Explanation: MC4024 is used for attaining high output frequency, because the maximum output
frequency of NE566 and SE566 is 500kHz.
11. Voltage to frequency conversion factor for VCO is
a) Kv = Vc/ fo
b) Kv = fo/Vc
c) Kv = fo Vc
d) Kv = 1/(foVc)
View Answer
Answer: b
Explanation: The voltage to frequency conversion factor is defined as the change in frequency to
the change in modulating input voltage.
=> Kv=fo/Vc.
12. Calculate the voltage to frequency conversion factor, where fo=155Hz and Vcc=10V.
a) 130
b) 124
c) 134
d) 116
View Answer
Answer: b
Explanation: The voltage to frequency conversion factor, Kv = fo/Vcc= 8fo/Vcc =
(8155)/10=124.
13. Find the equation for change in frequency of VCO?
a) fo = (2Vc)/(RTCTVcc)
b) fo = Vc/(4RTCTVcc)
c) fo = Vc/(2RTCTVcc)
d) fo = (4Vc)/(RTCTVcc)
View Answer
14. Using the given specifications, determine the voltage to frequency conversion factor.
a) 8.32
b) 8.90
c) 8.51
d) 8.75
View Answer
Answer: c
Explanation: fo = 2Vc/(RTCTVcc)
=>Vc= (foRTCTVcc)/2 = (4.7Fx10kx5x112)/2 = 13.16V.
Kv= fo/ Vc = 112Hz/13.16V
=>Kv=8.51.
To obtain a faster slew rate the op-amp should have
a) High current and large compensating capacitor
b) Small compensating capacitor
c) High current or small compensating capacitor
d) Low current or large compensating capacitor
View Answer
Answer: c
Explanation: The slew rate is given as, SR =dVc/dt|max = I/C
Therefore the higher current should be given a small compensating capacitor is used internally or
outside an op-amp.
2. Find the expression for full power response.
a) fmax(Hz) =(slew rate106)/(6.28Vm)
b) fmax(Hz) =slew rate /(628106Vm)
c) fmax(Hz) =(slew rateVm106)/6.28
d) fmax(Hz) =(6.28Vm 106)/ slew rate
View Answer
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3. Calculate the time taken by the output to swing from +14v to -14v for a 741C op-amp having a
slew rate of 0.5V/s?
a) 22s
b) 42s
c) 56s
d) 70s
View Answer
Answer: c
Explanation: Slew rate = dv/dt
=> Time taken = 14-(-14)/ 0.5V/s = 28v/0.5V/s = 56s.
4. Consider a square wave having a peak to peak amplitude of 275mv and it is amplified to a
peak to peak amplitude of 4v, with rise time of 5.2s. Calculate the slew rate?
a) 0.615 v/s
b) 0.712 v/s
c) 0.325 v/s
d) None of the mentioned
View Answer
Answer: a
Explanation: From the definition of rise time, the change in the output voltage is 5.2s
v= (90%-10%)4v= (0.9-0.1)4v =3.2v.
Therefore, slew rate = 3.2v/5.2s =0.615v/s.
5. Determine the maximum input signal to be applied to an op-amp to get distortion free output.
If the op-amp used is an inverting amplifier with a gain of 50 and maximum output amplitude
obtained is 4.2V sine wave?
a) 159mv
b) 0.168mv
c) 207mv
d) 111mv
View Answer
Answer: b
Explanation: Given, Vm= 4.2Vpeak
the output voltage = 4.2+4.2 =8.4 V peak to peak.
Hence for the output to be undistorted sine wave, the maximum input signal should be less than
=> 8.4/50= 0.168 = 168mVpeak to peak.
6. What happens if the frequency or amplitude of the input signal is increased to exceed slew rate
of the op-amp?
a) All of the mentioned
b) High frequency output
c) Distorted output
d) Large amplitude output
View Answer
Answer: c
Explanation: Slew rate determines the maximum frequency of operation for a desired output
swing. If the slew rate is greater than 2fVm /106 then the output is distorted, whereas an increase
in the frequency /amplitude of input signal distort the output.
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7. Compute the peak output amplitude, when the voltage gain verses frequency curve of 741C is
flat upto 25Hz.
a) 4Vpeak
b) 9Vpeak
c) 20Vpeak
d) None of the mentioned
View Answer
Answer: d
Explanation: The slew rate of 741C op-amp = 0.5V/s. So, the maximum output voltage at
25kHz is SR= (2fVm)/ 106 V/s
=> Vm = (SR106)/(2f ) = (0.5106)/(225kHz)
Vm = 3.18Vpeak.
8. Calculate the maximum input frequency at which the output will be distorted from the given
specifications
Vo = 30 Vpp ; Slew rate = 0.6v/s.
a) 1000Hz
b) 10kHz
c) 1kHz
d) 10kHz
View Answer
Answer: d
Explanation: The minimum time between the two zero crossing is given as
=> 30v/(0.6v/s) =50s. Hence the maximize input frequency fmax at which the output get
distorted is fmax = 1/(250s) =10000 =10kHz.
9. Match AC parameter of the op-amp in column 1 with the column 2.
Column 1
1. Bandwidth
2. Transient
response
3. Slew rate
Column-2
i . a large signal phenomenon
ii. Rise time is related to bandwidth and
overshoots measure stability
iii. Depends on compensating components and
closed loop gain
View Answer
Answer: b
Explanation: The voltage at which A1 switch from +Vsat to -Vsat
=> -Vramp =(-R2 / R3) (+Vsat)
Answer: b
Explanation: Sawtooth waveform has unequal rise and fall times. It may rise positively many
times faster than it falls negatively or vice versa.
9. Find out the sawtooth wave generator from the following circuits.
View Answer
Answer: c
Explanation: The triangular wave generator can be converted into a sawtooth wave generator by
inserting a variable dc voltage into the non-inverting terminal of the integrator.
10. Consider the integrator used for generating sawtooth wave form. Match the list I with the list
II depending on the movement of wiper.
List-I
List-II
a) 1-iii,2-ii,3-i
b) 1-i ,2-ii ,3-iii
c) 1-i, 2-iii, 3-ii
d) 1-ii ,2-iii ,3-i
View Answer
Answer: c
Explanation: Depending on the duty cycle (movement of the wiper) the type of waveform is
determined.
Which circuit is used for obtaining desired output waveform in operational amplifier?
a) Clipper
b) Clamper
c) Peak amplifier
d) Sample and hold
View Answer
Answer: a
Explanation: In an op-amp clipper circuits a rectifier diode is used to clip off certain portions of
the input signal to obtain a designed output waveform.
2. The clipping level in op-amp is determined by
a) AC supply voltage
b) Control voltage
c) Reference voltage
d) Input voltage
View Answer
Answer: c
Explanation: The clipping level is determined by the reference voltage which should be less than
the input voltage range of an op-amp.
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3. In a positive clipper, the diode conducts when
a) Vin < Vref
b) Vin = Vref
c) Vin > Vref
d) None of the mentioned
View Answer
Answer: b
Explanation:In a positive clipper, the diode conducts until Vin = Vref (during the positive half
cycle of the input), because when Vin < Vref, the voltage (Vref) at the negative input is higher than
that at the positive input.
4. What happens if the potentiometer Rp is connected to negative supply?
View Answer
Answer: c
Explanation: The negative portion of the output voltage below -Vref is clipped off because, diode
will be in off condition when Vin < Vref.
6. What happens if the input voltage is higher than reference voltage in a positive clipper?
a) Output voltage = Reference voltage
b) Output voltage = DC Positive voltage
c) Output voltage = Input voltage
d) All of the mentioned
View Answer
Answer: a
Explanation: When input voltage is higher than reference voltage, the op-amp operates in open
loop and diode become reverse biased. Thus, the output voltage will be equal to reference
voltage.
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7. A positive small signal halfwave rectifier can
a) Rectify signals with peak value only
b) Rectify signals with value of few millivolts only
c) Rectify signals with both peak value and down to few millivolts
d) None of the mentioned
View Answer
Answer: c
Explanation: A positive small signal halfwave rectifier can rectify signals with peak values down
to few millivolts, because the high open loop gain of the op-amp automatically adjusts the
voltage drive to the diode, so that the rectified output peak is the same as the input.
8. Determine the output waveform of negative small signal half wave rectifier.
View Answer
Answer: d
Explanation: During the positive alteration of Vin, D1 is reverse biased. Therefore, Vo =0v. On the
other hand, during the negative alteration, D1 is forward biased and hence Vo follows Vin.
9. Diode in small signal positive halfwave rectifier circuit acts as
a) Ideal diode
b) Clipper diode
c) Clamper diode
d) Rectifier diode
View Answer
Answer: a
Explanation: The diode acts as an ideal diode, since the voltage across the ON diode is divided
by the open loop gain of the op-amp. As the input voltage starts increasing in the positive
direction, the output of the op-amp also increases positively till the diode become forward
biased.
10. How to minimize the response time and increase the operating frequency range of the opamp?
a) Positive halfwave rectifier with two diodes
b) Positive halfwave rectifier with one diode
c) Negative halfwave rectifier with two diodes
d) Negative halfwave rectifier with one diode
View Answer
Answer: c
Explanation: Negative halfwave rectifier circuit with two diodes are used so that the output of
the op-amp does not saturate. Thus, minimizes the response time and increases the operating
frequency range.
11. Why a voltage follower stage is connected at the output of the negative small signal half
wave rectifier?
a) Due to Non-uniform input resistance
b) Due to Non-uniform output resistance
c) Due to Uniform output voltage
d) None of the mentioned
View Answer
Answer: b
Explanation: The output resistance of the circuit is non-uniform as it depends on the state of
diode. That is, the output impedance is low when diode is on and high when diode is off.
12. A circuit with a predetermined dc level is added to the output voltage of the op-amp is called
a) Clamper
b) Positive clipper
c) Halfwave rectifier
d) None of the mentioned
View Answer
Answer: a
Explanation: A clamper clamps the output to a desired dc level.
13. Determine the output waveform for a peak amplifier with input =4Vpsinewave and Vref=1V.
View Answer
Answer: a
Explanation: In a peak amplifier the input waveform peak is clamped at Vref.
The output voltage Vo=2Vp+Vref=(24v)+1v = 9v.
14. An op-amp clamper circuit is also referred as
a) DC cutter
b) DC inserter
c) DC lifter
d) DC leveller
View Answer
Answer: b
Explanation: In an op-amp clamper circuit, a pre-determined dc level is deliberately inserted at
the output voltage. For this reason, the clamper is sometimes called as DC inserter.
15. At what values of Ci and Rd a precision clamping can obtained in peak clamper when the time
period of the input waveform is 0.4s?
a) Ci=0.1F and Rd=10k
b) Ci=0.47F and Rd=10k
View Answer
Answer: a
Explanation: When 555 timer is configured in monostable operation, the trigger input is applied
through pin2 whereas, upper comparator threshold (pin6) & discharge (pin7) are shorted and
connected at the output.
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3. How to overcome mistriggering on the positive pulse edges in the monostable circuit?
a) Connect a RC network at the input
b) Connect an integrator at the input
c) Connect a differentiator at the input
d) Connect a diode at the input
View Answer
Answer: c
Explanation: To prevent the mistrigger on positive pulse edges, a resister & capacitor combined
of 10k and 0.001F at the input to form a differentiator
The circuit shows the differentiator to be connected between trigger input and the +VCC.
4. A monostable multivibrator has R = 120k and the time delay T = 1000ms, calculate the value
of C?
a) 0.9F
b) 1.32F
c) 7.5F
d) 2.49F
View Answer
Answer: c
Explanation: Time delay for a monostable multivibrator, T = 1.1RC
=> C = T/(1.1R) = 1000ms/(1.1120k) = 7.57F.
5. Which among the following can be used to detect the missing heart beat?
a) Monostable multivibrator
b) Astable multivibrator
c) Schmitt trigger
d) None of the mentioned
View Answer
Answer: a
Explanation: A monostable multivibrator can be used as a missing pulse detector by connecting a
transistor between trigger inputs. If a pulse misses, the discharge trigger input goes high &
transistor become cut-off and the output goes low. So, this type of circuit can be used to detect
missing heart beat.
6. A 555 timer in monostable application mode can be used for
a) Pulse position modulation
b) Frequency shift keying
c) Speed control and measurement
d) Digital phase detector
View Answer
Answer: c
Explanation: In monostable operation mode, if input trigger pulses are generated from a rotating
wheel, the circuit will determine the wheel speed whenever it drops below a predetermined
value. Therefore, it can be used for speed control and measurement.
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7. How can a monostable multivibrator be modified into a linear ramp generator?
a) Connect a constant current source to trigger input
b) Connect a constant current source to trigger output
c) Replace resistor by constant current source
d) Replace capacitor by constant current source
View Answer
Answer: c
Explanation: The resistor R of the monostable circuit is replaced by a constant current source.
So, that the capacitor is charged linearly and generates ramp signal.
8. Determine time period of linear ramp generator using the specifications
RE = 2.7k, R1 =47k , R2 100k , C= 0.1F, VCC =5v.
a) 8ms
b) 4ms
c) 2ms
d) 1ms
View Answer
Answer: d
Explanation: The time period of the linear ramp generator, T= [(2/3)(VCCRE)(R1+ R2)C]/
{(R1VCC)-[VBE(R1+R2)]}
= {(2/3)5v[2.7k(4.7k+ 100k)](0.1F)}/{[(47k)5v]-[(0.7)(47k+100k)]}
=>T= 132.3/132.100 =1.001510-3 = 1ms.
a) Vo (+) = +10 v
b) Vo (+) = +12v
c) Vo (+) = +7v
d) None of the mentioned
View Answer
Answer: b
Explanation: The voltage at the terminal V1 = (Vp -Vd1) /2
V1 = (12-0.7) /2 = 5.65 v (Vd1= voltage drop across diode=0.7)
Similarly, the voltage at the negative terminal V2 = (Vo -Vd3 ) /2 = (Vo 0.7) /2
Since Vid 0v , V1 = V2
Vo = (5.65 *2 ) + 0.7 = 12v.
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View Answer
4. What is the alternate method to measure the values of non-sinusoidal waveform other than ac
voltmeter?
a) Clipper
b) Clamper
c) Peak detector
d) Comparator
View Answer
Answer: c
Explanation: A conventional ac voltmeter is designed to measure rms value of the pure sine wave
whereas, the peak value of the non-sinusoidal wave forms can be a peak detector.
5. State the condition needed to be satisfied by peak detector for proper operation of circuit.
a) CRd T/10 and CRL 10T
b) CRd 10T and CRL T/10
c) CRd T/10 and CRL 10T
d) CRd 10T and CRL T/10
View Answer
Answer: a
Explanation: For proper operation of the circuit, charging and discharging time constant must
satisfy the following: CRd T/10 and CRL to 10T.
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6. The resistor in the peak detector are used to
a) To maintain proper operation
b) Protect op-amp from damage
c) To get shaped non-sinusoidal waveform
d) None of the mentioned
View Answer
Answer: b
Explanation: The resistor is used to protect the op-amp against the excessive discharge current,
especially when the power supply is switched off.
7. How the recovery time of the op-amp is reduced?
a) Diode is connected at the output of amplifier
b) Load resistor
c) Forward biased diode resistor
d) Discharge capacitor
View Answer
Answer: a
Explanation: The diode connected at the output of op-amp conducts during negative half cycle of
input voltage. Hence, prevent the op-amp from going into negative saturation. This in turn helps
to reduce the recovery time of the op-amp.
8.how to detect the negative peaks of input signals in the peak detector given below?
a) Reversing D1 diode
b) Reversing D1 and D2 diodes
c) Reversing D2 diode
d) Charging the positions of D1 and D2
View Answer
Answer: b
Explanation: The negative peaks of the input signal Vin can be detected by reversing diodes D1
and D2.
9. In the sample and hold circuit, the period during which the voltage across capacitor is equal to
input voltage
a) Sample period
b) Hold period
c) Delay period
d) Charging period
View Answer
Answer: a
Explanation: The time periods of the sample and hold control voltage during which the voltage
across capacitor is equal to the input voltage are called sample period.
10. During which period the op-amps output of sample and hold circuits is processed?
a) None of the mentioned
b) Sample and hold period
c) Sample period
d) Hold period
View Answer
Answer: d
Explanation: Hold period is the period during which the voltage across the capacitor is constant
and the output of the op-amp is processed or observed during hold periods.
a) 0 mv
b) 25 mv
c) 50 mv
d) -25 mv
View Answer
Answer: c
Explanation: Upper threshold voltage, VUT =[R1/(R1+R2)]( +Vsat) = [100k/(56k +100
)](+14v)= +25mv.
Lower threshold voltage VLT = [R1/(R1+ R2)](-Vsat) = [100k /(56k+100)](-14v)= -25 mv.
Hysteresis voltage = VUT-VLT = 25-(-25) = 50mv.
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7. How to limit the output voltage swing only to positive direction?
a) Combination of two zener diodes
b) Combination of zener and rectifier diode
c) All of the mentioned
View Answer
9. A basic op-amp circuit has a zener and rectifier diode connected in the feedback path.
Calculate the maximum positive voltage. Where, zener voltage = 5.1 v and voltage drop across
Answer: b
Explanation: An oscillation is a type of feedback amplifier in which a part of output is fed back
to the input via a feedback circuit.
4. Find the basic structure of feedback oscillator.
a)
b)
c)
d) None of the mentioned
View Answer
Answer: c
Explanation: The above mentioned diagram is the basic structure of feedback oscillator. It
consists of an amplifier, to the external input (vi) is applied and it have a feedback network from
which the feedback signal (vf) is obtained.
5. What is the condition to achieve oscillations?
a) |A|=1
b) A=0o
c) A=multiples of 2
d) All the mentioned
View Answer
Answer: d
Explanation: All the conditions should be simultaneously satisfied to achieve oscillations.
6. What happens if |A|<1
a) Oscillation will die down
b) Oscillation will keep on increasing
c) Oscillation remains constant
d) Oscillation fluctuates
View Answer
Answer: a
Explanation: If |A| becomes less than unity, the feedback signal goes on reducing in each
feedback cycle and oscillation will die down eventually.
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7. How sustained oscillation can be achieved?
a) Maintaining |A| slightly greater than unity
b) Maintaining |A| equal to unity
c) Due to non-linearity of transistor
d) Due to use of feedback network
View Answer
Answer: c
Explanation: When |A| is kept slightly greater than unity the signal, however, cannot go on
increasing and get limited due to non-linearity of the device (that is transistor enters into
saturation). Thus, it is the non-linearity of the transistor because of which the sustained
oscillation can be achieved.
8. Why it is difficult to maintain Barkhausen condition for oscillation?
a) Due to variation in temperature
b) Due to variation in supply voltage
c) Due to variation in components life time
d) All of the mentioned
View Answer
Answer: d
Explanation: The Barkhausen condition |A|=1 is usually difficult to maintain in the circuit as the
value of A and vary due to temperature variations, aging of components, change of supply
voltage etc.
9. Name the type of noise signal present in the oscillation?
a) Schmitt noise
b) Schottky noise
c) Saturation noise
d) None of the mentioned
View Answer
Answer: b
Explanation: Schottky noise is the noise signal always present at the input of the transistor due to
variation in the carrier concentration.
10. A basic feedback oscillator is satisfying the Barkhausen criterion. If the value is given as
0.7072, find the gain of basic amplifier?
a) 2.1216
b) 0.7072
c) 1
d) 1.414
View Answer
Answer: d
Explanation: Barkhausen criterion for oscillation is given as A=1
=> A=1/ = 1/0.7072 = 1.414.
11. The feedback signal of basic sine wave oscillator is given as
a) Vf = A Vo
b) Vf = A Vi
c) Vf = A (Vo/ Vi)
d) Vf = A (Vi/ Vo)
View Answer
Answer: b
Explanation: The feedback signal of an oscillator is given as the product of external applied
signal & the loop gain of the system.
=> Vf= A Vi.
12. Express the requirement for oscillation in polar form
a) A =1360o
b) A =190o
c) A =1o
d) A =1270o
View Answer
Answer: a
Explanation: There are two requirements for oscillation
1. The magnitude of A=1
2. The total phase shift of A=0o or 360o.
Which is not considered as a linear voltage regulator?
a) Fixed output voltage regulator
b) Adjustable output voltage regulator
c) Switching regulator
d) Special regulator
View Answer
Answer: c
Explanation: In linear regulators the impedance of active element may be continuously varied to
supply a desired current to the load. But in the switching regulator, a switch is turned on and off.
2. What is the dropout voltage in a three terminal IC regulator?
a) |Vin| |Vo|+2v
b) |Vin| < |Vo|-2v
c) |V in| = |Vo|
d) |Vin| |Vo|
View Answer
Answer: a
Explanation: The unregulated input voltage must be atleast 2V more than the regulated output
voltage. For example, if Vo=5V, then Vin=7V.
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3. To get a maximum output current, IC regulation are provided with
a) Radiation source
b) Heat sink
c) Peak detector
d) None of the mentioned
View Answer
Answer: b
Explanation: The load current may vary from 0 to rated maximum output current. To maintain
this condition, the IC regulator is usually provided with a heat sink; otherwise it may not provide
the rated maximum output current.
4. For the given circuit, let VEB(ON)=1v, = 15 and IO=2mA. Calculate the load current
a) IL = 23.45A
b) IL = 46.32A
c) IL = 56.87A
d) IL = 30.75A
View Answer
Answer: d
Explanation: The equation for load current, IL = [(+1)IO]-[(VEB(ON)/R1)]=[(15+1)2]
[15(1v/12 )] =32-1.25 =30.75A.
5. Which type of regulator is considered more efficient?
a) All of the mentioned
b) Special regulator
c) Fixed output regulator
d) Switching regulator
View Answer
Answer: d
Explanation: The switching element dissipates negligible power in either on or off state.
Therefore, the switching regulator is more efficient than the linear regulators.
6. State the reason for thermal shutdown of IC regulator?
a) Spikes in temperature
b) Decrease in temperature
c) Fluctuation in temperature
d) Increase in temperature
View Answer
Answer: d
Explanation: The IC regulator has a temperature sensor (built-in) which turn off the IC, when it
becomes too hot (usually 125oC-150oC). The output current will drop and remains there until the
IC has cooled significantly.
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7. Find the difference between output current having a load of 100 and 120 for 7805 IC
regulator. Consider the following specification: Voltage across the load = 5v; Voltage across the
internal resistor= 350mv.
a) 8.4mA
b) 7mA
c) 9mA
d) 3.4mA
View Answer
Answer: a
Explanation: Given the voltage across the internal resistor to be 350mv, which is less than 0.7v.
Hence the transistor in 7805 is off.
When load = 100, IL= IO= Ii= 5v/100 = 50mA
When load=120, IO= 5v/120 = 41.6mA.
So, the difference between the output voltage = 50-41.6mA = 8.4mA.
8. The change in output voltage for the corresponding change in load current in a 7805 IC
regulator is defined as
a) All of the mentioned
b) Line regulation
c) Load regulation
d) Input regulation
View Answer
Answer: c
Explanation: Load regulation is defined as the change in output voltage for a change in load
current and is also expressed in millivolts or as a percentage of output voltage.
9. An IC 7840 regulator has an output current =180mA and internal resistor =10. Find the
collector current in the output using the transistor specification: =15 and VEB(ON) =1.5v.
a) 270mA
b) 450mA
c) 100mA
d) 50mA
View Answer
Answer: b
Explanation: The collector current from transistor, IC= IB
Where, IB= IO-(VEB(ON)/R1) = 180mA-(1.5v-10) = 0.03A.
Therefore, IC= 150.03 = 0.45A = 450mA.
10. How the average temperature coefficient of output voltage expressed in fixed voltage
regulator?
a) miilivolts/oC
b) miilivoltsoC
c) None of the mentioned
d) oC/ miilivolts
View Answer
Answer: a
Explanation: The temperature stability or average temperature coefficient of output voltage, is
the change in the output voltage per unit change in temperature and expressed in miilivolts/oC.
11. In the circuit given below, let VEB(ON)=0.8v and =16. Calculate the output current coming
from 7805 IC and collector current coming from transistor Q1 for a load of 5.
a) 17.17v
b) 34.25v
c) 89.34v
d) 23.12v
View Answer
Answer: a
Explanation: The output voltage, VO =VREF[1=(R2/R1)]+(IADJR2)=1.25Vin [1+(3k/240)] +
( 100A3k )= 16.875 +0.3.
=> VO=17.17v.
13. Compute the input voltage of 7805c voltage regulator with a current source that will deliver a
0.725A current to 65, 10w load. (Assume reference voltage =5v)
a) Vin = 84v
b) Vin = 34v
c) Vin = 54v
d) Vin = 64v
View Answer
Answer: c
Explanation: VO=VREF+VL =VREF+(ILRL) = 5v+(0.725A65) = 52.125v
=> Input voltage, Vin = VO + dropout voltage = 52.125v+2v.
=> Vin 54v.
14. Which of the following is not a characteristic of adjustable voltage regulators?
a) Non-versatile
b) Better performance
c) Increased reliability
d) None of the mentioned
View Answer
Answer: a
Explanation: Adjustable voltage regulators are versatile; it has improved over-load protection
allowing greater output current over operating temperature range.
a) Va > Vd
b) Va Vd
c) Va Vd
d) Va Vd
View Answer
Answer: b
Explanation: When Va < Vd, the output of the comparator becomes low and the AND gate is
disabled. This stops the counting at that time and the digital output of the counter represents the
analog input voltage.
he Integrating type converters are used in
a) Digital meter
b) Panel meter
c) Monitoring system
d) All of the mentioned
View Answer
Answer: d
Explanation: The Integrating type converters are used in application such as digital meter, panel
meter and monitoring system where the conversion accuracy is critical.
4. In integrating type ADCs, the
a) Input voltage is proportional to input averaged over the integration period
b) Output voltage is proportional to input averaged over the integration period
c) Output voltage is proportional to sum of input voltage
d) Input voltage is proportional to sum of input voltage
View Answer
Answer: b
Explanation: Since the integrating type ADC do not require sample and hold circuit at the input.
The change in input during conversion will not affect the output code and is proportional to the
value of the input averaged over the integration period.
5. Which type of ADC is chosen for noisy environment?
a) Successive approximation ADC
b) Dual slope
c) Charge balancing ADC
d) All of the mentioned
View Answer
Answer: c
Explanation: The main advantage of these converters is that it is possible to transmit frequency
even in noisy environment or in isolated form.
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6. How to overcome the drawback of the charge balancing ADC?
a) By using precision integrator
b) By using Voltage to frequency converter
c) By using voltage comparator
d) By using dual slope converter
View Answer
Answer: d
Explanation: Charge balancing ADC depend up on RC product whose value cannot be easily
maintained with temperature and time. This is eliminated using dual slope ADC as it is
independent of R, C and T.
7. Which among the following has long conversion time?
a) Servo converter
b) Dual ramp converter
c) Flash converter
d) None of the mentioned
View Answer
Answer: b
Explanation: The main disadvantage of dual slope ADC is the long conversion time. For
instance, if 2n-T=1/50 is used to reject line pick-up, the conversion time will be 20ms.
8. In which application dual slop converter are used.
a) Thermocouple
b) All of the mentioned
c) Weighting scale
d) Digital panel meter
View Answer
Answer: b
Explanation: Dual slope converters are particularly suitable for accurate measurement of slow
varying signals.
9. A dual slope has the following specifications:
16bit counter; Clock rate =4 MHz; Input voltage=12v; Output voltage =-7v and
Capacitor=0.47F.
If the counters have cycled through 2n counts, determine the value of resistor in the integrator.
a) 60k
b) 50k
c) 120k
d) 100k
View Answer
10. A 12 bit dual ramp generation has a maximum output voltage of +12v. Compute the
equivalent digital number for the analog signal of +6v.
a) 1000000000
b) 10000000000
c) 1000000000000
d) 100000000000
View Answer
Answer: d
Explanation: since Va =VR (N/2n) so the digital count N= 2n(Va/VR)
N= 212(6/12v) = 40960.5 =2048.
Binary equivalent for 2048 => 100000000000.
For the given circuit find the output voltage?
a) -5.625v
b) -3.50v
c) -4.375v
d) -3.125v
View Answer
2. Which type of switches are not preferable for a simple weighted resistor DAC?
a) Bipolar Transistor
b) Voltage switches
c) MOSFET
d) All of the mentioned
View Answer
Answer: a
Explanation: Bipolar transistor does not perform well as voltage switches and MOSFET, due to
the inherent offset voltage when in saturation.
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3. The inverted R-2R ladder can also be operated in
a) Inverted mode
b) Current Mode
c) Voltage mode
d) Non inverted mode
View Answer
Answer: b
Explanation: The inverted mode R-2R ladder circuit works on the principle of summing current.
Therefore, it is said to operate in current mode.
4. Which of among the following circuit is considered to be linear?
a) Weighted Resistor type DAC
b) R-2R ladder type DAC
c) Inverter R-2R ladder DAC
d) All of the mentioned
View Answer
5. Multiplying DAC uses
a) Varying reference voltage
b) Varying input voltage
c) Constant reference voltage
d) Constant input voltage
View Answer
Answer: a
Explanation: A digital to analog converter which uses a varying reference voltage is called a
multiplying D-A converter.
6. Calculate the value of LSB and MSB of a 12-bit DAC for 10v?
a) LSB =7.8mv, MSB =5v
b) LSB =9.3mv, MSB =5v
c) LSB =14.3mv, MSB =5v
a) 1.36v
b) 2.27v
c) 5.45v
d) None of the mentioned
View Answer
Answer: b
Explanation: The output voltage for input 10110111 = 12.4mv [(127)+(026) + (125) + (124)
+ (023)+ (122) +(121)+ (120)] = 12.4 (128+32+16+4+2+1) =12.4mv183=2.27v.
. Express the output voltage of digital to analog converter?
a) Vo =KVFS(d12-1+d22-2+.dn2-n)
b) Vo =VFS/k(d12-1+d22-2+.dn2-n)
c) Vo =VFS(d12-1+d22-2+.dn2-n)
d) Vo =K(d12-1+d22-2+.dn2-n)
View Answer
Answer: a
Explanation: The input is an n-bit binary word D and is combined with the reference voltage VR
to give on analog output signal. Mathematically it is described as
Vo =KVFS(d12-1+d22-2+.dn2-n) where, K -scaling factor, VFS-full scale output voltage.
2. Why the switches used in weighted resistor DAC are of single pole double throw (SPDT)
type?
a) To connect the resistance to reference voltage
b) To connect the resistance to ground
c) To connect the resistance to either reference voltage or ground
d) To connect the resistance to output
View Answer
Answer: c
Explanation: SPDT are electronic switches controlled by a binary word. If the binary input to a
switch is 1, it connects the resistance to the reference voltage and if the input is 0, the switch
connects the resistor to ground.
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3. Determine the output current for an n-bit weighted resistor DAC?
a) (VR/R ) (do/2 +d1/22 + dn/2n)
b) (VR/R ) (d1/21 +d2/22 + dn/2n)
c) (VR/R ) (d02/2 +d12/22 + dn2/2n)
d) None of the mentioned
View Answer
Answer: b
Explanation: The output current, Io= I1+I2+.In
Answer: a
Explanation: For better resolution of output, the input binary word length has to be increased. As
the number of bit increases, the range of resistance value increases.
8. The smallest resistor in a 12 bit weighted resistor DAC is 2.5k, what will be the largest
resistor value?
a) 40.96M
b) 10.24M
c) 61.44 M
d) 18.43M
View Answer
Answer: b
Explanation: The largest resistor value for 12-bit DAC= 2nR = 2122.5k = 40962.5k
=10.24M.
9. CMOS inverter is used as SPDT switch in resistor DAC and is connected to the op-amp line.
Find the output of CMOS, if the input applied is 1
a) Resistance is connected to ground
b) Resistance is connected to input line
c) Resistance is connected to bit line
d) None of the mentioned
View Answer
10. How to overcome the limitation of binary weighted resistor type DAC?
a) Using R-2R ladder type DAC
b) Multiplying DACs
c) Using monolithic DAC
d) Using hybrid DAC
View Answer
Answer: a
Explanation: Usage wide range of resistors is the limitation of binary weighted resistor type
DAC, this can be avoided by using R-2R ladder type DAC Where only two value of resistor are
required.
11. Find output voltage equation for 3 bit DAC converter with R and 2R resistor?
a) Vo= -RF [(b2/8R) +(b1/4R) +(b0/2R)]
b) Vo= -RF [(b2/R) +(b1/2R) +(b0/4R)]
c) Vo= -RF [(b2/2R)+(b1/4R) +(b0/8R)]
d) Vo= -RF [(b0/4R)+(b1/2R) +(b2/R)]
View Answer
Answer: c
Explanation: The output voltage corresponding to all possible combination of binary input in a 3-