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8 GSPS, TxDAC+
Digital-to-Analog Converter
AD9144
Data Sheet
FEATURES
QUAD MOD
ADRF6720
LPF
DAC
0/90 PHASE
SHIFTER
JESD204B
SYNCOUTx
SYSREF
DAC
AD9144
LO_IN
MOD_SPI
QUAD MOD
ADRF6720
QUAD
DAC
LPF
DAC
0/90 PHASE
SHIFTER
JESD204B
SYNCOUTx
LO_IN
MOD_SPI
CLK
DAC
SPI
11675-001
DAC
Figure 1.
APPLICATIONS
Wireless communications
3G/4G W-CDMA base stations
Wideband repeaters
Software defined radios
Wideband communications
Point-to-point
Local multipoint distribution service (LMDS) and
multichannel multipoint distribution service (MMDS)
Transmit diversity, multiple input/multiple output (MIMO)
Instrumentation
Automated test equipment
PRODUCT HIGHLIGHTS
1.
GENERAL DESCRIPTION
The AD9144 is a quad, 16-bit, high dynamic range digital-toanalog converter (DAC) that provides a maximum sample rate
of 2.8 GSPS, permitting a multicarrier generation up to the
Nyquist frequency. The DAC outputs are optimized to interface
seamlessly with the ADRF6720 analog quadrature modulator
(AQM) from Analog Devices, Inc. An optional 3-wire or 4-wire
serial port interface (SPI) provides for programming/readback
of many internal parameters. Full-scale output current can be
programmed over a typical range of 13.9 mA to 27.0 mA. The
AD9144 is available in an 88-lead LFCSP.
Rev. A
2.
3.
4.
5.
6.
Document Feedback
AD9144
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
AC Specifications........................................................................ 10
I to Q Swap .................................................................................. 70
Terminology .................................................................................... 15
Overview...................................................................................... 25
Analog Outputs............................................................................... 79
Interpolation ............................................................................... 29
Data Sheet
AD9144
REVISION HISTORY
6/15Rev. 0 to Rev. A
Changed Functional Block Diagram Section to Typical
Application Circuit Section.............................................................. 1
Changes to Figure 1........................................................................... 1
Changed Detailed Functional Block Diagram Section to
Functional Block Diagram Section ................................................. 4
Deleted Reference Voltage Parameter, Table 1 .............................. 5
Changes to Output Voltage (VOUT) Logic High Parameter,
Output Voltage (VOUT) Logic Low Parameter, and SYSREF
Frequency Parameter, Table 2 .......................................................... 6
Changes to Table 4 ............................................................................ 7
Changes to Interpolation Parameter, Table 6 ................................ 8
Deleted Sync Off, Subclass Mode 0 Parameter, Table 7 ............... 9
Changed Junction Temperature Parameter to Operating
Junction Temperature, Table 10 ....................................................11
Changes to Terminology Section ..................................................15
Changes to Figure 26 Caption .......................................................19
Changes to Figure 29 Caption .......................................................20
Change to Device Revision Parameter, Table 14 .........................24
Changes to Step 1: Start Up the DAC Section, Table 16, and
Table 17 .............................................................................................25
Changes to Step 3: Transport Layer Section and Table 19 .........26
Changes to Table 20 and Table 21 .................................................27
Changes to Step 7: Optional Features Section .............................28
Added Table 25; Renumbered Sequentially .................................29
Changes to DAC PLL Setup Section and Table 26 ......................29
Changes to Lane0Checksum Section ...........................................30
Changes to Table 30 and Subclass 0 Section ................................31
Changes to Table 33 ........................................................................32
Changes to Table 37 ........................................................................35
Changes to Table 38 ........................................................................36
Added SERDES PLL Fixed Register Writes Section and
Table 39 .............................................................................................36
Changes to Figure 38 and Table 40 ...............................................37
Changes to Figure 29 and Data Link Layer Section ...................38
Added Figure 42; Renumbered Sequentially ...............................39
Changes to Figure 44 ......................................................................40
Changes to Continuous Sync Mode (SYNCMOD = 0x2)
Section ..............................................................................................42
Changes to Subclass 0 Section .......................................................43
Changes to Figure 53 ......................................................................50
AD9144
Data Sheet
INV SINC
FSC
NCO
MODE CONTROL
HB1
HB2
HB3
HB1
HB2
HB3
Q-GAIN
I-GAIN
OUT3
Q-OFFSET
PHASE
ADJUST
DACCLK
I-OFFSET
OUT2+
4, 8
FSC
OUT2
COMPLEX
MODULATION
OUT1+
INV SINC
FSC
PDP0
SERDIN0
OUT3+
COMPLEX
MODULATION
HB3
fDAC
VTT
SERDIN7
HB2
PDP1
HB1
NCO
MODE CONTROL
Q-GAIN
I-GAIN
OUT1
Q-OFFSET
PHASE
ADJUST
DACCLK
I-OFFSET
fDAC
HB1
PROTECT_OUT0
PROTECT_OUT1
FSC
PLL_CTRL
SERIAL
I/O PORT
POWER-ON
RESET
DACCLK
OUT0
REF
AND
BIAS
SYSREF
Rx
CLK
Rx
I120
SYSREF+
SYSREF
CLK+
CLK
11675-002
DAC PLL
TXEN1
TXEN0
PLL_LOCK
IRQ
DAC
ALIGN
DETECT
CLK_SEL
CONFIG
REGISTERS
CLOCK DISTRIBUTION
AND
CONTROL LOGIC
RESET
SYNCOUT1+
SYNCOUT1
OUT0+
4, 8
HB3
SYNCHRONIZATION
LOGIC
SDO
SDIO
SCLK
CS
SYNCOUT0+
SYNCOUT0
HB2
Figure 2.
Data Sheet
AD9144
SPECIFICATIONS
DC SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = 40C to +85C, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Gain Error
I/Q Gain Mismatch
Full-Scale Output Current
Maximum Setting
Minimum Setting
Output Compliance Range
Output Resistance
Output Capacitance
Gain DAC Monotonicity
Settling Time
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
REFERENCE
Internal Reference Voltage
ANALOG SUPPLY VOLTAGES
AVDD33
PVDD12
CVDD12
DIGITAL SUPPLY VOLTAGES
SIOVDD33
VTT
DVDD12
Test Conditions/Comments
Min
Typ
16
Max
Unit
Bits
With calibration
1.0
2.0
With internal reference
LSB
LSB
2.5
0.6
+2
+5.5
+0.6
% FSR
% FSR
25.5
13.1
250
27.0
13.9
28.6
14.8
+750
mA
mA
mV
M
pF
0.2
3.0
Guaranteed
20
ns
0.04
32
ppm
ppm/C
1.2
3.13
1.14
1.14
3.3
1.2
1.2
3.47
1.26
1.26
V
V
V
3.13
1.1
3.3
1.2
3.47
1.37
V
V
1.14
1.274
1.2
1.3
1.26
1.326
V
V
1.14
1.274
1.71
1.2
1.3
1.8
1.26
1.326
3.47
V
V
V
1.59
1.84
126
95.3
101
518.2
234
11
36
134
112.4
111
654
255
12
50
mA
mA
mA
mA
mA
mA
A
SVDD12
IOVDD
POWER CONSUMPTION
4 Interpolation Mode,
JESD Mode 4, 8 SERDES Lanes
AVDD33
PVDD12
CVDD12
SVDD12
DVDD12
SIOVDD33
IOVDD
fDAC = 1.6 GSPS, IF = 40 MHz, NCO off, PLL on, digital gain
on, inverse sinc on, DAC FSC = 20 mA
Includes VTT
AD9144
Data Sheet
DIGITAL SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = 40C to +85C, IOUTFS = 20 mA, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input Voltage (VIN) Logic
High
Low
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
0.7 IOVDD
0.3 IOVDD
V
V
0.75 IOVDD
0.25 IOVDD
V
V
1060
2120
2800
2800
MSPS
MSPS
MSPS
MSPS
1 interpolation
2 interpolation
4 interpolation
8 interpolation
1060
1060
700
350
MSPS
MSPS
MSPS
MSPS
INTERFACE4
Number of JESD204B Lanes
JESD204B Serial Interface Speed
Minimum
Maximum
DAC CLOCK INPUT (CLK+, CLK)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
REFCLK Frequency (PLL Mode)
SYSTEM REFERENCE INPUT
(SYSREF+, SYSREF)
Differential Peak-to-Peak
Voltage
Common-Mode Voltage
SYSREF Frequency5
SYSREF TO DAC CLOCK6
Setup Time
Hold Time
Keep Out Window
SPI
Maximum Clock Rate
Minimum SCLK Pulse Width
High
Low
SDIO to SCLK
Setup Time
Hold Time
8
Per lane
Per lane, SVDD12 = 1.3 V 2%
1.44
Gbps
Gbps
2000
1000
mV
mV
MHz
MHz
2000
mV
2000
fDATA/(K S)
mV
Hz
10.6
400
Lanes
1000
600
2800
35
400
1000
0
SYSREF differential swing = 0.4 V, slew
rate = 1.3 V/ns, common modes tested:
ac-coupled, 0 V, 0.6 V, 1.25 V, 2.0 V
tSSD
tHSD
KOW
SCLK
131
119
ps
ps
ps
20
IOVDD = 1.8 V
10
tPWH
tPWL
MHz
8
12
tDS
tDH
5
2
Rev. A | Page 6 of 125
ns
ns
ns
ns
Data Sheet
Parameter
SDO to SCLK
Data Valid Window
CS to SCLK
Setup Time
Hold Time
AD9144
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
tDV
25
ns
tSCS
ns
tHCS
ns
See Table 3 for detailed specifications for DAC update rate conditions.
Maximum speed for 1 interpolation is limited by the JESD interface. See Table 4 for details.
Maximum speed for 2 interpolation is limited by the JESD interface. See Table 4 for details.
4
See Table 4 for detailed specifications for JESD speed conditions.
5
K, F, and S are JESD204B transport layer parameters. See Table 44 for the full definitions.
6
See Table 5 for detailed specifications for SYSREF to DAC clock timing conditions.
2
3
Test Conditions/Comments
DVDD12, CVDD12 = 1.2 V 5%
DVDD12, CVDD12 = 1.2 V 2%
DVDD12, CVDD12 = 1.3 V 2%
Min
2.23
2.41
2.80
Typ
Max
Unit
GSPS
GSPS
GSPS
FULL RATE
OVERSAMPLING
Test Conditions/Comments
SVDD12 = 1.2 V 5%
SVDD12 = 1.2 V 2%
SVDD12 = 1.3 V 2%
SVDD12 = 1.2 V 5%
SVDD12 = 1.2 V 2%
SVDD12 = 1.3 V 2%
SVDD12 = 1.2 V 5%
SVDD12 = 1.2 V 2%
SVDD12 = 1.3 V 2%
Min
5.75
5.75
5.75
2.88
2.88
2.88
1.44
1.44
1.44
Typ
Max
8.92
9.42
10.64
4.63
4.93
5.52
2.31
2.46
2.76
Unit
Gbps
Gbps
Gbps
Gbps
Gbps
Gbps
Gbps
Gbps
Gbps
AD9144
Data Sheet
Test Conditions/Comments
Min
Typ
Max
Unit
AC-coupled
DC-coupled
AC-coupled
DC-coupled
126
131
92
119
ps
ps
ps
ps
AC-coupled
DC-coupled
AC-coupled
DC-coupled
96
104
77
95
ps
ps
ps
ps
AC-coupled
DC-coupled
AC-coupled
DC-coupled
83
90
68
84
ps
ps
ps
ps
Test Conditions/Comments
Min
PClock is the AD9144 internal processing clock and equals the lane rate 40.
Typ
Max
Unit
17
PClock1 cycles
58
137
251
484
17
20
8
4
12
12
60
60
60
s
s
s
Data Sheet
AD9144
Min
Typ
Max
Unit
1
+1
DACCLK cycles
DACCLK cycles
Symbol
Test Conditions/Comments
Min
25C
Input level = 1.2 V 0.25 V, VTT = 1.2 V
Input level = 0 V
UI
VRCM
R_VDIFF
ZTT
ZRDIFF
RLRDIF
RLRCM
VOD
VOS
VOD
94
0.05
110
100
8
6
192
1.19
341
Max
Unit
714
+1.85
1050
30
120
A
A
ps
V
mV
dB
dB
235
1.27
394
mV
V
mV
17
2
PClock3 cycles
PClock3 cycles
DAC clock cycles
10
4
80
Typ
AD9144
Data Sheet
AC SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V,1 VTT = 1.2 V,
TA = 25C, IOUTFS = 20 mA, unless otherwise noted.
Table 9.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 983.04 MSPS
fDAC = 983.04 MSPS
fDAC = 1966.08 MSPS
fDAC = 1966.08 MSPS
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC =983.04 MSPS
fDAC = 983.04 MSPS
fDAC = 1966.08 MSPS
fDAC = 1966.08 MSPS
NOISE SPECTRAL DENSITY (NSD), SINGLE-TONE
fDAC = 983.04 MSPS
fDAC = 1966.08 MSPS
W-CDMA FIRST ADJACENT CHANNEL LEAKAGE
RATIO (ACLR), SINGLE CARRIER
fDAC = 983.04 MSPS
fDAC = 983.04 MSPS
fDAC = 1966.08 MSPS
W-CDMA SECOND ACLR, SINGLE CARRIER
fDAC = 983.04 MSPS
fDAC = 983.04 MSPS
fDAC = 1966.08 MSPS
1
Test Conditions/Comments
9 dBFS single-tone
fOUT = 20 MHz
fOUT = 150 MHz
fOUT = 20 MHz
fOUT = 170 MHz
9 dBFS
fOUT = 20 MHz
fOUT = 150 MHz
fOUT = 20 MHz
fOUT = 170 MHz
0 dBFS
fOUT = 150 MHz
fOUT = 150 MHz
0 dBFS
fOUT = 30 MHz
fOUT = 150 MHz
fOUT = 150 MHz
0 dBFS
fOUT = 30 MHz
fOUT = 150 MHz
fOUT = 150 MHz
Min
Typ
Max
Unit
82
76
81
69
dBc
dBc
dBc
dBc
90
82
90
81
dBc
dBc
dBc
dBc
162
163
dBm/Hz
dBm/Hz
82
80
80
dBc
dBc
dBc
84
85
85
dBc
dBc
dBc
Data Sheet
AD9144
Table 10.
Parameter
I120 to Ground
SERDINx, VTT, SYNCOUT1/
SYNCOUT0, TXENx
OUTx
SYSREF
CLK to Ground
RESET, IRQ, CS, SCLK, SDIO, SDO,
PROTECT_OUTx to Ground
LDO_BYP1
LDO_BYP2
LDO24
Ambient Operating Temperature (TA)
Operating Junction Temperature
Storage Temperature
Rating
0.3 V to AVDD33 + 0.3 V
0.3 V to SIOVDD33 + 0.3 V
0.3 V to AVDD33 + 0.3 V
GND 0.5 V to +2.5 V
0.3 V to PVDD12 + 0.3 V
0.3 V to IOVDD + 0.3 V
0.3 V to SVDD12 + 0.3 V
0.3 V to PVDD12 + 0.3 V
0.3 V to AVDD33 + 0.3 V
40C to +85C
125C
65C to +150C
TJ = TB + (JB P)
where:
TT is the temperature measured at the top of the package.
P is the total device power dissipation.
TB is the temperature measured at the board.
Table 11. Thermal Resistance
Package
88-Lead LFCSP1
1
JA
22.6
JB
5.59
JC
1.17
JT
0.1
JB
5.22
ESD CAUTION
Unit
C/W
AD9144
Data Sheet
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
LDO_BYP2
CVDD12
I120
AVDD33
OUT0+
OUT0
LDO24
CVDD12
LDO24
OUT1
OUT1+
AVDD33
CVDD12
AVDD33
OUT2+
OUT2
LDO24
CVDD12
LDO24
OUT3
OUT3+
AVDD33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AD9144
TOP VIEW
(Not to Scale)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
IOVDD
CS
SCLK
SDIO
SDO
RESET
IRQ
PROTECT_OUT0
PROTECT_OUT1
PVDD12
PVDD12
GND
GND
DVDD12
SERDIN7+
SERDIN7
SVDD12
SERDIN6+
SERDIN6
SVDD12
VTT
SVDD12
NOTES
1. THE EXPOSED PAD MUST BE SECURELY CONNECTED TO THE GROUND PLANE.
11675-003
SYNCOUT0+
SYNCOUT0
VTT
SERDIN2+
SERDIN2
SVDD12
SERDIN3+
SERDIN3
SVDD12
SVDD12
SVDD12
LDO_BYP1
SIOVDD33
SVDD12
SERDIN4
SERDIN4+
SVDD12
SERDIN5
SERDIN5+
VTT
SYNCOUT1
SYNCOUT1+
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PVDD12
CLK+
CLK
PVDD12
SYSREF+
SYSREF
PVDD12
PVDD12
PVDD12
PVDD12
TXEN0
TXEN1
DVDD12
DVDD12
SERDIN0+
SERDIN0
SVDD12
SERDIN1+
SERDIN1
SVDD12
VTT
SVDD12
Mnemonic
PVDD12
CLK+
CLK
4
5
PVDD12
SYSREF+
SYSREF
7
8
9
10
11
12
13
14
15
PVDD12
PVDD12
PVDD12
PVDD12
TXEN0
TXEN1
DVDD12
DVDD12
SERDIN0+
16
SERDIN0
17
18
SVDD12
SERDIN1+
19
SERDIN1
Description
1.2 V Supply. PVDD12 provides a clean supply.
PLL Reference/Clock Input, Positive. When the PLL is used, this pin is the positive reference clock input. When
the PLL is not used, this pin is the positive device clock input. This pin is self biased and must be ac-coupled.
PLL Reference/Clock Input, Negative. When the PLL is used, this pin is the negative reference clock input. When
the PLL is not used, this pin is the negative device clock input. This pin is self biased and must be ac-coupled.
1.2 V Supply. PVDD12 provides a clean supply.
Positive Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It can be ac-coupled or
dc-coupled.
Negative Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It can be ac-coupled or
dc-coupled.
1.2 V Supply. PVDD12 provides a clean supply.
1.2 V Supply. PVDD12 provides a clean supply.
1.2 V Supply. PVDD12 provides a clean supply.
1.2 V Supply. PVDD12 provides a clean supply.
Transmit Enable for DAC0 and DAC1. The CMOS levels are determined with respect to IOVDD.
Transmit Enable for DAC2 and DAC3. The CMOS levels are determined with respect to IOVDD.
1.2 V Digital Supply.
1.2 V Digital Supply.
Serial Channel Input 0, Positive. CML compliant. SERDIN0+ is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
Serial Channel Input 0, Negative. CML compliant. SERDIN0 is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 1, Positive. CML compliant. SERDIN1+ is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
Serial Channel Input 1, Negative. CML compliant. SERDIN1 is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
Rev. A | Page 12 of 125
Data Sheet
Pin No.
20
21
22
23
24
25
26
Mnemonic
SVDD12
VTT
SVDD12
SYNCOUT0+
SYNCOUT0
VTT
SERDIN2+
27
SERDIN2
28
29
SVDD12
SERDIN3+
30
SERDIN3
31
32
33
34
35
36
37
SVDD12
SVDD12
SVDD12
LDO_BYP1
SIOVDD33
SVDD12
SERDIN4
38
SERDIN4+
39
40
SVDD12
SERDIN5
41
SERDIN5+
42
43
44
45
46
47
48
VTT
SYNCOUT1
SYNCOUT1+
SVDD12
VTT
SVDD12
SERDIN6
49
SERDIN6+
50
51
SVDD12
SERDIN7
52
SERDIN7+
53
54
55
56
57
58
59
60
61
DVDD12
GND
GND
PVDD12
PVDD12
PROTECT_OUT1
PROTECT_OUT0
IRQ
RESET
AD9144
Description
1.2 V JESD204B Receiver Supply.
1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.
1.2 V JESD204B Receiver Supply.
Positive LVDS Sync (Active Low) Output Signal Channel Link 0.
Negative LVDS Sync (Active Low) Output Signal Channel Link 0.
1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.
Serial Channel Input 2, Positive. CML compliant. SERDIN2+ is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
Serial Channel Input 2, Negative. CML compliant. SERDIN2 is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 3, Positive. CML compliant. SERDIN3+ is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
Serial Channel Input 3, Negative. CML compliant. SERDIN3 is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
1.2 V JESD204B Receiver Supply.
1.2 V JESD204B Receiver Supply.
LDO SERDES Bypass. This pin requires a 1 resistor in series with a 1 F capacitor to ground.
3.3 V Supply for SERDES.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 4, Negative. CML compliant. SERDIN4 is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
Serial Channel Input 4, Positive. CML compliant. SERDIN4+ is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 5, Negative. CML compliant. SERDIN5 is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
Serial Channel Input 5, Positive. CML compliant. SERDIN5+ is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.
Negative LVDS Sync (Active Low) Output Signal Channel Link 1.
Positive LVDS Sync (Active Low) Output Signal Channel Link 1.
1.2 V JESD204B Receiver Supply.
1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 6, Negative. CML compliant. SERDIN6 is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
Serial Channel Input 6, Positive. CML compliant. SERDIN6+ is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 7, Negative. CML compliant. SERDIN7 is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
Serial Channel Input 7, Positive. CML compliant. SERDIN7+ is internally terminated to the VTT pin voltage
using a calibrated 50 resistor. This pin is ac-coupled only.
1.2 V Digital Supply.
Ground. Connect GND to the ground plane.
Ground. Connect GND to the ground plane.
1.2 V Supply. PVDD12 provides a clean supply.
1.2 V Supply. PVDD12 provides a clean supply.
Power Detection Protection Pin Output for DAC2 and DAC3. Pin 58 is high when power protection is in process.
Power Detection Protection Pin Output for DAC0 and DAC1. Pin 59 is high when power protection is in process.
Interrupt Request (Active Low, Open Drain).
Reset. This pin is active low. CMOS levels are determined with respect to IOVDD.
Rev. A | Page 13 of 125
AD9144
Pin No.
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Mnemonic
SDO
SDIO
SCLK
CS
IOVDD
AVDD33
OUT3+
OUT3
LDO24
CVDD12
LDO24
OUT2
OUT2+
AVDD33
CVDD12
AVDD33
OUT1+
OUT1
LDO24
CVDD12
LDO24
OUT0
OUT0+
AVDD33
I120
CVDD12
LDO_BYP2
EPAD
Data Sheet
Description
Serial Port Data Output. CMOS levels are determined with respect to IOVDD.
Serial Port Data Input/Output. CMOS levels are determined with respect to IOVDD.
Serial Port Clock Input. CMOS levels are determined with respect to IOVDD.
Serial Port Chip Select. This pin is active low; CMOS levels are determined with respect to IOVDD.
IOVDD Supply for CMOS Input/Output and SPI. Operational for 1.8 V IOVDD 3.3 V.
3.3 V Analog Supply for DAC Cores.
DAC3 Positive Current Output.
DAC3 Negative Current Output.
2.4 V LDO. Requires a 1 F capacitor to ground.
1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 71.
2.4 V LDO. Requires a 1 F capacitor to ground.
DAC2 Negative Current Output.
DAC2 Positive Current Output.
3.3 V Analog Supply for DAC Cores.
1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 76.
3.3 V Analog Supply for DAC Cores.
DAC1 Positive Current Output.
DAC1 Negative Current Output.
2.4 V LDO. Requires a 1 F capacitor to ground.
1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 81.
2.4 V LDO. Requires a 1 F capacitor to ground.
DAC0 Negative Current Output.
DAC0 Positive Current Output.
3.3 V Analog Supply for DAC Cores.
Output Current Generation Pin for DAC Full-Scale Current. Tie a 4 k resistor from the I120 pin to ground.
1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 87.
LDO Clock Bypass for DAC PLL. This pin requires a 1 resistor in series with a 1 F capacitor to ground.
Exposed Pad. The exposed pad must be securely connected to the ground plane.
Data Sheet
AD9144
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation of the actual analog output from
the ideal output, determined by a straight line drawn from zero
scale to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Offset Error
Offset error is the deviation of the output current from the ideal
of 0 mA. For OUTx+, 0 mA output is expected when all inputs
are set to 0. For OUTx, 0 mA output is expected when all
inputs are set to 1.
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the difference between
the output when the input is at its minimum code and the
output when the input is at its maximum code.
Output Compliance Range
The output compliance range is the range of allowable voltages
at the output of a current output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Offset drift is a measure of how far from full-scale range (FSR)
the DAC output current is at 25C (in ppm). Gain drift is a
measure of the slope of the DAC output current across its full
ambient operating temperature range, TA, (in ppm/C).
Power Supply Rejection (PSR)
PSR is the maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the peak amplitude
of the output signal and the peak spurious signal within the dc
to Nyquist frequency of the DAC. Typically, energy in this band
is rejected by the interpolation filters. This specification,
therefore, defines how well the interpolation filters work and
the effect of other parasitic coupling paths on the DAC output.
AD9144
Data Sheet
20
40
60
80
60
200
300
400
500
fOUT (MHz)
100
200
300
400
500
fDAC = 1966MHz
fDAC = 2456MHz
MEDIAN
20
100
fOUT (MHz)
11675-107
100
11675-104
0dBFS
6dBFS
9dBFS
12dBFS
20
40
SFDR (dBc)
60
80
40
60
100
100
200
300
400
500
fOUT (MHz)
100
11675-305
100
200
300
400
500
fOUT (MHz)
11675-108
80
fDAC = 983MHz
fDAC = 1228MHz
fDAC = 1474MHz
20
IMD3 (dBc)
40
60
80
40
60
80
100
200
300
fOUT (MHz)
400
500
11675-106
100
Figure 6. Single-Tone Second and Third Harmonics and Maximum Digital Spur
in the First Nyquist Zone, fDAC = 1966 MHz, 0 dB Back Off
100
100
200
300
400
fOUT (MHz)
500
11675-109
SFDR (dBc)
40
80
100
SFDR (dBc)
0dBFS
6dBFS
9dBFS
12dBFS
20
SFDR (dBc)
SFDR (dBc)
fDAC = 983MHz
fDAC = 1228MHz
fDAC = 1474MHz
Data Sheet
0
fDAC = 1966MHz
fDAC = 2456MHz
20
20
40
40
IMD3 (dBc)
60
80
60
80
100
200
300
400
500
fOUT (MHz)
100
11675-110
100
fDAC = 983MHz
fDAC = 1966MHz
100
200
300
400
500
fOUT (MHz)
Figure 13. Two-Tone Third IMD (IMD3) vs. fOUT over Tone Spacing at
0 dB Back Off, fDAC = 983 MHz and 1966 MHz
130
0dBFS
6dBFS
9dBFS
12dBFS
20
11675-113
IMD3 (dBc)
AD9144
fDAC = 983MHz
fDAC = 1228MHz
fDAC = 1474MHz
135
NSD (dBm/Hz)
IMD3 (dBc)
140
40
60
145
150
155
160
80
100
200
300
400
500
fOUT (MHz)
170
300
400
500
500
0dBFS
6dBFS
9dBFS
12dBFS
20
200
fOUT (MHz)
Figure 11. Two-Tone Third IMD (IMD3) vs. fOUT over Digital Back Off,
fDAC = 983 MHz, Each Tone Is at 6 dBFS
0
100
11675-114
11675-111
100
11675-115
165
fDAC = 1966MHz
fDAC = 2456MHz
135
NSD (dBm/Hz)
IMD3 (dBc)
140
40
60
145
150
155
160
80
100
100
200
300
fOUT (MHz)
400
500
11675-112
165
Figure 12. Two-Tone Third IMD (IMD3) vs. fOUT over Digital Back Off,
fDAC = 1966 MHz, Each Tone Is at 6 dBFS
170
100
200
300
400
fOUT (MHz)
AD9144
130
Data Sheet
60
0dBFS
6dBFS
9dBFS
12dBFS
135
80
140
NSD (dBm/Hz)
fOUT = 30MHz
fOUT = 200MHz
fOUT = 400MHz
145
150
155
PLL: OFF
PLL: ON
100
120
140
160
160
180
100
200
300
400
500
fOUT (MHz)
11675-116
170
100
1k
10k
100k
1M
10M
Figure 19. Single-Tone Phase Noise vs. Offset Frequency over fOUT,
fDAC = 2.0 GHz, PLL On and Off
Figure 16. Single-Tone NSD vs. fOUT over Digital Back Off,
fDAC = 983 MHz
130
10
0dBFS
6dBFS
9dBFS
12dBFS
135
NSD (dBm/Hz)
140
145
150
155
160
100
200
300
400
500
fOUT (MHz)
11675-117
170
Figure 17. Single-Tone NSD vs. fOUT over Digital Back Off,
fDAC = 1966 MHz
130
PLL OFF
PLL ON
135
fDAC = 983MHz
fDAC = 1966MHz
140
145
150
155
160
170
100
200
300
400
fOUT (MHz)
500
11675-316
165
11675-118
NSD (dBm/Hz)
11675-315
165
11675-119
165
AD9144
11675-317
11675-320
Data Sheet
1
2
4
8
1700
1600
1500
1400
1300
1200
1000
0
500
1000
1500
2000
2500
fDAC (MHz)
11675-326
11675-318
1100
Figure 26. Total Power Consumption vs. fDAC over Interpolation, 8 SERDES Lanes
Enabled, 4 DACs Enabled, NCO, Digital Gain, Inverse Sinc and DAC PLL Disabled
120
100
NCO
PLL (fDAC /fREF RATIO:4)
DIGITAL GAIN
INVERSE SINC
80
60
40
0
200
400
600
800
1000
1200
1400
1600
fDAC (MHz)
11675-327
11675-319
20
AD9144
700
Data Sheet
2 LANES
4 LANES
8 LANES
350
300
SUPPLY CURRENT (mA)
500
400
300
200
250
200
150
100
50
0
200
11675-328
100
1.2V SUPPLY
1.3V SUPPLY
3.3V SUPPLY
Figure 28. SVDD12 Current vs. Lane Rate over Number of SERDES Lanes and
Supply Voltage Setting
400
600
800
100
fDAC (MHz)
1200
1400
1600
11675-329
600
DVDD12
CVDD12
PVDD12
AVDD33
Figure 29. DVDD12, CVDD12, PVDD12, and AVDD33 Supply Current vs. fDAC
over Supply Voltage Setting, 4 DACs Enabled
Data Sheet
AD9144
THEORY OF OPERATION
The AD9144 is a 16-bit, quad DAC with a SERDES interface.
Figure 2 shows a detailed functional block diagram of the
AD9144. Eight high speed serial lanes carry data at a maximum
speed of 10.6 Gbps, and a 1.06 GSPS input data rate to the DACs.
Compared to either LVDS or CMOS interfaces, the SERDES
interface simplifies pin count, board layout, and input clock
requirements to the device.
The clock for the input data is derived from the device clock
(required by the JESD204B specification). This device clock can
be sourced with a PLL reference clock used by the on-chip PLL
to generate a DAC clock or a high fidelity direct external DAC
sampling clock. The device can be configured to operate in one-,
two-, four-, or eight-lane modes, depending on the required
input data rate. To add application flexibility, the quad DAC can
be configured as a dual-link device with each JESD204B link
providing data for a dual DAC pair.
The digital datapath of the AD9144 offers four interpolation
modes (1, 2, 4, and 8) through three half-band filters with
a maximum DAC sample rate of 2.8 GSPS. An inverse sinc filter
is provided to compensate for sinc related roll-off.
The AD9144 DAC cores provide a fully differential current
output with a nominal full-scale current of 20 mA. The full-scale
AD9144
Data Sheet
SCLK 64
CS 65
SPI
PORT
DATA FORMAT
The instruction byte contains the information shown in Table 13.
Table 13. Serial Port Instruction Word
I[15] (MSB)
R/W
I[14:0]
A[14:0]
11675-044
SDIO 63
The serial clock pin synchronizes data to and from the device
and runs the internal state machines. The maximum frequency
of SCLK is 10 MHz. All data input is registered on the rising edge
of SCLK. All data is driven out on the falling edge of SCLK.
Data Sheet
AD9144
DATA TRANSFER CYCLE
SDIO
A3
A2 A1
A0 D7N D6 N D5N
CS
SCLK
SDIO
A0
A1 A2
CS
SCLK
tDV
SDIO
DATA BIT n
DATA BIT n 1
tSCS
tHCS
CS
tPWH
tPWL
SDIO
tDH
INSTRUCTION BIT 15
INSTRUCTION BIT 14
INSTRUCTION BIT 0
11675-047
SCLK
tDS
11675-045
SCLK
11675-046
INSTRUCTION CYCLE
CS
11675-048
AD9144
Data Sheet
CHIP INFORMATION
Register 0x003 to Register 0x006 contain chip information, as shown in Table 14.
Table 14. Chip Information
Information
Chip Type
Product ID
Product Grade
Device Revision
Description
The product type is high speed DAC, which is represented by a code of 0x04 in Register 0x003.
8 MSBs in Register 0x005 and 8 LSBs in Register 0x004. The product ID is 0x9144.
Register 0x006[7:4]. The product grade is 0x00.
Register 0x006[3:0]. The device revision is 0x06.
Data Sheet
AD9144
2.
3.
4.
5.
6.
Value
0x8B
0x01
0xFF
0xFF
0x01
If using the optional DAC PLL, also set the registers in Table 17.
Table 17. Optional DAC PLL Configuration Procedure
Addr.
0x087
Value1
0x62
0x088
0xC9
0x089
0x0E
0x08A
0x12
0x08D
0x7B
0x1B0
0x00
0x1B9
0x24
0x1BC
0x0D
0x1BE
0x02
0x1BF
0x8E
0x1C0
0x2A
0x1C1
0x2A
0x1C4
0x7E
0x08B
0x08C
0x085
Various
0x
0x
0x
0x
0x083
0x10
7.
Bit
No.
7
[6:3]
2
0x080
0x081
Value
0xBD
0x3C
0x
0
Variable
PdDACs
0
0x
0x
PdClocks
PdSysref
Description
Soft reset.
Deassert reset, set 4-wire SPI.
Power up band gap.
PdDACs = 0 if all 4 DACs are
being used. If not, see the DAC
Power-Down Setup section.
Power up master DAC.
PdClocks = 0 if all 4 DACs are
being used. If not, see the DAC
Power-Down Setup section.
PdSysref = 0x00 for Subclass 1.
PdSysref = 0x10 for Subclass 0.
See the Subclass Setup section
for details on subclass.
Description
Digital datapath configuration
Digital datapath configuration
Clock configuration
SERDES interface configuration
SERDES interface configuration
Variable
LODivMode
RefDivMode
BCount
LookUpVals
Description
Optimal DAC PLL loop filter
settings
Optimal DAC PLL loop filter
settings
Optimal DAC PLL loop filter
settings
Optimal DAC PLL charge pump
settings
Optimal DAC LDO settings for
DAC PLL
Power DAC PLL blocks when
power machine is disabled
Optimal DAC PLL charge pump
settings
Optimal DAC PLL VCO control
settings
Optimal DAC PLL VCO power
control settings
Optimal DAC PLL VCO calibration
settings
Optimal DAC PLL lock counter
length setting
Optimal DAC PLL charge pump
setting
Optimal DAC PLL varactor
settings
See the DAC PLL Setup section
See the DAC PLL Setup section
See the DAC PLL Setup section
See Table 25 in the DAC PLL Setup
section for the list of register
addresses and values for each.
Enable DAC PLL2
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register
value.
2
Verify that Register 0x084[1] reads back 1 after enabling the DAC PLL to
indicate that the DAC PLL has locked.
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register value.
Rev. A | Page 25 of 125
AD9144
Data Sheet
Addr.
0x200
0x201
Addr.
0x112
Bit No.
0x110
Variable
InterpMode
Description
Select interpolation
mode; see the
Interpolation section.
DataFmt
DataFmt = 0 if twos
complement;
DataFmt = 1 if unsigned
binary.
0x
7
Value
0x
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register value.
0x
0x300
0x
6
CheckSumMode
DualLink
CurrentLink
0x450
0x
DID
0x451
0x
BID
0x452
0x
LID
0x453
0x454
0x
Scrambling
L 12
F 12
0x455
0x
K 12
0x456
0x
M 12
0x457
0x458
0x
0x
N 12
Subclass
[4:0]
NP 12
0x459
0x
5
JESDVer
[4:0]
S 12
0x45A
JESDVer = 1 for
JESD204B,
JESDVer = 0 for
JESD204A.
See the JESD204B
Setup section.
0x
7
[4:0]
HD
0x45D
0
0x
CF
Lane0Checksum
0x46C
0x
Lanes
0x476
0x
0x47D
0x
Lanes
0x
7
[4:0]
Description
Power up the
interface.
See the JESD204B
Setup section.
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the correct register value.
2
This JESD204B link parameter is programmed in n 1 notation as noted. For
example, if the setup requires L = 8 (8 lanes per link), program L 1 or 7 into
Register 0x453[4:0].
Data Sheet
AD9144
This section describes how to set up the data link layer of the
SERDES interface. This section deals with SYSREF processing,
setting deterministic latency, and establishing the link.
Addr.
0x2AA
0x2AB
0x2B1
0x2B2
0x2A7
0x2AE
0x314
0x230
Bit
No.
Value1
0xB7
0x87
0xB7
0x87
0x01
0x01
0x01
0x
5
[4:2]
Halfrate
0x2
1
0x206
0x206
0x289
2
[1:0]
OvSmp
0x00
0x01
0x
1
PLLDiv
0x284
0x285
0x286
0x287
0x62
0xC9
0x0E
0x12
0x28A
0x28B
0x7B
0x00
0x290
0x89
0x294
0x24
0x296
0x297
0x299
0x03
0x0D
0x02
0x29A
0x8E
0x29C
0x2A
0x29F
0x78
0x2A0
0x06
0x280
0x268
0x01
0x
[7:6]
[5:0]
Variable
EqMode
0x22
Description
SERDES interface termination
setting
SERDES interface termination
setting
Autotune PHY setting
Autotune PHY setting
SERDES SPI configuration
Set up CDR; see the SERDES
Clocks Setup section
SERDES PLL default
configuration
Set up CDR; see the SERDES
Clocks Setup section
Reset CDR
Release CDR reset
SERDES PLL configuration
Set CDR oversampling for
PLL; see the SERDES Clocks
Setup section
Optimal SERDES PLL loop filter
Optimal SERDES PLL loop filter
Optimal SERDES PLL loop filter
Optimal SERDES PLL charge
pump
Optimal SERDES PLL VCO LDO
Optimal SERDES PLL
configuration
Optimal SERDES PLL VCO
varactor
Optimal SERDES PLL charge
pump
Optimal SERDES PLL VCO
Optimal SERDES PLL VCO
Optimal SERDES PLL
configuration
Optimal SERDES PLL VCO
varactor
Optimal SERDES PLL charge
pump
Optimal SERDES PLL VCO
varactor
Optimal SERDES PLL VCO
varactor
Enable SERDES PLL2
See the Equalization Mode
Setup section
Required value (default)
Bit
No.
Value1
0x
Variable
Subclass
0x304
0x
LMFCDel
0x305
0x
LMFCDel
0x306
0x
LMFCVar
0x307
0x
LMFCVar
0x03A
0x01
0x03A
0x81
0x03A
0xC1
Addr.
0x301
SYSREF
Signal
0x308
to
0x30B
0x
XBarVals
0x334
0x
InvLanes
0x300
0x
6
3
2
CheckSumMode
DualLink
CurrentLink
[1:0]
EnLinks
Description
See the JESD204B
Setup section.
See the Link Latency
Setup section.
See the Link Latency
section.
See the Link Latency
Setup section.
See the Link Latency
Setup section.
Set sync mode =
one-shot sync; see
the Syncing LMFC
Signals section for
other sync options.
Enable the sync
machine.
Arm the sync
machine.
If Subclass = 1, ensure
that at least one
SYSREF edge is sent
to the device.2
If remapping lanes,
set up crossbar; see
the Crossbar Setup
section.
Invert polarity of
desired logical lanes.
Bit x of InvLanes
must be a 1 for each
Logical Lane x to
invert.
Enable the links.
See the JESD204B
Setup section.
Set to 0 to access
Link 0 status or 1 for
Link 1 status
readbacks. See the
JESD204B Setup
section.
EnLinks = 3 if
DualLink = 1
(enables Link 0 and
Link 1);
EnLinks = 1 if
DualLink = 0 (enables
Link 0 only).
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the correct register value.
2
Verify that Register 0x03B[3] reads back 1 after sending at least one SYSREF
edge to the device to indicate that the LMFC sync machine has properly locked.
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the correct register value.
2
Verify that Register 0x281[0] reads back 1 after enabling the SERDES PLL to
indicate that the SERDES PLL has locked.
Rev. A | Page 27 of 125
AD9144
Data Sheet
Table 22. Optional Features
Feature
Digital
Modulation
Default
Off
Inverse Sinc
On
Digital Gain
2.7 dB
Phase Adjust
Off
DC Offset
Off
Group Delay
Downstream
Protection
Off
Self Calibration
Off
Description
Modulates the data with a desired
carrier. See the Digital Modulation
section.
Improves pass-band flatness. See
the Inverse Sinc section.
Multiplies data by a factor. Can
compensate inverse sinc usage or
balance I/Q amplitude. See the
Digital Gain section.
Used to balance I/Q phase. See the
Phase Adjust section.
Used to cancel LO leakage. See the
DC Offset section.
Used to control overall latency. See
the Group Delay section.
Used to protect downstream
components. See the Downstream
Protection section.
Used to improve DAC linearity. Not
paged by the dual paging register.
See the Self Calibration section.
Data Sheet
AD9144
INTERPOLATION
LODivMode,
Register 0x08B[1:0]
1
2
3
Divide by
(RefDivFactor)
1
2
4
8
16
RefDivMode,
Register 0x08C[2:0]
0
1
2
3
4
Register
0x1BB
Setting
0x03
0x03
0x13
Interpolation
Mode
1 (bypass)
InterpMode
0x00
Usable
Bandwidth
0.5 fDATA
0x01
0.4 fDATA
4
8
0x03
0x04
0.4 fDATA
0.4 fDATA
JESD204B SETUP
This section explains how to select a JESD204B operating mode
for a desired application. This section defines appropriate values
for CheckSumMode, UnusedLanes, DualLink, CurrentLink,
Scrambling, L, F, K, M, N, NP, Subclass, S, HD, Lane0Checksum,
and Lanes needed for the Step 3: Transport Layer section.
Note that DualLink, Scrambling, L, F, K, M, N, NP, S, HD, and
Subclass must be set the same on the transmit side.
For a summary of how a JESD204B system works and what each
parameter means, see the JESD204B Serial Data Interface section.
Finally, to finish configuring the DAC PLL, set the VCO control
registers up as described in Table 25 based on the VCO
frequency (fVCO). Write the registers listed in the table with the
corresponding LookUpVals.
VCO Frequency
Range (GHz)
fVCO < 6.3
6.3 fVCO < 7.25
fVCO 7.25
Register
0x1C5
Setting
0x07
0x06
0x06
For more information on the DAC PLL, see the DAC Input
Clock Configurations section.
0
4
8
1
1
1
4
8
2
2
Mode
2
4
4
1
2
3
4
2
1
4
4
2
4
1
1
5
2
4
2
2
Mode
6 7
2 2
2 1
1 1
2 4
9
1
2
1
1
10
1
1
1
2
AD9144
Data Sheet
DualLink
DualLink sets up two independent JESD204B links, which allows
each link to be reset independently. If this functionality is desired,
set DualLink to 1; if a single link is desired, set DualLink to 0.
Note that Link 0 and Link 1 must have identical parameters.
The operating modes available when using dual-link mode are
shown in Table 28. In addition to these operating modes, the
modes in Table 28 can also be used when using single-link mode.
Scrambling
Scrambling is a feature that makes the spectrum of the link data
independent. This avoids spectral peaking and provides some
protection against data dependent errors caused by frequency
selective effects in the electrical interface. Set to 1 if scrambling
is being used, or to 0 if it is not.
Subclass
Subclass determines whether the latency of the device is
deterministic, meaning it requires an external synchronization
signal. See the Subclass Setup section for more information.
CurrentLink
Set CurrentLink to either 0 or 1 depending on whether Link 0
or Link 1, respectively, needs to be configured.
Lanes
Lanes is used to enable and deskew particular lanes in two
thermometer coded registers.
Lanes = (2L) 1.
CheckSumMode
CheckSumMode must match the checksum mode used on the
transmit side. If the checksum used is the sum of fields in the
link configuration table, CheckSumMode = 0. If summing the
registers containing the packed link configuration fields,
CheckSumMode = 1. For more information on the how to
calculate the two checksum modes, see the Lane0Checksum
section.
Lane0Checksum
Lane0Checksum can be used for error checking purposes
to ensure that the transmitter is set up as expected. Both
CheckSumMode calculations use the fields contained in
Register 0x450 to Register 0x45A. Select whether to sum by
fields or by registers, matching the setting on the transmitter.
If CheckSumMode = 0, the summation is computed by fields.
The checksum is the lower 8 bits of the sum of the DID,
ADJCNT, BID, ADJDIR, PHADJ, LID, Scrambling, L 1, F 1,
K 1, M 1, CS, N 1, Subclass, NP 1, JESDVer, S 1, HD,
and CF variables.
If CheckSumMode = 1, the summation is computed by registers.
The checksum is the sum of Register 0x450 to Register 0x45A,
Modulo 256.
DualLink
0
1
0
1
0
PdDACs
0b0111
0b0101
0b0011
0b0000
0b0000
PdClocks
UnusedLanes
UnusedLanes is used to turn off unused circuit blocks to save
power. Each physical lane that is not being used (SERDINx)
must be powered off by writing a 1 to the corresponding bit of
Register 0x201.
Data Sheet
AD9144
Halfrate
0
0
1
OvSmp
1
0
0
PLLDiv
2
1
0
Halfrate and OvSmp set how the clock detect and recover
(CDR) circuit sample. See the SERDES PLL section for an
explanation of how that circuit blocks works and the role of
PLLDiv in the block.
0
4
8
N/A1
1
2
16
8
2
2
16
8
3
1
32
16
Subclass Setup
4
4
8
N/A1
5
2
16
8
6
2
16
8
7
1
32
16
9
4
8
N/A1
10
2
16
8
Subclass 1
This mode gives deterministic latency and allows links to be
synced to within DAC clock periods. It requires an external
SYSREF signal that is accurately phase aligned to the DAC clock.
Subclass 0
This mode does not require any signal on the SYSREF pins
(the pins can be left disconnected).
Subclass 0 still requires that all lanes arrive within the same
LMFC cycle and that the dual DACs must be synchronized to
each other (they are synchronized to an internal clock instead of
to the SYSREF signal).
where:
MinDelay is the minimum of all MinDelayLane values across
lanes, links, and devices.
MaxDelay is the maximum of all MaxDelayLane values across
lanes, links, and devices.
AD9144
Data Sheet
Bit.
No.
Value1
0x
0x01
0x03A
0x81
0x03A
0xC1
Variable
Subclass
SYSREF
Signal
0x300
0x
6
CheckSumMode
DualLink
CurrentLink
[1:0]
EnLinks
4.
5.
Description
Set subclass
Set sync mode to
one-shot sync
Enable the sync
machine
Arm the sync
machine
If Subclass = 1, ensure
that at least one
SYSREF edge is sent
to the device.
Enable the links
See the JESD204B
Setup section
See the JESD204B
Setup section
Set to 0 to access
Link 0 status or 1
for Link 1 status
readbacks. See the
JESD204B Setup
section.
EnLinks = 3 if in
DualLink mode to
enable Link 0 and
Link 1; EnLinks = 1 if
not in DualLink mode
to enable Link 0
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register value.
Data Sheet
AD9144
CROSSBAR SETUP
Bits
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
Logical Lane
LOGICAL_LANE0_SRC
LOGICAL_LANE1_SRC
LOGICAL_LANE2_SRC
LOGICAL_LANE3_SRC
LOGICAL_LANE4_SRC
LOGICAL_LANE5_SRC
LOGICAL_LANE6_SRC
LOGICAL_LANE7_SRC
AD9144
Data Sheet
JESD204B OVERVIEW
The AD9144 has eight JESD204B data ports that receive data.
The eight JESD204B ports can be configured as part of a single
JESD204B link or as part of two separate JESD204B links (duallink mode) that share a single system reference (SYSREF) and
device clock (CLK).
DataRate = (DACRate)/(InterpolationFactor)
LaneRate = (20 DataRate M)/L
where LaneRate must be between 1.44 Gbps and 10.64 Gbps.
Achieving and recovering synchronization of the lanes is very
important. To simplify the interface to the transmitter, the
AD9144 designates a master synchronization signal for each
JESD204B link. In single-link mode, SYNCOUT0 is used as the
master signal for all lanes; in dual-link mode, SYNCOUT0 is used
as the master signal for Link 0, and SYNCOUT1 is used as the
master signal for Link 1. If any lane in a link loses synchronization,
a resynchronization request is sent to the transmitter via the
synchronization signal of the link. The transmitter stops sending
data and instead sends synchronization characters to all lanes in
that link until resynchronization is achieved.
PHYSICAL
LAYER
SERDIN0
TRANSPORT
LAYER
DUAL A Q DATA[15:0]
DESERIALIZER
TO
DAC
FRAME TO
SAMPLES
QBD/
DESCRAMBLER
SERDIN7
DUAL A I DATA[15:0]
DUAL B I DATA[15:0]
DESERIALIZER
11675-004
DUAL B Q DATA[15:0]
SYSREF
0
4
8
1
1
1
4
8
2
2
2
4
4
1
2
3
4
2
1
4
4
2
4
1
1
250
1000
1000
250
500
1000
250
500
500
250
250
250
250
1000
1000
Mode
5
2
4
2
2
250
500
1000
6
2
2
1
2
7
2
1
1
4
9
1
2
1
1
10
1
1
1
2
250
500
500
250
250
250
250
1000
1000
250
500
500
Data Sheet
AD9144
Table 36. Dual-Link JESD204B Operating Modes for Link 0 and Link 1
Mode
Parameter
M (Converter Counts)
L (Lane Counts)
S (Samples per Converter per Frame)
F (Octets/Frame per Lane)
Example Clock for 10 Gbps Lane Rate
PClock (MHz)
Frame Clock (MHz)
Sample Clock (MHz)
4
2
4
1
1
5
2
4
2
2
6
2
2
1
2
7
2
1
1
4
9
1
2
1
1
10
1
1
1
2
250
1000
1000
250
500
1000
250
500
500
250
250
250
250
1000
1000
250
500
500
PHYSICAL LAYER
Address
0x2AA
0x2AB
0x2B1
0x2B2
0x2A7
0x2AE
TERMINATION
EQUALIZER
CDR
1:40
11675-006
SPI
CONTROL
FROM SERDES PLL
Description
SERDES interface termination configuration
SERDES interface termination configuration
SERDES interface termination configuration
SERDES interface termination configuration
Autotune PHY terminations
Autotune PHY terminations
525
55
0
55
525
0
0.35
0.5
0.65
TIME (UI)
1.00
11675-007
SERDINx
AMPLITUDE (mV)
DESERIALIZER
Value
0xB7
0x87
0xB7
0x87
0x01
0x01
AD9144
Data Sheet
Clock Relationships
The following clocks rates are used throughout the rest of the
JESD204B section. The relationship between any of the clocks
can be derived from the following equations:
To enable the SERDES PLL, first set the PLL divider register
according to Table 38, then enable the SERDES PLL by writing
Register 0x280[0] to 1.
DataRate = (DACRate)/(InterpolationFactor)
FrameRate = ByteRate/F
where F is defined as (bytes per frame) per lane.
SERDES PLL
Functional Overview of the SERDES PLL
The independent SERDES PLL uses integer-N techniques to
achieve clock synthesis. The entire SERDES PLL is integrated
on-chip, including the VCO and the loop filter. The SERDES
PLL VCO operates over the range of 5.65 GHz to 11.04 GHz.
In the SERDES PLL, a VCO divider block divides the VCO
clock by 2 to generate a 2.825 GHz to 5.52 GHz quadrature
clock for the deserializer cores. This clock is the input to the
clock and data recovery block that is described in the Clock and
Data Recovery section.
The reference clock to the SERDES PLL is always running at a
frequency, fREF = 1/40 of the lane rate = PClockRate. This clock
is divided by a DivFactor to deliver a clock to the PFD block
that is between 35 MHz and 80 MHz. Table 38 includes the
respective SERDES_PLL_DIV_MODE register settings for each
of the desired DivFactor options available.
Register
Address
0x284
0x285
0x286
0x287
0x28A
0x28B
0x290
0x294
0x296
0x297
0x299
0x29A
0x29C
0x29F
0x2A0
Divide by
(DivFactor)
1
2
4
Description
Optimal SERDES PLL loop filter
Optimal SERDES PLL loop filter
Optimal SERDES PLL loop filter
Optimal SERDES PLL charge pump
Optimal SERDES PLL VCO LDO
Optimal SERDES PLL configuration
Optimal SERDES PLL VCO varactor
Optimal SERDES PLL charge pump
Optimal SERDES PLL VCO
Optimal SERDES PLL VCO
Optimal SERDES PLL configuration
Optimal SERDES PLL VCO varactor
Optimal SERDES PLL charge pump
Optimal SERDES PLL VCO varactor
Optimal SERDES PLL VCO varactor
Register
Value
0x62
0xC9
0x0E
0x12
0x7B
0x00
0x89
0x24
0x03
0x0D
0x02
0x8E
0x2A
0x78
0x06
SERDES_PLL_DIV_MODE,
Register 0x289[1:0]
2
1
0
Data Sheet
AD9144
2.825GHz TO 5.52GHz
OUTPUT
VCO
LDO
CHARGE
PUMP
I Q
PFD
80MHz
MAX
fREF
BIT RATE 40
DivFactor
(1, 2, 4)
C1
R1
UP
C2
C3
LC VCO
5.65GHz TO 11.04GHz
2
DOWN
80
R3
ALC CAL
11675-011
FO CAL
3.2mA
Figure 38. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block
Equalization
ENHALFRATE,
Register 0x230[5]
0
0
1
CDR_OVERSAMP,
Register 0x230[1]
1
0
0
The CDR circuit synchronizes the phase used to sample the data on
each serial lane independently. This independent phase adjustment
per serial interface ensures accurate data sampling and eases the
implementation of multiple serial interfaces on a PCB.
After configuring the CDR circuit, reset it and then release the
reset by writing 1 and then 0 to Register 0x206[0].
AD9144
Data Sheet
4
6
AD9144 ALLOWED
CHANNEL LOSS
(LOW POWER MODE)
EXAMPLE OF
AD9144
COMPATIBLE
CHANNEL (LOW
POWER MODE)
10
12
14
EXAMPLE OF
AD9144
COMPATIBLE
CHANNEL
(NORMAL MODE)
AD9144 ALLOWED
CHANNEL LOSS
(NORMAL MODE)
16
EXAMPLE OF
JESD204B
COMPLIANT
CHANNE L
18
20
22
2.5
5.0
11675-339
24
7.5
FREQUENCY (GHz)
ATTENUATION (dB)
10
15
20
STRIPLINE = 6
STRIPLINE = 10
STRIPLINE = 15
STRIPLINE = 20
STRIPLINE = 25
STRIPLINE = 30
25
30
40
1
10
FREQUENCY (GHz)
11675-010
35
15
20
6 MICROSTRIP
10 MICROSTRIP
15 MICROSTRIP
20 MICROSTRIP
25 MICROSTRIP
30 MICROSTRIP
30
35
40
FREQUENCY (GHz)
10
11675-011
ATTENUATION (dB)
10
25
Data Sheet
AD9144
PHYSICAL
LAYER (PHY)
LOGICAL
LAYER
CROSSBAR
DAC CORE
QBD
SERDIN0/PHYSICAL LANE 0
SERDIN1/PHYSICAL LANE 1
SINGLE-LINK MODE
DAC0
SERDIN2/PHYSICAL LANE 2
SERDIN3/PHYSICAL LANE 3
SERDIN4/PHYSICAL LANE 4
SERDIN5/PHYSICAL LANE 5
DAC1
LOGICAL LANE 3/LINK 0 LANE 3
QUAD-BYTE
DEFRAMER
(QBD0)
DAC2
SERDIN6/PHYSICAL LANE 6
SERDIN7/PHYSICAL LANE 7
PHYSICAL LANES
DAC3
LOGICAL LANES
SERDIN0/PHYSICAL LANE 0
SERDIN1/PHYSICAL LANE 1
SERDIN2/PHYSICAL LANE 2
SERDIN3/PHYSICAL LANE 3
SERDIN4/PHYSICAL LANE 4
SERDIN5/PHYSICAL LANE 5
CROSSBAR
REGISTER
0x308
TO
REGISTER
0x30B
QUAD-BYTE
DEFRAMER 0
(QBD0)
DAC1
SERDIN6/PHYSICAL LANE 6
SERDIN7/PHYSICAL LANE 7
QUAD-BYTE
DEFRAMER 1
(QBD1)
DAC3
LOGICAL LANES
11675-442
PHYSICAL LANES
LANE 7 DESERIALIZED
AND DESCRAMBLED DATA
LANE 7 DATA CLOCK
SYSREF
SERDIN0
FIFO
CROSS
BAR
SWITCH
SERDIN7
FIFO
LANE0 OCTETS
LANE7 OCTETS
SYSTEM CLOCK
PHASE DETECT
11675-012
QUAD-BYTE
DEFRAMER
QBD
DESCRAMBLE
LANE 0 DESERIALIZED
AND DESCRAMBLED DATA
10-BIT/8-BIT DECODE
DUAL-LINK MODE
DAC0
PCLK
SPI CONTROL
AD9144
Data Sheet
L RECEIVE LANES
(EARLIEST ARRIVAL) K K K R D D
D D A R Q C
L RECEIVE LANES
(LATEST ARRIVAL) K K K K K K K R D D
D D A R Q C
D D A R D D
D D A R D D
L ALIGNED
RECEIVE LANES K K K K K K K R D D
D D A R Q C
11675-013
D D A R D D
After the last /A/ character of the last ILAS, multiframe data
begins streaming. The receiver adjusts the position of the /A/
character such that it aligns with the internal LMFC of the
receiver at this point.
The main purposes of this phase are to align all the lanes of the
link and to verify the parameters of the link.
Various test modes for verifying the link integrity can be found
in the JESD204B Test Modes section.
Data Sheet
AD9144
Lane FIFO
The FIFOs in front of the crossbar switch and deframer
synchronize the samples sent on the high speed serial data
interface with the deframer clock by adjusting the phase of the
incoming data. The FIFO absorbs timing variations between the
data source and the deframer; this allows up to two PClock cycles
of drift from the transmitter. The FIFO_STATUS_REG_0 register
and FIFO_STATUS_REG_1 register (Register 0x30C and
Register 0x30D, respectively) can be monitored to identify
whether the FIFOs are full or empty.
Crossbar Switch
Register 0x308 to Register 0x30B allow arbitrary mapping of
physical lanes (SERDINx) to logical lanes used by the SERDES
deframers.
Table 41. Crossbar Registers
Address
0x308
0x308
0x309
0x309
0x30A
0x30A
0x30B
0x30B
Bits
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
Descrambler
The AD9144 provides an optional descrambler block using a
self synchronous descrambler with a polynomial: 1 + x14 + x15.
Enabling data scrambling reduces spectral peaks that are
produced when the same data octets repeat from frame to
frame. It also makes the spectrum data independent so that
possible frequency-selective effects on the electrical interface do
not cause data-dependent errors. Descrambling of the data is
enabled by setting the SCR bit (Register 0x453[7]) to 1.
Logical Lane
LOGICAL_LANE0_SRC
LOGICAL_LANE1_SRC
LOGICAL_LANE2_SRC
LOGICAL_LANE3_SRC
LOGICAL_LANE4_SRC
LOGICAL_LANE5_SRC
LOGICAL_LANE6_SRC
LOGICAL_LANE7_SRC
SYSREF Signal
Write each LOGICAL_LANEy_SRC with the number (x) of the
desired physical lane (SERDINx) from which to obtain data.
By default, all logical lanes use the corresponding physical lane
as their data source. For example, by default LOGICAL_
LANE0_SRC = 0; therefore, Logical Lane 0 obtains data from
Physical Lane 0 (SERDIN0). If instead the user wants to use
SERDIN4 as the source for Logical Lane 0, the user must write
LOGICAL_LANE0_SRC = 4.
Lane Inversion
Register 0x334 allows inversion of desired logical lanes, which
can be used to ease routing of the SERDINx signals. For each
Logical Lane x, set Bit x of Register 0x334 to 1 to invert it.
Deframers
The AD9144 consists of two quad-byte deframers (QBDs). Each
deframer takes in the 8-bit/10-bit encoded data from the
deserializer (via the crossbar switch), decodes it, and descrambles it
into JESD204B frames before passing it to the transport layer to be
converted to DAC samples. The deframer processes four symbols
(or octets) per processing clock (PClock) cycle.
AD9144
Data Sheet
3k
SYSREF
3k
~600mV
11675-015
SYSREF+
Data Sheet
AD9144
Sync Procedure
1.
2.
3.
4.
5.
6.
7.
Use Register 0x021[3:0] to enable the sync status bits for DAC
Dual A (DAC0 and DAC1), and then use Register 0x025[3:0] to
read back their statuses and reset the IRQ signals.
Use Register 0x022[3:0] to enable the sync status bits for DAC
Dual B (DAC2 and DAC3), and then use Register 0x026[3:0]
read back their statuses and reset the IRQ signals.
See the Interrupt Request Operation section for more information.
Deterministic Latency
JESD204B systems contain various clock domains distributed
throughout each system. Data traversing from one clock
domain to a different clock domain can lead to ambiguous
delays in the JESD204B link. These ambiguities lead to
nonrepeatable latencies across the link from power cycle to
power cycle with each new link establishment. Section 6 of the
JESD204B specification addresses the issue of deterministic
latency with mechanisms defined as Subclass 1 and Subclass 2.
The AD9144 supports JESD204B Subclass 0 and Subclass 1 operation, but not Subclass 2. Write the subclass to Register 0x301[2:0]
and once per link to Register 0x458[7:5].
Subclass 0
This mode does not require any signal on the SYSREF pins,
which can be left disconnected.
Subclass 0 still requires that all lanes arrive within the same
LMFC cycle, and the dual DACs must be synchronized to each
other.
Subclass 1
This mode gives deterministic latency and allows links to be
synced to within of a DAC clock period. It requires an
external SYSREF signal that is accurately phase aligned to the
DAC clock.
AD9144
Data Sheet
Because the LMFC is periodic, this can account for any amount
of fixed delay. As a result, the LMFC period must only be larger
than the variation in the link delays, and the AD9144 can achieve
proper performance with a smaller total latency. Figure 46 and
Figure 47 show a case where the link delay is larger than an
LMFC period. Note that it can be accommodated by delaying
LMFCRx.
POWER CYCLE
VARIANCE
LMFC
ILAS
ALIGNED DATA
DATA
LATE ARRIVING
LMFC REFERENCE
EARLY ARRIVING
LMFC REFERENCE
Link Delay
POWER CYCLE
VARIANCE
LMFC
ILAS
ALIGNED DATA
DATA
LMFCRX
LMFC REFERENCE FOR ALL POWER CYCLES
LMFC_DELAY
FRAME CLOCK
LOGIC DEVICE
(JESD204B Tx)
CHANNEL
JESD204B Rx
DSP
DAC
POWER CYCLE
VARIANCE
LMFC
DATA AT
Tx INPUT
ALIGNED DATA
AT Rx OUTPUT
11675-018
ILAS
DATA
ILAS
DATA
FIXED DELAY
VARIABLE
DELAY
11675-019
11675-017
Data Sheet
AD9144
1.
2.
3.
4.
6.
7.
LMFC
PCLOCK
FRAME CLOCK
ILAS
DATA
ILAS
Tx VAR
DELAY
Rx VAR
DELAY
DATA
PCB FIXED
DELAY
LMFCRX
TOTAL VARIABLE
LATENCY = 4
PCLOCK CYCLES
11675-024
DATA AT Tx FRAMER
AD9144
Data Sheet
2.
3.
4.
5.
6.
SYSREF
LMFCRX
ILAS
ALIGNED DATA
DATA
11675-022
DYN_LINK_LATENCY
ILAS
DATA
ILAS
DATA
ILAS
DATA
LMFCRX
DETERMINISTICALLY
DELAYED DATA
ILAS
LMFC_DELAY = 6
(FRAME CLOCK CYCLES)
DATA
LMFC_VAR = 7
(PCLOCK CYCLES)
11675-025
1.
Data Sheet
AD9144
TRANSPORT LAYER
TRANSPORT LAYER
(QBD)
LANE 0 OCTETS
DAC A_I0[15:0]
DELAY
BUFFER 0
F2S_0
DAC A_Q0[15:0]
LANE 3 OCTETS
PCLK_0
SPI CONTROL
LANE 4 OCTETS
DAC B_I0[15:0]
DELAY
BUFFER 1
F2S_1
DAC B_Q0[15:0]
LANE 7 OCTETS
11675-026
PCLK_1
SPI CONTROL
CS
Parameter
F
K
HD
Description
Number of octets per frame per lane: 1, 2, or 4.
Number of frames per multiframe.
K = 32 if F = 1, K = 16 or 32 otherwise.
Number of lanes per converter device (per link), as
follows:
1, 2, 4, or 8 (single-link mode).
1, 2, or 4 (dual-link mode).
Number of converters per device (per link), as follows:
1, 2, or 4 (single-link mode).
1 or 2 (dual-link mode).
Number of samples per converter, per frame: 1 or 2.
N
N (NP)
Description
Number of control words per device clock per link.
Not supported, must be 0.
Number of control bits per conversion sample.
Not supported, must be 0.
High density user data format. Used when samples
must be split across lanes.
Set to 1 when F = 1, otherwise 0.
Converter resolution = 16.
Total number of bits per sample = 16.
AD9144
Data Sheet
0
4
8
1
1
32
1
16
16
1
4
8
2
2
16/32
0
16
16
2
4
4
1
2
16/32
0
16
16
3
4
2
1
4
16/32
0
16
16
4
2
4
1
1
32
1
16
16
250
1000
1000
250
500
1000
250
500
500
250
250
250
250
1000
1000
Mode
5
2
4
2
2
16/32
0
16
16
250
500
1000
6
2
2
1
2
16/32
0
16
16
7
2
1
1
4
16/32
0
16
16
9
1
2
1
1
32
1
16
16
10
1
1
1
2
16/32
0
16
16
250
500
500
250
250
250
250
1000
1000
250
500
500
Table 47. Dual-Link JESD204B Operating Modes for Link 0 and Link 1
Parameter
M (Converter Count)
L (Lane Count)
S (Samples per Converter per Frame)
F (Octets per Frame per Lane)
K1 (Frames per Multiframe)
HD (High Density)
N (Converter Resolution)
NP (Bits per Sample)
Example Clocks for 10 Gbps Lane Rate
PClock Rate (MHz)
Frame Clock Rate (MHz)
Data Rate (MHz)
1
4
2
4
1
1
32
1
16
16
5
2
4
2
2
16/32
0
16
16
Mode
6
2
2
1
2
16/32
0
16
16
7
2
1
1
4
16/32
0
16
16
9
1
2
1
1
32
1
16
16
10
1
1
1
2
16/32
0
16
16
250
1000
1000
250
500
1000
250
500
500
250
250
250
250
1000
1000
250
500
500
Data Sheet
AD9144
Configuration Parameters
JESDV
Description
Number of lanes 1.
Number of ((octets per frame) per
lane) 1.
Number of frames per multiframe 1.
Number of converters 1.
Converter bit resolution 1.
Bit packing per sample 1.
Number of ((samples per converter)
per frame) 1.
High density format. Set to 1 if F = 1.
Leave at 0 if F 1.
F parameter, in ((octets per frame) per
lane).
Device ID. Match the Device ID sent
by the transmitter.
Bank ID. Match the Bank ID sent by
the transmitter.
Lane ID for lane 0. Match the Lane ID
sent by the transmitter on Logical
Lane 0.
JESD204x Version. Match the version
sent by the transmitter (0x0 =
JESD204A, 0x1 = JESD204B).
Address
0x453[4:0]
0x454[7:0]
0x455[4:0]
0x456[7:0]
0x457[4:0]
0x458[4:0]
0x459[4:0]
0x476[7:0]
0x450[7:0]
0x45A[7]
0x451[3:0]
0x452[4:0]
0x459[7:5]
AD9144
Data Sheet
J0
SERDINx
J19 J18
DESERIALIZER
DESERIALIZER
J11 J10
SERDINx
J9
J8
J1
J0
DESERIALIZER
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
LANE 0, OCTET 0
10-BIT/8-BIT
DECODE
DAC0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DAC1
DESCRAMBLER
2 CONVERTERS
(M = 2)
1 SAMPLE PER
CONVERTER PER FRAME
(S = 1)
16-BIT NIBBLE GROUP
(N = 16)
1 OCTET PER LANE
(F = 1)
11675-027
J1
CONVERTER 0, SAMPLE 0
J8
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CONVERTER 1, SAMPLE 0
J9
NIBBLE GROUP 0
SERDINx
LANE 1, OCTET 0
DESERIALIZER
LANE 2, OCTET 0
J11 J10
TRANSPORT
LAYER
NIBBLE GROUP 1
J19 J18
LANE 3, OCTET 0
PHYSICAL
LAYER
SERDINx
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Data Sheet
AD9144
Table 49. SPI Configuration MapRegister Settings for JESD204B Parameters for Mode 0
LANE 3,
OCTET 0
J0
J1
SERDINx
J7
LANE 6,
OCTET 0
J6
J9
SERDINx
J8
J0
J1
SERDINx
LANE 5,
OCTET 0
J6
J9
LANE 4,
OCTET 0
J15 J14
LANE 2,
OCTET 0
J15 J14
SERDINx
J8
J0
J1
SERDINx
J6
J8
SERDINx
J9
J7
J7
J15 J14
J9
SERDINx
SERDINx
LANE 1,
OCTET 0
LANE 7,
OCTET 0
NIBBLE GROUP 0
NIBBLE GROUP 1
NIBBLE GROUP 2
NIBBLE GROUP 3
CONVERTER 0, SAMPLE 0
CONVERTER 1, SAMPLE 0
CONVERTER 2, SAMPLE 0
CONVERTER 3, SAMPLE 0
D15 ... D0
D15 ... D0
D15 ... D0
D15 ... D0
DAC1
DAC2
DAC0
DAC3
11675-028
4 CONVERTERS
(M = 4)
LANE 0,
OCTET 0
J7
J15 J14
J1
J0
Description
Register 0x453[7] = 0 or 1: scrambling disabled or enabled; Register 0x453[4:0] = 0x7: L = 8 lanes per link
Register 0x454[7:0] = 0x00: F = 1 octet per frame
Register 0x455[4:0] = 0x1F: K = 32 frames per multiframe
Register 0x456[7:0] = 0x03: M = 4 converters per link
Register 0x457[7:6] = 0x0: always set CS = 0; Register 0x457[4:0] = 0xF: N = 16, always set to 16-bit resolution
Register 0x458[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458[4:0] = 0xF: NP = 16 bits per sample
Register 0x459[7:5] = 0x1: JESD204B version; Register 0x459[4:0] = 0x0: S = 1 (sample/converter)/frame
Register 0x45A[7] = 1: HD = 1; Register 0x45A[4:0] = 0x00: always set CF = 0
Register 0x46C[7:0] = 0xFF: deskew Link Lane 0 to Link Lane 7
Register 0x476[7:0] = 0x01: F = 1 octet per frame
Register 0x47D[7:0] = 0xFF: enable Link Lane 0 to Link Lane 7
J6
Setting
0x07 or 0x87
0x00
0x1F
0x03
0x0F
0x0F or 0x2F
0x20
0x80
0xFF
0x01
0xFF
J8
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
0x45A
0x46C
0x476
0x47D
AD9144
Data Sheet
Table 50. SPI Configuration MapRegister Settings for JESD204B Parameters for Mode 1
4 CONVERTERS
(M = 4)
L 0,
O1
L 1,
O0
NIBBLE
GROUP 0
CONV 0,
SMPL 0
L 3,
O0
NIBBLE
GROUP 2
CONV 1,
SMPL 0
L 3,
O1
NIBBLE
GROUP 3
CONV 1,
SMPL 1
NIBBLE
GROUP 4
CONV 2,
SMPL 0
NIBBLE
GROUP 5
CONV 2,
SMPL 1
L 6,
O0
J0
L 7,
O0
NIBBLE
GROUP 6
CONV 3,
SMPL 0
J1
SERDINx
L 6,
O1
J15 J14
J15 J14
SERDINx
L 5,
O1
J1
J0
J0
L 5,
O0
J1
SERDINx
L 4,
O1
J15 J14
J1
J0
L 4,
O0
J15 J14
SERDINx
J1
SERDINx
L 2,
O1
J15 J14
J0
NIBBLE
GROUP 1
CONV 0,
SMPL 1
L 2,
O0
J1
SERDINx
L 1,
O1
J15 J14
J1
J15 J14
SERDINx
J1
SERDINx
L 0,
O0
L 7,
O1
NIBBLE
GROUP 7
CONV 3,
SMPL 1
DAC0
DAC1
DAC2
DAC3
11675-029
J15 J14
J0
Description
Register 0x453[7] = 0 or 1: scrambling disabled or enabled; Register 0x453[4:0] = 0x7: L = 8 lanes per link
Register 0x454[7:0] = 0x01: F = 2 octets per frame
Register 0x455[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456[7:0] = 0x03: M = 4 converters per link
Register 0x457[7:6] = 0x0: always set CS = 0; Register 0x457[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458[4:0] = 0xF: NP = 16 bits per sample
Register 0x459[7:5] = 0x1: set to JESD204B version; Register 0x459[4:0] = 0x1: S = 2 (sample/converter)/frame
Register 0x45A[7] = 0: HD = 0; Register 0x45A[4:0] = 0x00: always set CF = 0
Register0x46C[7:0] = 0xFF: deskew Link Lane 0 to Link Lane 7
Register 0x476[7:0] = 0x02: F = 2 octets per frame
Register 0x47D[7:0] = 0xFF: enable Link Lane 0 to Link Lane 7
J0
Setting
0x07 or 0x87
0x01
0x0F or 0x1F
0x03
0x0F
0x0F or 0x2F
0x21
0x00
0xFF
0x02
0xFF
J0
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
0x45A
0x46C
0x476
0x47D
Data Sheet
AD9144
Table 51. SPI Configuration MapRegister Settings for JESD204B Parameters for Mode 2
4 CONVERTERS
(M = 4)
LANE 0,
OCTET 1
LANE 1,
OCTET 0
LANE 2,
OCTET 0
J0
J1
SERDINx
LANE 2,
OCTET 1
J15 J14
J1
J0
LANE 1,
OCTET 1
J15 J14
SERDINx
J1
SERDINx
J1
SERDINx
LANE 0,
OCTET 0
LANE 3,
OCTET 0
LANE 3,
OCTET 1
NIBBLE GROUP 0
NIBBLE GROUP 1
NIBBLE GROUP 2
NIBBLE GROUP 3
CONVERTER 0, SAMPLE 0
CONVERTER 1, SAMPLE 0
CONVERTER 2, SAMPLE 0
CONVERTER 3, SAMPLE 0
DAC1
DAC2
DAC0
DAC3
11675-030
J15 J14
J0
Description
Register 0x453[7] = 0 or 1: scrambling disabled or enabled; Register 0x453[4:0] = 0x3: L = 4 lanes per link
Register 0x454[7:0] = 0x01: F = 2 octets per frame
Register 0x455[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456[7:0] = 0x03: M = 4 converters per link
Register 0x457[7:6] = 0x0: always set CS = 0; Register 0x457[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458[4:0] = 0xF: NP = 16 bits per sample
Register 0x459[7:5] = 0x1: set to JESD204B version; Register 0x459[4:0] = 0x0: S = 1 (sample/converter)/frame
Register 0x45A[7] = 0: HD = 0; Register 0x45A[4:0] = 0x00: always set CF = 0
Register0x46C[7:0] = 0x0F: deskew Link Lane 0 to Link Lane 3
Register 0x476[7:0] = 0x02: F = 2 octets per frame
Register 0x47D[7:0] = 0x0F: enable Link Lane 0 to Link Lane 3
J15 J14
Setting
0x03 or 0x83
0x01
0x0F or 0x1F
0x03
0x0F
0x0F or 0x2F
0x20
0x00
0x0F
0x02
0x0F
J0
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
0x45A
0x46C
0x476
0x47D
AD9144
Data Sheet
Table 52. SPI Configuration MapRegister Settings for JESD204B Parameters for Mode 3
J0
Description
Register 0x453[7] = 0 or 1: scrambling disabled or enabled; Register 0x453[4:0] = 0x1: L = 2 lanes per link
Register 0x454[7:0] = 0x03: F = 4 octets per frame
Register 0x455[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456[7:0] = 0x03: M = 4 converters per link
Register 0x457[7:6] = 0x0: always set CS = 0; Register 0x457[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458[7:5] =0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458[4:0] = 0xF: NP = 16 bits per sample
Register 0x459[7:5] = 0x1: set to JESD204B version; Register 0x459[4:0] = 0x0: S = 1 (sample/converter)/frame
Register 0x45A[7] = 0: HD = 0; Register 0x45A[4:0] = 0x00: always set CF = 0
Register0x46C[7:0] = 0x03: deskew Link Lane 0 and Link Lane 1
Register 0x476[7:0] = 0x04: F = 4 octets per frame
Register 0x47D[7:0] = 0x03: enable Link Lane 0 and Link Lane 1
J1
J1
SERDINx
J31 J30
LANE 0,
LANE 0,
OCTET 0
OCTET 1
NIBBLE GROUP 0
LANE 0,
LANE 0,
OCTET 2
OCTET 3
NIBBLE GROUP
GROUP 11
LANE 1,
LANE 1,
OCTET 0
OCTET 1
NIBBLE
NIBBLE GROUP
GROUP 22
LANE 1,
LANE 1,
OCTET 2
OCTET 3
NIBBLE
NIBBLE GROUP
GROUP 33
CONVERTER 0, SAMPLE 0
CONVERTER 1, SAMPLE 0
CONVERTER 2, SAMPLE 0
CONVERTER 3, SAMPLE 0
DAC1
DAC2
DAC0
DAC3
11675-031
4 CONVERTERS
(M = 4)
SERDINx
J31 J30
Setting
0x01 or 0x81
0x03
0x0F or 0x1F
0x03
0x0F
0x0F or 0x2F
0x20
0x00
0x03
0x04
0x03
J0
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
0x45A
0x46C
0x476
0x47D
Data Sheet
AD9144
Table 53. SPI Configuration MapRegister Settings for JESD204B Parameters for Mode 4
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
0x45A
0x46C
0x476
0x47D
Setting
0x03 or 0x83
0x00
0x1F
0x01
0x0F
0x0F or 0x2F
0x20
0x01
0x0F
0x01
0x0F
Description
Register 0x453[7] = 0 or 1: scrambling disabled or enabled; Register 0x453[4:0] = 0x3: L = 4 lanes per link
Register 0x454[7:0] = 0x00: F = 1 octet per frame
Register 0x455[4:0] = 0x1F: K = 32 frames per multiframe
Register 0x456[7:0] = 0x01: M = 2 converters per link
Register 0x457[7:6] = 0x0: always set CS = 0; Register 0x457[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458[4:0] = 0xF: NP = 16 bits per sample
Register 0x459[7:5] = 0x1: set to JESD204B version; Register 0x459[4:0] = 0x0: S = 1 (sample/converter)/frame
Register 0x45A[7] = 1: HD = 1; Register 0x45A[4:0] = 0x00: always set CF = 0
Register0x46C[7:0] = 0x0F: deskew Link Lane 0 to Link Lane 3
Register 0x476[7:0] = 0x01: F = 1 octet per frame
Register 0x47D[7:0] = 0x0F: enable Link Lane 0 to Link Lane 3
See Figure 53 for an illustration of the AD9144 JESD204B Mode 4 data deframing process.
Table 54. SPI Configuration MapRegister Settings for JESD204B Parameters for Mode 5
2 CONVERTERS
(M = 2)
LANE 0,
OCTET 0
LANE 1,
OCTET 0
LANE 2,
OCTET 0
J0
LANE 3,
OCTET 0
J1
SERDINx
LANE 2,
OCTET 1
J15 J14
J1
J0
LANE 1,
OCTET 1
J15 J14
SERDINx
J1
J15 J14
J1 J0
LANE 0,
OCTET 1
LANE 3,
OCTET 1
NIBBLE GROUP 0
NIBBLE GROUP 1
NIBBLE GROUP 2
NIBBLE GROUP 3
CONVERTER 0, SAMPLE 0
CONVERTER 0, SAMPLE 1
CONVERTER 1, SAMPLE 0
CONVERTER 1, SAMPLE 1
DAC0
DAC1
11675-032
SERDINx
J0
Description
Register 0x453[7] = 0 or 1: scrambling disabled or enabled; Register 0x453[4:0] = 0x3: L = 4 lanes per link
Register 0x454[7:0] = 0x01: F = 2 octets per frame
Register 0x455[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456[7:0] = 0x01: M = 2 converters per link
Register 0x457[7:6] = 0x0: always set CS = 0; Register 0x457[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458[4:0] = 0xF: NP = 16 bits per sample
Register 0x459[7:5] = 0x1: set to JESD204B version; Register 0x459[4:0] = 0x1: S = 2 (sample/converter)/frame
Register 0x45A[7] = 0: HD = 0; Register 0x45A[4:0] = 0x00: always set CF = 0
Register0x46C[7:0] = 0x0F: deskew Link Lane 0 to Link Lane 3
Register 0x476[7:0] = 0x02: F = 2 octets per frame
Register 0x47D[7:0] = 0x0F: enable Link Lane 0 to Link Lane 3
SERDINx
Setting
0x03 or 0x83
0x01
0x0F or 0x1F
0x01
0x0F
0x0F or 0x2F
0x21
0x00
0x0F
0x02
0x0F
J15 J14
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
0x45A
0x46C
0x476
0x47D
AD9144
Data Sheet
Table 55. SPI Configuration MapRegister Settings for JESD204B Parameters for Mode 6
J1
DAC0
D0
D1
D4
D5
D6
D7
D9
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
CONVERTER 1, SAMPLE 0
D10
CONVERTER 0, SAMPLE 0
D2
LANE 1, OCTET 1
D3
SERDINx
J15 J14
SERDINx
J1
LANE 1, OCTET 0
NIBBLE GROUP 1
D11
D12
D13
D14
LANE 0, OCTET 1
NIBBLE GROUP 0
DAC1
11675-033
2 CONVERTERS
(M = 2)
LANE 0, OCTET 0
D15
J15 J14
J0
Description
Register 0x453[7] = 0 or 1: scrambling disabled or enabled, Register 0x453[4:0] = 0x1: L = 2 lanes per link
Register 0x454[7:0] = 0x01: F = 2 octets per frame
Register 0x455[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456[7:0] = 0x01: M = 2 converters per link
Register 0x457[7:6] = 0x0: always set CS = 0; Register 0x457[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458[4:0] = 0xF: NP = 16 bits per sample
Register 0x459[7:5] = 0x1: set to JESD204B version; Register 0x459[4:0] = 0x0: S = 1 (sample/converter)/frame
Register 0x45A[7] = 0: HD = 0; Register 0x45A[4:0] = 0x00: always set CF = 0
Register0x46C[7:0] = 0x03: deskew Link Lane 0 and Link Lane 1
Register 0x476[7:0] = 0x02: F = 2 octets per frame
Register 0x47D[7:0] = 0x03: enable Link Lane 0 and Link Lane 1
D8
Setting
0x01 or 0x81
0x01
0x0F or 0x1F
0x01
0x0F
0x0F or 0x2F
0x20
0x00
0x03
0x02
0x03
J0
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
0x45A
0x46C
0x476
0x47D
Data Sheet
AD9144
Table 56. SPI Configuration MapRegister Settings for JESD204B Parameters for Mode 7
SERDINx
J1
J0
Description
Register 0x453[7] = 0 or 1: scrambling disabled or enabled, Register 0x453[4:0] = 0x0: L = 1 lane per link
Register 0x454[7:0] = 0x03: F = 4 octets per frame
Register 0x455[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456[7:0] = 0x01: M = 2 converters per link
Register 0x457[7:6] = 0x0: always set CS = 0; Register 0x457[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458[4:0] = 0xF: NP = 16 bits per sample
Register 0x459[7:5] = 0x1: set to JESD204B version; Register 0x459[4:0] = 0x0: S = 1 (sample/converter)/frame
Register 0x45A[7] = 0: HD = 0; Register 0x45A[4:0] = 0x00: always set CF = 0
Register0x46C[7:0] = 0x01: deskew Link Lane 0
Register 0x476[7:0] = 0x04: F = 4 octets per frame
Register 0x47D[7:0] = 0x01: enable Link Lane 0
2 CONVERTERS
(M = 2)
LANE 0,
LANE 0,
OCTET 0
OCTET 1
NIBBLE GROUP 0
LANE 0,
LANE 0,
OCTET 2
OCTET 3
NIBBLE
NIBBLE GROUP
GROUP 12
CONVERTER 0, SAMPLE 0
CONVERTER 1, SAMPLE 0
D15 ... D0
D15 ... D0
DAC0
DAC1
11675-034
Setting
0x00 or 0x80
0x03
0x0F or 0x1F
0x01
0x0F
0x0F or 0x2F
0x20
0x00
0x01
0x04
0x01
J31 J30
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
0x45A
0x46C
0x476
0x47D
AD9144
Data Sheet
Table 57. SPI Configuration MapRegister Settings for JESD204B Parameters for Mode 9
J1
J6
SERDINx
LANE 0,
OCTET 0
LANE 1,
OCTET 0
NIBBLE GROUP 0
CONVERTER 0, SAMPLE 0
1 CONVERTER
(M = 1)
D15 ... D0
DAC0
11675-035
J7
J9
J8
J0
Description
Register 0x453[7] = 0 or 1: scrambling disabled or enabled, Register 0x453[4:0] = 0x1: L = 2 lanes per link
Register 0x454[7:0] = 0x00: F = 1 octet per frame
Register 0x455[4:0] = 0x1F: K = 32 frames per multiframe
Register 0x456[7:0] = 0x00: M = 1 converter per link
Register 0x457[7:6] = 0x0: always set CS = 0; Register 0x457[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458[4:0] = 0xF: NP = 16 bits per sample
Register 0x459[7:5] = 0x1: Set to JESD204B version; Register 0x459[4:0] = 0x0: S = 1 (sample/converter)/frame
Register 0x45A[7] = 1: HD = 1; Register 0x45A[4:0] = 0x00: always set CF = 0
Register0x46C[7:0] = 0x03: deskew Link Lane 0 and Link Lane 1
Register 0x476[7:0] = 0x01: F = 1 octet per frame
Register 0x47D[7:0] = 0x03: enable Link Lane 0 and Link Lane 1
SERDINx
Setting
0x01 or 0x81
0x00
0x1F
0x00
0x0F
0x0F or 0x2F
0x20
0x01
0x03
0x01
0x03
J15 J14
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
0x45A
0x46C
0x476
0x47D
Data Sheet
AD9144
Table 58. SPI Configuration MapRegister Settings for JESD204B Parameters for Mode 10
J1
J0
Description
Register 0x453[7] = 0 or 1: scrambling disabled or enabled, Register 0x453[4:0] = 0x0: L = 1 lane per link
Register 0x454[7:0] = 0x01: F = 2 octets per frame
Register 0x455[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456[7:0] = 0x00: M = 1 converter per link
Register 0x457[7:6] = 0x0: always set CS = 0; Register 0x457[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458[4:0] = 0xF: NP = 16 bits per sample
Register 0x459[7:5] = 0x1: set to JESD204B version; Register 0x459[4:0] = 0x0: S = 1 (sample/converter)/frame
Register 0x45A[7] = 0: HD = 0; Register 0x45A[4:0] = 0x00: always set CF = 0
Register0x46C[7:0] = 0x01: deskew Link Lane 0
Register 0x476[7:0] = 0x02: F = 2 octets per frame
Register 0x47D[7:0] = 0x01: enable Link Lane 0
SERDINx
LANE 0,
OCTET 0
LANE 1,
OCTET 0
NIBBLE GROUP 0
CONVERTER 0, SAMPLE 0
1 CONVERTER
(M = 1)
D15 ... D0
DAC0
11675-036
Setting
0x00 or 0x80
0x01
0x0F or 0x1F
0x00
0x0F
0x0F or 0x2F
0x20
0x00
0x01
0x02
0x01
J15 J14
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
0x45A
0x46C
0x476
0x47D
AD9144
Data Sheet
4.
5.
6.
7.
8.
9.
PRBS Pattern
PRBS7
PRBS15
PRBS31
The STPL test ensures that each sample from each converter is
mapped appropriately according to the number of converters (M)
and the number of samples per converter (S). As specified in
the JESD204B standard, the converter manufacturer specifies
what test samples are transmitted. Each sample must have a
unique value. For example, if M = 2 and S = 2, there are 4
unique samples transmitted repeatedly until the test is stopped.
The expected sample must be programmed into the device, and
the expected sample is compared to the received sample one
sample at a time until all have been tested. The process for
performing this test on the AD9144 is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
Data Sheet
AD9144
2.
Select the desired link lane and error type of the counter to
view. Write these to Register 0x46B according to Table 60.
To select a link lane, first select a link (Register 0x300[2] =
0 to select Link 0 or Register 0x300[2] = 1 to select Link 1
(dual-link only)).
Note that when using Link 1, Link Lane x refers to Logical
Lane x + 4.
Read the error count from Register 0x46B. Note that the
maximum error count is equal to the error threshold set in
Register 0x47C.
Bits
[6:4]
[1:0]
Variable
LaneSel
CntrSel
Description
LaneSel = x to monitor the error
count of Link Lane x. See the notes
on link lane in Step 1 of the Checking
Error Counts section.
CntrSel = 0b00 for bad running
disparity counter.
CntrSel = 0b01 for not in table error
counter.
CntrSel = 0b10 for unexpected control
character counter.
2.
3.
Variable
RstIRQ
Disable_ErrCnt
RstErrCntr
[2:0]
LaneAddr
Description
RstIRQ = 1 to reset IRQ for the lane
selected in Bits[2:0].
Disable_ErrCnt = 1 to disable the error
count for the lane selected in Bits[2:0].
RsteErrCntr = 1 to reset the error
count for the lane selected in Bits[2:0].
LaneAddr = x to monitor the error
count of Link Lane x. See the notes on
link lane in Step 1 of the Checking
Error Counts section.
AD9144
Data Sheet
Table 63. Sync Assertion Mask
Addr.
0x47B
PClockFactor
(Frames/PClock)
4
2
1
SYNCB_ERR_DUR
These register settings assert the SYNCOUTx signal for 2 frame clock cycles
pulse widths.
2.
3.
4.
Bit No.
7
Bit Name
BADDIS_S
NIT_S
UCC_S
Description
Set to 1 to assert SYNCOUTx
if the disparity error count
reaches the threshold
Set to 1 to assert SYNCOUTx
if the not in table error count
reaches the threshold
Set to 1 to assert SYNCOUTx
if the unexpected control
character count reaches the
threshold
Data Sheet
AD9144
HARDWARE CONSIDERATIONS
Power Supply Recommendations
The power supply domains are described in Table 64. The
power supplies can be grouped into separate PCB domains,
as show in Figure 63. All the AD9144 supply domains must
remain as noise free as possible for the best operation. Power
supply noise has a frequency component that affects performance,
and is specified in terms of V rms. Figure 64 shows the
recommended power supply components.
An LC filter on the output of the power supply is recommended
to attenuate the noise, and must be placed as close to the AD9144
as possible. An effective filter is shown in Figure 63. This filter
scheme reduces high frequency noise components. Each of the
power supply pins of the AD9144 must also have a 0.1 F capacitor
connected to the ground plane, as shown in Figure 63. Place the
capacitor as close to the supply pin as possible. Adjacent power
pins can share a bypass capacitor. Connect the ground pins of
the AD9144 to the ground plane using vias.
Voltage (V)
1.2
1.2
1.2
1.2
1.8
1.2
3.3
3.3
Circuitry
Digital core
DAC PLL
JESD204B receiver interface
DAC clocking
SPI interface
VTT
Sync LVDS transmit
DAC
This supply requires a 1.3 V supply when operating at maximum DAC sample
rates. See Table 3 for details.
2
This supply can be combined with CVDD12 on the same regulator with a
separate supply filter network and sufficient bypass capacitors near the pins.
3
This supply requires a 1.3 V supply when operating at maximum interface
rates. See Table 4 for details.
4
This supply can be connected to SVDD12 and does not need separate
circuitry.
AD9144
Data Sheet
1.8V FPGA VCCIO
OR
OTHER SYSTEM SUPPLY
10H
IOVDD
66
10F
1.2V
LINEAR
REGULATOR
DVDD12
13
10F
14
53
3.3V
LINEAR
REGULATOR
SIOVDD33
35
10F
AVDD33
67
75
1.2V
LINEAR
REGULATOR
SVDD12
17
10F
77
20
85
22
28
1.2V
LINEAR
REGULATOR
10H
31
CVDD12
10F
71
32
76
33
81
36
87
39
45
10H
PVDD12
10F
47
50
7
VTT
8
21
10F
25
10
42
56
46
AD9144
1.8V
POWER
INPUT
+12V
ADP1741
ADP2119
ADP1741
ADP1753
BUCK
1.2MHz/600kHz
800mA
3.8V
ADM7154-3.3
1.2V
1.2V
SVDD12 + V TT
DVDD12
CVDD12 + PVDD12
3.3V
AVDD33
3.3V
IOVDD + SIOVDD33
ADP2370
ADM7160-3.3
11675-464
+3.3V
STEP-DOWN DDC
1.2MHz, 2A
1.2V
11675-039
57
NOTES
1. UNLABELED CAPACITORS ARE 0.1F, AS CLOSE AS POSSIBLE TO DEVICE PIN(S), WITH MINIMUM DISTANCE
AND VIAS BETWEEN CAPACITORS AND PIN(S).
Data Sheet
AD9144
Return Loss
DIFF
LAYER 3
LAYER 4
GND
STANDARD VIA
LAYER 5
DIFF+
LAYER 6
GND
LAYER 7
LAYER 8
Figure 65. Minimizing Stub Effect and Adding Ground Vias for
Differential Stripline Traces
11675-040
Signal Skew
There are many sources for signal skew, but the two sources to
consider when laying out a PCB are interconnect skew within a
single JESD204B link and skew between multiple JESD204B
links. In each case, keeping the channel lengths matched to
within 15 mm is adequate for operating the JESD204B link at
speeds of up to 10.6 Gbps. Managing the interconnect skew
within a single link is fairly straightforward. Managing multiple
links across multiple devices is more complex. However, follow
the 15 mm guideline for length matching.
Topology
Structure the differential SERDINx pairs to achieve 50 to
ground for each half of the pair. Stripline vs. microstrip tradeoffs are described in the Insertion Loss section. In either case,
it is important to keep these transmission lines separated from
potential noise sources such as high speed digital signals and
noisy supplies. If using stripline differential traces, route them
using a coplanar method, with both traces on the same layer.
Although this does not offer more noise immunity than the
broadside routing method (traces routed on adjacent layers),
it is easier to route and manufacture so that the impedance
continuity is maintained. An illustration of broadside vs.
coplanar differential routing techniques is shown in Figure 66.
Tx DIFF A
Tx DIFF B
Tx ACTIVE
Tx
DIFF A
Tx
DIFF B
Tx
ACTIVE
11675-041
Insertion Loss
AD9144
Data Sheet
SYNCOUTx, SYSREF, and CLK Signals
TIGHTLY COUPLED
DIFFERENTIAL Tx LINES
Tx
DIFF A
Tx
DIFF B
LOOSELY COUPLED
DIFFERENTIAL Tx LINES
AC Coupling Capacitors
The AD9144 requires that the JESD204B input signals be
ac-coupled to the source. These capacitors must be 100 nF and
placed as close as possible to the transmitting logic device. To
minimize the impedance mismatch at the pads, select the
package size of the capacitor so that the pad size on the PCB
matches the trace width as closely as possible.
LANE 0
LANE 1
Tx
DEVICE
Rx
DEVICE
LANE N 1
LANE N
SYSREF
DEVICE CLOCK
SYSREF
CLOCK SOURCE
(AD9516-1, ADCLK925)
DEVICE CLOCK
11675-043
Tx
DIFF B
11675-042
Tx
DIFF A
Data Sheet
AD9144
INPUT
POWER
DETECTION
AND
PROTECTION
INTERPOLATION
MODES
1, 2, 4, 8
COARSE
AND
FINE
MODULATION
INV
SINC
DIGITAL GAIN,
PHASE OFFSET,
DC OFFSET,
AND
GROUP DELAY
ADJUSTMENT
11675-049
DIGITAL DATAPATH
DUAL PAGING
Digital datapath registers are paged to allow configuration of
either DAC dual independently or both simultaneously. Table 65
shows how to use the dual paging register.
Table 65. Paging Modes
Duals
Paged
A
B
A and B
INTERP_MODE,
Reg 0x112[2:0]
0x00
0x01
0x03
0x04
Usable
Bandwidth
0.5 fDATA
0.4 fDATA
0.4 fDATA
0.4 fDATA
Maximum
fDATA (MHz)
10601
10601
700
350
Filter Performance
DACs Updated
DAC0 and DAC1
DAC2 and DAC3
DAC0, DAC1, DAC2, and DAC3
DATA FORMAT
2
4
8
MAGNITUDE (dB)
20
40
60
80
100
0.2
0.4
0.6
0.8
FREQUENCY (fDAC )
1.0
11675-368
DUAL_PAGE,
Reg. 0x008[1:0]
1
2
3 (default)
INTERPOLATION FILTERS
AD9144
Data Sheet
The NCO produces a quadrature carrier to translate the input
signal to a new center frequency. A quadrature carrier is a pair of
sinusoidal waveforms of the same frequency, offset 90 from
each other. The frequency of the quadrature carrier is set via an
FTW. The quadrature carrier is mixed with the I and Q data and
then summed into the I and Q datapaths, as shown in Figure 72.
80
0.1
70
0.2
60
0.3
50
0.4
40
30
20
40
0.5
IMAGE REJECTION
PASS-BAND RIPPLE
41
42
43
44
BANDWIDTH (% fDATA )
45
0.6
90
11675-369
Value
FTW[7:0]
FTW[15:8]
FTW[23:16]
FTW[31:24]
FTW[39:32]
FTW[47:40]
Description
8 LSBs of FTW
Next 8 bits of FTW
Next 8 bits of FTW
Next 8 bits of FTW
Next 8 bits of FTW
8 MSBs of FTW
DIGITAL MODULATION
I DATA
COS(n + )
NCO
SIN(n + )
FTW[47:0]
NCO_PHASE_OFFSET
[15:0]
OUT_I
OUT_Q
+
1
SEL_SIDEBAND
Q DATA
INTERPOLATION
11675-056
Modulation Mode
None
NCO Fine Modulation
Coarse fDAC/4
Coarse fDAC/8
INTERPOLATION
Data Sheet
AD9144
Value
PhaseOffsetI[7:0]
PhaseOffset[15:8]
INVERSE SINC
Digital Gain
SIN(x)/x ROLL-OFF
SINC1 FILTER RESPONSE
COMPOSITE RESPONSE
0 Gain 4095/2048
dB dBGain 6.018 dB
MAGNITUDE (dB)
dBGain = 20 log10(Gain)
GainCode = 2048 Gain = 2048 10dBGain/20
0.05
0.10
0.15
0.20
0.25
0.30
0.35
FREQUENCY ( fDAC )
0.40
0.45
0.50
11675-058
Figure 73. Responses of sin(x)/x Roll-Off, the Sinc1 Filter, and the Composite
of the Two Input Signal Power Detection and Protection
AD9144
Data Sheet
Group Delay
Value
DIG_GAIN_ENABLE
GainCodeI[7:0]
GainCodeI[11:8]
GainCodeQ[7:0]
GainCodeQ[11:8]
Description
Set to 1 to enable digital gain
I DAC LSB gain code
I DAC MSB gain code
Q DAC LSB gain code
Q DAC MSB gain code
Phase Adjust
Ordinarily, the I and Q channels of each DAC pair have an
angle of 90 between them. The phase adjust feature changes the
angle between the I and Q channels, which can help balance the
phase into a modulator.
14 DegreesAdjust < 14
PhaseAdj = (DegreesAdjust/14) 212
I TO Q SWAP
I_TO_Q (Register 0x111[0], paged as described in the Dual
Paging section) is a convenience bit that can be set to send the
I datapath to the Q DAC. Note that this operation occurs at the
end of the datapath (after any modulation, digital gain, phase
adjust, and phase offset).
NCO ALIGNMENT
Value
PHASE_ADJ_ENABLE
0x11C
0x11D[4:0]
PhaseAdj[7:0]
PhaseAdj[12:8]
Description
Set to 1 to enable phase
adjust
LSB phase adjust code
MSB phase adjust code
DC Offset
1.
Value
DC_OFFSET_ON
LSBsOffsetI[7:0]
LSBsOffsetI[15:8]
LSBsOffsetQ[7:0]
LSBsOffsetQ[15:8]
SixteenthsOffsetI
0x13B[4:0]
SixteenthsOffsetQ
Description
Set to 1 to enable dc offset
I DAC LSB dc offset code
I DAC MSB dc offset code
Q DAC LSB dc offset code
Q DAC MSB dc offset code
I DAC sub-LSB dc offset
code
Q DAC sub-LSB dc offset
code
2.
3.
4.
Data Sheet
AD9144
3.
4.
5.
AD9144
Data Sheet
DOWNSTREAM PROTECTION
FILTER
AND
MODULATION
DATA
PDP
DIGITAL
GAIN
PDP_PROTECT
FROM LMFC
SYNC LOGIC
BSM
DATA TO DACs
1
BSM_PROTECT
0
PDP_PROTECT_OUT
TXENx
TxEnSm
Tx_PROTECT
Tx_PROTECT_OUT
SPI_PROTECT
PROTECT_OUTx
PROTECT_OUT_INVERT
SPI_PROTECT_OUT
PROTECT OUTx GENERATION
11675-372
Data Sheet
AD9144
Table 74. TxEnSM Registers
0x063
0x064
Bit
No.
[7:0]
Value
PDP_THRESHOLD[7:0]
[4:0]
7
[3:0]
PDP_THRESHOLD[12:8]
PDP_ENABLE
PDP_AVG_TIME
[7:0]
[4:0]
PDP_POWER[7:0]
PDP_POWER[12:8]
Description
Power that triggers
PDP_PROTECT. 8 LSBs.
5 MSBs.
Set to 1 to enable PDP.
Can be set from 0 to
10. Averages across
2(9 + PDP_AVG_TIME), IQ
sample pairs.
If PDP_THRESHOLD
is crossed, this reads
back the maximum
power seen. If not,
this reads back the
instantaneous power.
8 LSBs.
5 MSBs.
Addr.
0x11F
Bit No.
[7:6]
Value
FALL_COUNTERS
[5:4]
RISE_COUNTERS
0x121
[7:0]
RISE_COUNT_0
0x122
[7:0]
RISE_COUNT_1
0x123
[7:0]
FALL_COUNT_0
0x124
[7:0]
FALL_COUNT_1
Description
Number of fall counters
to use (1 to 2).
Number of rise
counters to use (0 to 2).
Delay TX_PROTECT rise
from TXEN rising edge
by 32 RISE_COUNT_0
DAC clock cycles.
Delay TX_PROTECT rise
from TXEN rising edge
by 32 RISE_COUNT_1
DAC clock cycles.
Delay TX_PROTECT rise
from TXEN rising edge
by 32 FALL_COUNT_0
DAC clock cycles. Must
be at least 0x12.
Delay TX_PROTECT rise
from TXEN rising edge
by 32 FALL_COUNT_1
DAC clock cycles.
Ramping
For proper ramping, digital gain must be enabled; tie TXEN
high if disabling digital gain.
The step size to use when ramping gain to 0 or its assigned value
can be controlled via the GAIN_RAMP_DOWN_STEP registers
(Register 0x142 and Register 0x143) and the GAIN_RAMP_
UP_STEP registers (Register 0x140 and Register 0x141). These
registers are paged as described in the Dual Paging section.
The current BSM state can be read back as shown in Table 75.
AD9144
Data Sheet
Value
0b00
0b01
0b10
0b11
Description
Data is being held at midscale.
Ramping gain to 0. Data ramping to
midscale.
Ramping gain to assigned value. Data
ramping to normal amplitude.
Data at normal amplitude.
PROTECT_OUTx Generation
Register 0x013 controls which signals are ORed into the external
PROTECT_OUTx signal. Register 0x11F[2] can be used to
invert the PROTECT_OUTx signal, By default, PROTECT_OUTx
is high when the output is valid. Both of these registers are
paged as described in the Dual Paging section.
Table 76. PROTECT_OUTx Registers
Addr.
0x013
0x11F
Bit No.
6
Value
PDP_PROTECT_OUT
TX_PROTECT_OUT
SPI_PROTECT_OUT
2
2
SPI_PROTECT
PROTECT_OUT_
INVERT
Description
1: PDP block triggers
PROTECT_OUT
1: TxEnSM triggers
PROTECT_OUT
1: SPI_PROTECT
triggers PROTECT_OUT
Sets SPI_PROTECT
Inverts
PROTECT_OUTx
DATAPATH PRBS
The datapath PRBS can be used to verify that the AD9144
datapath is receiving and correctly decoding data. The datapath
PRBS verifies that the JESD204B parameters of the transmitter
and receiver match, that the lanes of the receiver are mapped
appropriately, that the lanes have been appropriately inverted,
if necessary, and in general that the start-up routine has been
implemented correctly.
DC TEST MODE
As a convenience, the AD9144 provides a dc test mode, which
is enabled by setting Register 0x520[1] to 1 and clearing
Register 0x146[0] to 0. When this mode is enabled, the datapath
is given 0 (midscale) for its data. Register 0x146[0] must be set
to 1 for all other modes of operation.
In conjunction with dc offset, this test mode can provide desired dc
data to the DACs. This test mode can also provide sinusoidal data
to the DACs by combining digital modulation (to set frequency)
and dc offset (to set amplitude). See the DC Offset section.
Data Sheet
AD9144
EVENT
Reported
Per chip
EVENT_STATUS
INTERRUPT_SOURCE if
IRQ is enabled; if not, it
is EVENT
INTERRUPT_SOURCE if
IRQ is enabled; if not, 0
INTERRUPT_SOURCE if
IRQ is enabled; if not, 0
Read the status of the event flag bits that are being monitored.
Disable the interrupt by writing 0 to IRQ_EN.
Read the EVENT source. For Register 0x01F to
Register 0x026, EVENT_STATUS has a live readback.
For other events, see their registers.
Perform any actions required to clear the cause of the
EVENT. In many cases, no specific actions are required.
Verify that the EVENT source is functioning as expected.
Clear the interrupt by writing 1 to IRQ_RESET.
Enable the interrupt by writing 1 to IRQ_EN.
4.
5.
6.
7.
0
1
EVENT_STATUS
STATUS_MODE
IRQ
IRQ_EN
INTERRUPT_SOURCE
0
1
EVENT
IRQ_EN
OTHER
INTERRUPT
SOURCES
IRQ_RESET
11675-060
DEVICE_RESET
IRQ_EN
0x01F to 0x022; R/W per chip
0x47A; W per link
0x470 to 0x473
0x47B[4]
EVENT_STATUS
0x023 to 0x26; R per chip
0x47A; R per link
0x47A; R per link
0x47B[4]; R per link
AD9144
Data Sheet
Register
Value
0x62
0xC9
0x0E
0x12
0x7B
0x00
0x1B9
0x1BC
0x1BE
0x24
0x0D
0x02
0x1BF
0x1C0
0x8E
0x2A
0x1C1
0x1C4
0x2A
0x7E
Description
Optimal DAC PLL loop filter settings
Optimal DAC PLL loop filter settings
Optimal DAC PLL loop filter settings
Optimal DAC PLL charge pump settings
Optimal DAC LDO settings for DAC PLL
Power DAC PLL blocks when power
machine disabled
Optimal DAC PLL charge pump settings
Optimal DAC PLL VCO control settings
Optimal DAC PLL VCO power control
settings
Optimal DAC PLL VCO calibration settings
Optimal DAC PLL lock counter length
setting
Optimal DAC PLL charge pump setting
Optimal DAC PLL varactor settings
CLOCK MULTIPLICATION
CLK+
5k
600mV
11675-061
5k
CLK
Data Sheet
AD9144
REF_DIV_MODE,
Reg. 0x08C[2:0]
0
1
2
3
4
f REF
80 MHz
RefDivFactor
(1)
where:
RefDivFactor is the reference divider division ratio.
fREF is the reference frequency on the CLK input pins.
Frequency
(MHz)
368.64
184.32
307.2
122.88
61.44
491.52
245.76
fVCO
(MHz)
11796.48
11796.48
9831.04
7864.35
7864.35
7864.35
7864.35
RefDivFactor
8
4
8
2
1
8
4
f DACCLK
f REF
RefDivFactor
2 BCount
(2)
where:
BCount is the feedback loop divider ratio.
fDACCLK is the DAC sample clock.
TO VCO
R1
C2
C3
C1
TO VCO LDO
Charge Pump
The charge pump current is 6-bit programmable and varies from
0.1 mA to 6.4 mA in 0.1 mA steps. The charge pump current is
programmed into Register 0x08A for the DAC PLL, as shown in
the DAC PLL Fixed Register Writes section. The charge pump
calibration must be run one time during chip initialization to
reduce reference spurs. This calibration is on by default.
(4)
Divide by
(LODivFactor)
4
8
16
TO LOOP FILTER
DOWN
UP
LO_DIV_MODE,
Register 0x08B[1:0]
1
2
3
Rev. A | Page 77 of 125
11675-063
f DACCLK 2 BCount
BCount
16
16
16
8
8
16
16
Loop Filter
The BCount value is the divide ratio of the loop divider. It is set
to divide the fDACCLK to frequency match the fREF/RefDivFactor.
Select BCount so that the following equation is true:
LODivFactor
8
8
8
8
8
4
4
11675-062
DAC Reference
Frequency Range (MHz)
35 to 80
80 to 160
160 to 320
320 to 640
640 to 1000
AD9144
Data Sheet
4.
Temperature Tracking
When properly configured, the device automatically selects one
of the 512 VCO bands. The PLL settings selected by the device
ensure that the PLL remains locked over the full 40C to +85C
operating temperature range of the device without further
adjustment. The PLL remains locked over the full temperature
range even if the temperature during initialization is at one of
the temperature extremes. Check the PLL lock bit to make sure
that the calibration completed properly. The PLL lock bit is Bit 1
of Register 0x084.
5.
6.
7.
Register 0x084[5] notifies the user that the DAC PLL calibration is
completed and is valid.
Register 0x084[1] notifies the user that the PLL has locked.
Register 0x084[7] and Register 0x084[6] notify the user that the
DAC PLL hit the upper or lower edge of its operating band,
respectively. If either of these bits are high, recalibrate the DAC
PLL by setting Register 0x083[7] to 0 and then 1.
CHARGE
PUMP
fREF
35MHz
TO 1GHz
2
4
8
16
The DAC PLL lock and lost signals are available as IRQ events.
Use Register 0x01F[5:4] to enable these signals, and then use
Register 0x023[5:4] to read back their statuses and reset the IRQ
signals. See the Interrupt Request Operation section for more
information.
4-BIT
PROGRAMMABLE,
INTEGRATED
LOOP FILTER
VCO
LDO
PFD
80MHz
MAX
C1
RETIMER
UP
C2
LC VCO
6GHz
TO
12GHz
C3
R1
DOWN
R3
2
I
2
I
ALC CAL
FO CAL
CAL CONTROL BITS
0.1mA TO 6.4mA
MUX/SELECTABLE BUFFERS
LODivFactor =
4, 8, 16
B COUNTER
BCount (INTEGER FEEDBACK DIVIDER)
RANGE = 6 TO 127
DAC CLOCK
420MHz TO 2.8GHz
11675-064
RefDivFactor
<750MHz
Register
0x1BB
Setting
0x03
0x03
0x13
750MHz TO 1.5GHz
Register
0x1B5
Setting
0x08
0x09
0x09
>1.5GHz
VCO Frequency
Range (GHz)
fVCO < 6.3
6.3 fVCO < 7.25
fVCO 7.25
Data Sheet
AD9144
ANALOG OUTPUTS
TRANSMIT DAC OPERATION
Address
0x040[1:0]
0x041[7:0]
0x042[1:0]
0x043[7:0]
0x044[1:0]
0x045[7:0]
0x046[1:0]
0x047[7:0]
1.2V
Q DACs
FULL-SCALE
ADJUST
DAC3
Value
DACFSC_0[9:8]
DACFSC_0[7:0]
DACFSC_1[9:8]
DACFSC_1[7:0]
DACFSC_2[9:8]
DACFSC_2[7:0]
DACFSC_3[9:8]
DACFSC_3[7:0]
Description
Dual A I DAC MSB gain code
Dual A I DAC LSB gain code
Dual A Q DAC MSB gain code
Dual A Q DAC LSB gain code
Dual B I DAC MSB gain code
Dual B I DAC LSB gain code
Dual B Q DAC MSB gain code
Dual B Q DAC LSB gain code
OUT3+
28
OUT3
26
OUT2+
4k
I DACs
FULL-SCALE
ADJUST
IOUTFS (mA)
DAC1
OUT1+
OUT1
OUT0+
DAC0
OUT0
11675-065
I120
24
OUT2
CURRENT
SCALING
22
20
18
16
14
12
512
256
128
128
256
384
512
Figure 81. DAC Full-Scale Current (IOUTFS) vs. DAC Gain Code
IOUTP
384
11675-066
DAC2
DACCODEBIN
IOUTFS
2N 1
(5)
(6)
DACCODETWOS 2N 1
IOUTFS
2N 1
(7)
(8)
AD9144
Data Sheet
4
Register 0x011, Bit 7 and Bit 2, must stay low to enable the band
gap and DAC master bias, respectively.
CALIBRATION OFF
CALIBRATION ON
2
DNL (LSB)
30k
40k
50k
60k
70k
CALIBRATION OFF
CALIBRATION ON
SECOND HARMONIC
FOURTH HARMONIC
50
60
70
80
90
100
0
50
100
150
200
250
300
fOUT (MHz)
60
CALIBRATION OFF
CALIBRATION ON
1
65
0
70
IMD2 (dBc)
1
2
3
10k
20k
30k
40k
50k
60k
70k
75
80
85
90
95
100
50
100
150
200
250
fOUT (MHz)
300
11675-096
11675-088
INL (LSB)
20k
CALIBRATION OFF
CALIBRATION ON
10k
11675-095
SFDR (dBc)
11675-089
Self Calibration
Data Sheet
AD9144
0x0E7
SPI Data
Byte
0x38
0x0F
0xA2
0x01
0x03
0b10
0x30
Description
Enable calibration clock.
Calibrate all DACs.
Configure initial value.
Enable averaged calibration.
Start averaged calibration.
CAL_PASS (Register 0x023[7]) = 1 to
indicate that the calibration passed.
If CAL_PASS = 0, check CAL_FAIL
(Register 0x023[6]). If both CAL_PASS =
0 and CAL_FAIL = 0, calibration is
either still running or it never ran.
Try waiting ~100 ms and reread
CAL_PASS and CAL_FAIL, or rerun the
calibration routine.
Disable calibration clock.
40C
+25C
+85C
50
SECOND HARMONIC
FOURTH HARMONIC
60
SFDR (dBc)
70
80
Bit
0x0E8
3
2
1
0
0x0ED
0x0E9
0x0E9
0x0E7
0b0 or 0b1
0b0 or 0b1
0b0 or 0b1
0b0 or 0b1
0xA2
0x01
0x03
0x30
Description
Use highest comparator speed
and set calibration clock divider
Select DACs to calibrate
1 if DAC3 is enabled
1 if DAC2 is enabled
1 if DAC1 is enabled
1 if DAC0 is enabled
Configure initial value
Enable calibration
Start calibration
Disable calibration clock
50
100
150
250
300
Figure 86. Post-Calibration HD2 and HD4 over Temperature, Calibrated at 25C
60
40C
+25C
+85C
65
70
75
80
85
90
95
100
50
100
150
fOUT (MHz)
200
fOUT (MHz)
11675-486
200
250
300
11675-487
Addr.
0x0E7
SPI Data
Byte
0x38
100
IMD2 (dBc)
90
AD9144
Data Sheet
TEMPERATURE SENSOR
The AD9144 has a band gap temperature sensor for monitoring
the temperature changes of the AD9144. The temperature must
be calibrated against a known temperature to remove the
device-to-device variation on the band gap circuit used to sense
the temperature.
To monitor temperature change, the user must take a reading at
a known ambient temperature for a single-point calibration of
each AD9144 device.
Tx = TREF + 7.3 (CODE_X CODE_REF)/1000
where:
CODE_X is the readback code at the unknown temperature, Tx.
CODE_REF is the readback code at the calibrated temperature,
TREF.
To use the temperature sensor, it must be enabled by setting
Register 0x12F[0] to 1. The user must write a 1 to Register 0x134[0]
before reading back the die temperature from Register 0x132
and Register 0x133.
Data Sheet
AD9144
START-UP SEQUENCE
Table 87 through Table 96 show the register writes needed to set
up the AD9144 with fDAC = 1474.56 MHz, 2 interpolation, and
the DAC PLL enabled with a 368.64 MHz reference clock. The
JESD204B interface is configured in Mode 4, dual-link mode,
Subclass 1, and scrambling is enabled with all eight SERDES
lanes running at 7.3728 Gbps, inputting twos complement
formatted data. No remapping of lanes with the crossbar is
done in this example.
Address
0x087
Value
0x62
0x088
0xC9
0x089
0x0E
0x08A
0x12
1.
0x08D
0x7B
0x1B0
0x00
0x1B9
0x24
0x1BC
0x0D
0x1BE
0x02
0x1BF
0x8E
0x1C0
0x2A
0x1C1
0x2A
0x1C4
0x7E
0x08B
0x02
0x08C
0x03
0x085
0x10
0x1B5
0x09
0x1BB
0x13
0x1C5
0x06
W
R
0x083
0x084
0x10
0x01
2.
3.
4.
5.
6.
Address
0x000
0x000
0x011
Value
0xBD
0x3C
0x00
W
W
0x080
0x081
0x00
0x00
Description
Soft reset
Deassert reset, set 4-wire SPI
Enable reference, DAC
channels, and master DAC
Power up all clocks
Power up SYSREF receiver,
disable hysteresis
Address
0x12D
Value
0x8B
0x146
0x01
W
W
0x2A4
0x232
0xFF
0xFF
0x333
0x01
Description
Digital datapath
configuration
Digital datapath
configuration
Clock configuration
SERDES interface
configuration
SERDES interface
configuration
Description
Optimal DAC PLL loop filter
settings
Optimal DAC PLL loop filter
settings
Optimal DAC PLL loop filter
settings
Optimal DAC PLL charge
pump settings
Optimal DAC LDO settings
for DAC PLL
Power DAC PLL blocks when
power machine is disabled
Optimal DAC PLL charge
pump settings
Optimal DAC PLL VCO
control settings
Optimal DAC PLL VCO
power control settings
Optimal DAC PLL VCO
calibration settings
Optimal DAC PLL lock
counter length setting
Optimal DAC PLL charge
pump setting
Optimal DAC PLL varactor
settings
Set the VCO LO divider to 8
so that 6 GHz fVCO = fDACCLK
2(LODivMode + 1) 12 GHz
Set the reference clock divider
to 8 so that the reference
clock into the PLL is less
than 80 MHz
Set the B counter to 16 to
divide the DAC clock down
to 2 the reference clock
PLL lookup value from
Table 25 for fVCO 7.25GHz
PLL lookup value from
Table 25 for fVCO 7.25GHz
PLL lookup value from
Table 25 for fVCO 7.25GHz
Enable DAC PLL
Verify that Bit 1 reads back
high for PLL locked
Address
0x112
0x110
Value
0x01
0x00
Description
Set the interpolation to 2
Set twos complement data
format
AD9144
Data Sheet
Address
0x200
0x201
0x300
Value
0x00
0x00
0x08
0x450
0x00
0x451
0x00
0x452
0x00
0x453
0x83
W
W
W
W
W
0x454
0x455
0x456
0x457
0x458
0x00
0x1F
0x01
0x0F
0x2F
0x459
0x20
W
W
W
W
W
0x45A
0x45D
0x46C
0x476
0x47D
0x80
0x45
0x0F
0x01
0x0F
Command
W
Address
0x2AA
Value
0xB7
0x2AB
0x87
0x2B1
0xB7
0x2B2
0x87
W
W
W
W
0x2A7
0x2AE
0x314
0x230
0x01
0x01
0x01
0x28
W
W
W
0x206
0x206
0x289
0x00
0x01
0x04
0x284
0x62
0x285
0xC9
0x286
0x0E
0x287
0x12
0x28A
0x7B
0x28B
0x00
0x290
0x89
0x294
0x24
W
W
W
0x296
0x297
0x299
0x03
0x0D
0x02
0x29A
0x8E
0x29C
0x2A
0x29F
0x78
0x2A0
0x06
W
R
0x280
0x281
0x01
0x01
0x268
0x62
Address
0x300
Value
0x0C
0x450
0x00
0x451
0x00
0x452
0x04
0x453
0x83
W
W
W
W
W
0x454
0x455
0x456
0x457
0x458
0x00
0x1F
0x01
0x0F
0x2F
0x459
0x20
W
W
W
W
W
0x45A
0x45D
0x46C
0x476
0x47D
0x80
0x45
0x0F
0x01
0x0F
Description
Bit 3 = 1 for dual-link, Bit 2 = 1
to access registers for Link 1
Set the device ID to match
Tx (0x00 in this example)
Set the bank ID to match Tx
(0x00 in this example)
Set the lane ID to match Tx
(0x04 in this example)
Set descrambling and L = 4
(in n 1 notation)
Set F = 1 (in n 1 notation)
Set K = 32 (in n 1 notation)
Set M = 2 (in n 1 notation)
Set N = 16 (in n 1 notation)
Set Subclass 1 and NP = 16
(in n 1 notation)
Set JESD204B and S = 1
(in n 1 notation)
Set HD
Set checksum for Lane 0
Deskew Lane 4 to Lane 7
Set F (not in n 1 notation)
Enable Lane 4 to Lane 7
Description
SERDES interface
termination setting
SERDES interface
termination setting
SERDES interface
termination setting
SERDES interface
termination setting
Autotune PHY setting
Autotune PHY setting
SERDES SPI configuration
Configure CDRs in half rate
mode
Resets CDR logic
Release CDR logic reset
Configure PLL divider to 1
along with PLL required
configuration
Optimal SERDES PLL loop
filter
Optimal SERDES PLL loop
filter
Optimal SERDES PLL loop
filter
Optimal SERDES PLL charge
pump
Optimal SERDES PLL VCO
LDO
Optimal SERDES PLL
configuration
Optimal SERDES PLL VCO
varactor
Optimal SERDES PLL charge
pump
Optimal SERDES PLL VCO
Optimal SERDES PLL VCO
Optimal SERDES PLL
configuration
Optimal SERDES PLL VCO
varactor
Optimal SERDES PLL charge
pump
Optimal SERDES PLL VCO
varactor
Optimal SERDES PLL VCO
varactor
Enable SERDES PLL
Verify that Bit 0 reads back
high for SERDES PLL lock
Set EQ mode to low power
Data Sheet
AD9144
Link 0 Checks
Confirm that the registers in Table 95 read back as noted and
that system tasks are completed as described.
Address
0x301
0x304
Value
0x01
0x00
0x305
0x00
0x306
0x0A
0x307
0x0A
0x03A
0x01
W
W
SYSREF
Signal
0x03A
0x03A
0x81
0xC1
0x300
0x0B
Description
Set subclass to 1
Set the LMFC delay setting
to 0
Set the LMFC delay setting
to 0
Set the LMFC receive buffer
delay to 10
Set the LMFC receive buffer
delay to 10
Set sync mode to one-shot
sync
Enable the sync machine
Arm the sync machine
Ensure that at least one
SYSREF edge is sent to the
device
Bit 1 and Bit 0 = 1 to enable
Link 0 and Link 1, Bit 2 = 0
to access Link 0
Address
0x470
Value
0x0F
SYNCOUT0
Signal
SERDINx
Signals
R
0x471
0x0F
R
R
0x472
0x473
0x0F
0x0F
Description
Acknowledge that four
consecutive K28.5 characters
have been detected on Lane 0
to Lane 3.
Confirm that SYNCOUT0 is
high.
Apply ILAS and data to
SERDES input pins.
Check for frame sync on all
lanes.
Check for good checksum.
Check for ILAS.
Link 1 Checks
Confirm that the registers in Table 96 read back as noted and
that system tasks are completed as described.
Table 96. Link 1 Checks
Command
W
R
Address
0x300
0x470
Value
0x0F
0x0F
SYNCOUT0
Signal
SERDINx
Signals
R
0x471
0x0F
R
R
0x472
0x473
0x0F
0x0F
Description
Bit 2 = 1 to access Link 1.
Acknowledge that four
consecutive K28.5 characters
have been detected on Lane 4
to Lane 7.
Confirm that SYNCOUT0 is
high.
Apply ILAS and data to
SERDES input pins.
Check for frame sync on all
lanes.
Check for good checksum.
Check for ILAS.
AD9144
Data Sheet
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
R/W
0x000
SPI_INTFCONFA
SOFT
RESET_M
LSBFIRST_
M
ADDRINC_M
SDOACTIVE_M
SDOACTIVE
ADDRINC
LSBFIRST
SOFTRESET
0x00
R/W
0x003
CHIPTYPE
CHIPTYPE
0x04
0x004
PRODIDL
PRODIDL
0x44
0x005
PRODIDH
0x006
CHIPGRADE
0x008
SPI_PAGEINDX
0x00A
SCRATCH_PAD
0x011
PWRCNTRL0
0x012
TXENMASK
0x013
PWRCNTRL3
PRODIDH
PROD_GRADE
DEV_REVISION
RESERVED
DUAL_PAGE
SCRATCHPAD
PD_BG
PD_DAC_0 PD_DAC_1
PD_DAC_2
PD_DAC_3
PD_DACM
RESERVED
RESERVED
PDP_
PROTECT_
OUT
IRQEN_
SMODE_
CALPASS
IRQEN_
SMODE_
CALFAIL
TX_PROTECT_ RESERVED
OUT
0x014
GROUP_DLY
0x01F
IRQEN_
STATUSMODE0
0x020
IRQEN_
STATUSMODE1
0x021
IRQEN_
STATUSMODE2
IRQEN_
SMODE_
PDPERR0
RESERVED
IRQEN_
SMODE_
BLNKDONE0
0x022
IRQEN_
STATUSMODE3
IRQEN_
SMODE_
PDPERR1
RESERVED
0x023
IRQ_STATUS0
CALPASS
CALFAIL
0x03
R/W
R/W
0x7C
R/W
0x00
R/W
RESERVED
0x20
R/W
DUALB_
MASK
RESERVED
R
R
0x00
RESERVED
SPI_PROTECT_OUT SPI_PROTECT
0x91
0x06
DUALA_
MASK
0x88
R/W
IRQEN_SMODE_
SERPLLLOST
IRQEN_SMODE_
SERPLLLOCK
GROUP_DLY
RESERVED
IRQEN_
SMODE_
LANEFIFOERR
0x00
R/W
IRQEN_SMODE_
PRBS3
IRQEN_SMODE_
PRBS2
IRQEN_
SMODE_
PRBS1
IRQEN_
SMODE_
PRBS0
0x00
R/W
IRQEN_SMODE
_NCO_ALIGN0
IRQEN_SMODE_
SYNC_LOCK0
IRQEN_SMODE_
SYNC_ROTATE0
IRQEN_
SMODE_
SYNC_
WLIM0
0x00
IRQEN_
SMODE_
SYNC_TRIP0
R/W
IRQEN_
SMODE_
BLNKDONE1
IRQEN_SMODE
_NCO_ ALIGN1
IRQEN_SMODE_
SYNC_LOCK1
IRQEN_
SMODE_SYNC_
ROTATE1
IRQEN_
SMODE_
SYNC_
WLIM1
0x00
IRQEN_
SMODE_
SYNC_TRIP1
R/W
DACPLLLOST
DACPLLLOCK
SERPLLLOST
SERPLLLOCK
LANEFIFOERR
RESERVED
0x00
IRQEN_
IRQEN_SMODE
SMODE_
_ DACPLLLOCK
DACPLLLOST
RESERVED
0x024
IRQ_STATUS1
PRBS3
PRBS2
PRBS1
PRBS0
0x00
0x025
IRQ_STATUS2
PDPERR0
RESERVED
RESERVED
BLNKDONE0
NCO_
ALIGN0
SYNC_
LOCK0
SYNC_
ROTATE0
SYNC_
WLIM0
SYNC_
TRIP0
0x00
0x026
IRQ_STATUS3
PDPERR1
RESERVED
BLNKDONE1
NCO_
ALIGN1
SYNC_
LOCK1
SYNC_
ROTATE1
SYNC_
WLIM1
SYNC_
TRIP1
0x00
0x030
JESD_CHECKS
RESERVED
ERR_JESDBAD
ERR_KUNSUPP
ERR_
SUBCLASS
ERR_
INTSUPP
0x00
0x034
SYNC_
ERRWINDOW
0x00
R/W
0x038
SYNC_LASTERR_L
0x00
0x039
SYNC_LASTERR_H LASTUNDER
LASTOVER
0x00
0x03A
SYNC_CONTROL
SYNCENABLE
SYNCARM
0x00
R/W
0x03B
SYNC_STATUS
SYNC_
BUSY
0x00
0x03C
SYNC_CURRERR_L
0x00
ERR_DLYOVER ERR_WINLIMIT
RESERVED
ERRWINDOW
RESERVED
LASTERROR
RESERVED
SYNCCLRSTKY
RESERVED
SYNCCLRLAST
SYNCMODE
SYNC_LOCK
RESERVED
SYNC_
ROTATE
SYNC_WLIM
CURRERROR
SYNC_
TRIP
Data Sheet
AD9144
Reg.
Name
Bit 7
Bit 6
0x03D
SYNC_
CURRERR_H
CURRUNDER
CURROVER
0x040
DACGAIN0_1
0x041
DACGAIN0_0
0x042
DACGAIN1_1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
R/W
0x00
DACFSC_0[9:8]
0x00
R/W
0x00
R/W
DACFSC_1[9:8]
0x00
R/W
0x00
R/W
DACFSC_2[9:8]
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
RESERVED
RESERVED
DACFSC_0[7:0]
RESERVED
0x043
DACGAIN1_0
0x044
DACGAIN2_1
DACFSC_1[7:0]
0x045
DACGAIN2_0
0x046
DACGAIN3_1
0x047
DACGAIN3_0
0x050
NCOALIGN_
MODE
0x051
NCOKEY_ILSB
NCOKEYI[7:0]
0x00
R/W
0x052
NCOKEY_IMSB
NCOKEYI[15:8]
0x00
R/W
RESERVED
DACFSC_2[7:0]
RESERVED
DACFSC_3[9:8]
DACFSC_3[7:0]
NCO_
ALIGN_
ARM
RESERVED
NCO_ALIGN_FAIL
NCO_ALIGN_ NCO_ALIGN_
MTCH
PASS
RESERVED
NCO_ALIGN_MODE
0x053
NCOKEY_QLSB
NCOKEYQ[7:0]
0x00
R/W
0x054
NCOKEY_QMSB
NCOKEYQ[15:8]
0x00
R/W
0x00
R/W
0x060
PDP_THRES0
0x061
PDP_THRES1
PDP_THRESHOLD[7:0]
0x062
PDP_AVG_TIME
0x063
PDP_POWER0
0x064
PDP_POWER1
0x080
CLKCFG0
PD_CLK01 PD_CLK23
0x081
SYSREF_ACTRL0
RESERVED
0x082
SYSREF_ACTRL1
0x083
DACPLLCNTRL
RECAL_
DACPLL
RESERVED
0x084
DACPLLSTATUS
DACPLL_
OVERRANGE_H
DACPLL_
OVERRANGE_L
0x085
DACINTEGERWORD0
0x087
DACLOOPFILT1
RESERVED
PDP_THRESHOLD[12:8]
RESERVED
PDP_
ENABLE
PDP_AVG_TIME
PDP_POWER[7:0]
RESERVED
PDP_POWER[12:8]
PD_CLK_DIG PD_SERDES_
PCLK
PD_SYSREF
PD_CLK_REC
RESERVED
HYS_ON
SYSREF_RISE
HYS_CNTRL1
DACLOOPFILT2
0x089
DACLOOPFILT3
LF_
BYPASS_
R3
0x08A
DACCPCNTRL
RESERVED
0x08B
DACLOGENCNTRL
0x08C
DACLDOCNTRL1
0x00
0x08
R/W
LF_C1_WORD
0x88
R/W
LF_C3_WORD
0x88
R/W
LF_R3_WORD
0x08
R/W
DACPLL_
LOCK
RESERVED
CP_CURRENT
LO_DIV_MODE
RESERVED
DACLDOCNTRL2
0x0E2
CAL_CTRL_
GLOBAL
0x0E7
CAL_CLKDIV
RESERVED
0x0E8
CAL_PAGE
RESERVED
0x0E9
CAL_CTRL
REF_DIV_MODE
DAC_LDO
RESERVED
CAL_FIN
0x0ED
CAL_INIT
0x110
DATA_FORMAT
BINARY_
FORMAT
0x111
DATAPATH_CTRL
INVSINC_
ENABLE
CAL_
ACTIVE
CAL_ERRHI
CAL_START_
AVG
CAL_CLK_EN
CAL_EN_
AVG
RESERVED
CAL_PAGE
CAL_ERRLO
RESERVED
CAL_START
CAL_EN
CAL_INIT
RESERVED
RESERVED
DIG_GAIN_
ENABLE
PHASE_ADJ_
ENABLE
MODULATION_TYPE
R/W
R/W
RESERVED
0x08D
0xF8
0x00
RESERVED
LF_BYPASS_C1
0x00
R/W
RESERVED
LF_R1_WORD
LF_
LF_BYPASS_
BYPASS_R1 C2
0x00
R/W
B_COUNT
0x088
R/W
0x10
ENABLE_
DACPLL
LF_C2_WORD
R/W
0x00
0x00
HYS_CNTRL0
DACPLL_
CAL_VALID
0x00
SEL_
SIDEBAND
I_TO_Q
0x20
R/W
0x02
R/W
0x01
R/W
0x2B
R/W
0x00
R/W
0x30
R/W
0x0F
R/W
0x00
R/W
A6
R/W
00
R/W
0xA0
R/W
AD9144
Reg.
Name
0x112
INTERP_MODE
0x113
NCO_FTW_
UPDATE
Data Sheet
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RESERVED
Bit 1
Bit 0
INTERP_MODE
RESERVED
FTW_UPDATE_ FTW_
ACK
UPDATE_
REQ
Reset
R/W
0x01
R/W
0x00
R/W
0x114
FTW0
FTW[7:0]
0x00
R/W
0x115
FTW1
FTW[15:8]
0x00
R/W
0x116
FTW2
FTW[23:16]
0x00
R/W
0x117
FTW3
FTW[31:24]
0x00
R/W
0x118
FTW4
FTW[39:32]
0x00
R/W
0x119
FTW5
FTW[47:40]
0x10
R/W
0x11A
NCO_PHASE_
OFFSET0
NCO_PHASE_OFFSET[7:0]
0x00
R/W
0x11B
NCO_PHASE_
OFFSET1
NCO_PHASE_OFFSET[15:8]
0x00
R/W
0x11C
PHASE_ADJ0
PHASE_ADJ[7:0]
0x00
R/W
0x11D
PHASE_ADJ1
0x11F
TXEN_SM_0
0x121
TXEN_RISE_
COUNT_0
0x122
RESERVED
0x00
R/W
0x83
R/W
RISE_COUNT_0
0x0F
R/W
TXEN_RISE_
COUNT_1
RISE_COUNT_1
0x00
R/W
0x123
TXEN_FALL_
COUNT_0
FALL_COUNT_0
0xFF
R/W
0x124
TXEN_FALL_
COUNT_1
FALL_COUNT_1
0xFF
R/W
0x12D
DEVICE_CONFIG_
REG_0
DEVICE_CONFIG_0
0x46
R/W
0x12F
DIE_TEMP_CTRL0
0x20
R/W
0x132
DIE_TEMP0
0x00
FALL_COUNTERS
PHASE_ADJ[12:8]
RISE_COUNTERS
RESERVED
PROTECT_OUT_
INVERT
RESERVED
RESERVED
AUXADC_
ENABLE
DIE_TEMP[7:0]
0x133
DIE_TEMP1
0x134
DIE_TEMP_
UPDATE
RESERVED
DIE_TEMP[15:8]
DIE_TEMP_
UPDATE
0x00
0x00
R/W
0x135
DC_OFFSET_CTRL
RESERVED
DC_OFFSET_ 0x00
ON
R/W
0x136
IPATH_DC_
OFFSET_1PART0
LSB_OFFSET_I[7:0]
0x00
R/W
0x137
IPATH_DC_
OFFSET_1PART1
LSB_OFFSET_I[15:8]
0x00
R/W
0x138
QPATH_DC_
OFFSET_1PART0
LSB_OFFSET_Q[7:0]
0x00
R/W
0x139
QPATH_DC_
OFFSET_1PART1
LSB_OFFSET_Q[15:8]
0x00
R/W
0x13A
IPATH_DC_
OFFSET_2PART
RESERVED
SIXTEENTH_OFFSET_I
0x00
R/W
0x13B
QPATH_DC_
OFFSET_2PART
RESERVED
SIXTEENTH_OFFSET_Q
0x00
R/W
0x13C
IDAC_DIG_GAIN0
0x13D
IDAC_DIG_GAIN1
0x13E
QDAC_DIG_
GAIN0
0x13F
QDAC_DIG_GAIN1
0x140
GAIN_RAMP_UP_
STEP0
IDAC_DIG_GAIN[7:0]
RESERVED
IDAC_DIG_GAIN[11:8]
QDAC_DIG_GAIN[7:0]
RESERVED
QDAC_DIG_GAIN[11:8]
GAIN_RAMP_UP_STEP[7:0]
0xEA
R/W
0x0A
R/W
0xEA
R/W
0x0A
R/W
0x04
R/W
Data Sheet
Reg.
Name
0x141
GAIN_RAMP_
UP_STEP1
0x142
GAIN_RAMP_
DOWN_STEP0
0x143
GAIN_RAMP_
DOWN_STEP1
0x146
DEVICE_CONFIG_
REG_1
AD9144
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RESERVED
Bit 1
Bit 0
GAIN_RAMP_UP_STEP[11:8]
GAIN_RAMP_DOWN_STEP[7:0]
RESERVED
GAIN_RAMP_DOWN_STEP[11:8]
DEVICE_CONFIG_1
0x09
R/W
0x00
R/W
0x00
R/W
0x00
0x10
R/W
BSM_STAT
0x14B
PRBS
0x14C
PRBS_ERROR_I
PRBS_COUNT_I
0x00
0x14D
PRBS_ERROR_Q
PRBS_COUNT_Q
0x00
DACPLLT0
0x1B5
DACPLLT5
0x1B9
DACPLLT9
PRBS_
GOOD_Q
RESERVED
R/W
R/W
0x147
0x1B0
SOFTBLANKRB
Reset
0x00
RESERVED
PRBS_
GOOD_I
PRBS_MODE
PRBS_RESET
PRBS_EN
DAC_PLL_PWR
RESERVED
VCO_VAR
DAC_PLL_CP1
RESERVED
VCO_BIAS_TCF
VCO_BIAS_REF
0xFA
R/W
0x83
R/W
0x34
R/W
0x1BB
DACPLLTB
0x0C
R/W
0x1BC
DACPLLTC
DAC_PLL_VCO_CTRL
0x00
R/W
0x1BE
DACPLLTE
DAC_PLL_VCO_PWR
0x00
R/W
0x1BF
DACPLLTF
DAC_PLL_VCOCAL
0x8D
R/W
0x1C0
DACPLLT10
DAC_PLL_LOCK_CNTR
0x2E
R/W
0x1C1
DACPLLT11
DAC_PLL_CP2
0x24
R/W
0x1C4
DACPLLT17
DAC_PLL_VAR1
0x33
R/W
0x1C5
DACPLLT18
DAC_PLL_VAR2
0x08
R/W
0x200
MASTER_PD
0x01
R/W
0x201
PHY_PD
0x203
GENERIC_PD
0x206
CDR_RESET
0x230
CDR_OPERATING_
MODE_REG_0
0x232
DEVICE_CONFIG_
REG_3
0x268
EQ_BIAS_REG
0x280
SERDESPLL_
ENABLE_CNTRL
0x281
PLL_STATUS
0x284
LOOP_FILTER_1
LOOP_FILTER_1
0x77
R/W
0x285
LOOP_FILTER_2
LOOP_FILTER_2
0x87
R/W
0x286
LOOP_FILTER_3
LOOP_FILTER_3
0x08
R/W
0x287
SERDES_PLL_CP1
SERDES_PLL_CP1
0x3F
R/W
0x289
REF_CLK_
DIVIDER_LDO
0x00
R/W
0x28A
VCO_LDO
SERDES_PLL_VCO_LDO
0x2B
R/W
0x28B
SERDES_PLL_PD1
SERDES_PLL_PD1
0x7F
R/W
0x290
SERDESPLL_VAR1
SERDES_PLL_VAR1
0x83
R/W
0x294
SERDES_PLL_CP2
SERDES_PLL_CP2
0xB0
R/W
0x296
SERDESPLL_VCO1
SERDES_PLL_VCO1
0x0C
R/W
0x297
SERDESPLL_VCO2
SERDES_PLL_VCO2
0x00
R/W
RESERVED
SPI_PD_
MASTER
SPI_PD_PHY
RESERVED
SPI_
SYNC1_PD
RESERVED
RESERVED
ENHALFRATE
RESERVED
CDR_
OVERSAMP
0x00
R/W
SPI_
SYNC2_PD
0x00
R/W
SPI_CDR_
RESETN
0x01
R/W
RESERVED
0x28
R/W
0x0
R/W
0x62
R/W
0x00
R/W
DEVICE_CONFIG_3
EQ_POWER_MODE
RESERVED
RESERVED
RESERVED
RECAL_
SERDESPLL
SERDES_PLL_ SERDES_PLL_
OVERRANGE_ OVERRANGE_L
H
RESERVED
SERDES_PLL_CAL_
VALID_RB
RESERVED
DEVICE_
CONFIG_4
RESERVED
ENABLE_
SERDESPLL
SERDES_PLL_ 0x00
LOCK_RB
SERDES_PLL_DIV_MODE
AD9144
Data Sheet
Reg.
Name
Reset
R/W
0x299
SERDES_PLL_PD2
Bit 7
Bit 6
Bit 5
Bit 4
SERDES_PLL_PD2
Bit 3
Bit 2
Bit 1
Bit 0
0x00
R/W
0x29A
SERDESPLL_VAR2
SERDES_PLL_VAR2
0xFE
R/W
R/W
0x29C
SERDES_PLL_CP3
SERDES_PLL_CP3
0x17
0x29F
SERDESPLL_VAR3
SERDES_PLL_VAR3
0x33
R/W
0x2A0
SERDESPLL_VAR4
SERDES_PLL_VAR4
0x08
R/W
0x2A4
DEVICE_CONFIG_
REG_8
DEVICE_CONFIG_8
0x4B
R/W
0x2A5
SYNCOUTB_
SWING
RESERVED
SYNCOUTB_
SWING_MD
0x00
R/W
0x2A7
TERM_BLK1_
CTRLREG0
RESERVED
RCAL_
TERMBLK1
0x00
R/W
0x2AA DEVICE_CONFIG_
REG_9
DEVICE_CONFIG_9
0xC3
R/W
0x2AB
DEVICE_CONFIG_
REG_10
DEVICE_CONFIG_10
0x93
R/W
0x2AE
TERM_BLK2_
CTRLREG0
0x00
R/W
0x2B1
DEVICE_CONFIG_
REG_11
DEVICE_CONFIG_11
0xC3
R/W
0x2B2
DEVICE_CONFIG_
REG_12
DEVICE_CONFIG_12
0x93
R/W
0x300
GENERAL_JRX_
CTRL_0
0x00
R/W
0x301
GENERAL_JRX_
CTRL_1
0x01
R/W
0x302
DYN_LINK_
LATENCY_0
RESERVED
DYN_LINK_LATENCY_0
0x00
0x303
DYN_LINK_
LATENCY_1
RESERVED
DYN_LINK_LATENCY_1
0x00
0x304
LMFC_DELAY_0
RESERVED
LMFC_DELAY_0
0x00
R/W
0x305
LMFC_DELAY_1
RESERVED
LMFC_DELAY_1
0x00
R/W
0x306
LMFC_VAR_0
RESERVED
LMFC_VAR_0
0x06
R/W
RESERVED
RESERVED CHECKSUM
_MODE
RESERVED
RCAL_
TERMBLK2
LINK_MODE
LINK_PAGE
RESERVED
SUBCLASSV_LOCAL
0x307
LMFC_VAR_1
0x308
XBAR_LN_0_1
RESERVED
RESERVED
0x309
XBAR_LN_2_3
RESERVED
0x30A
XBAR_LN_4_5
RESERVED
0x30B
XBAR_LN_6_7
RESERVED
LOGICAL_LANE7_SRC
0x30C
FIFO_STATUS_
REG_0
0x30D
FIFO_STATUS_
REG_1
RESERVED
LINK_EN
LMFC_VAR_1
0x06
R/W
LOGICAL_LANE0_SRC
0x08
R/W
LOGICAL_LANE3_SRC
LOGICAL_LANE2_SRC
0x1A
R/W
LOGICAL_LANE5_SRC
LOGICAL_LANE4_SRC
0x2C
R/W
LOGICAL_LANE6_SRC
0x3E
R/W
LANE_FIFO_FULL
0x00
LANE_FIFO_EMPTY
0x00
LOGICAL_LANE1_SRC
0x312
SYNCB_GEN_1
0x00
R/W
0x314
SERDES_SPI_REG
SYNCB_ERR_DUR
SERDES_SPI_CONFIG
0x00
R/W
0x315
PHY_PRBS_TEST_
EN
PHY_TEST_EN
0x00
R/W
0x316
PHY_PRBS_TEST_ RESERVED
CTRL
0x00
R/W
0x317
PHY_PRBS_TEST_
THRESHOLD_
LOBITS
PHY_PRBS_THRESHOLD[7:0]
0x00
R/W
0x318
PHY_PRBS_TEST_
THRESHOLD_
MIDBITS
PHY_PRBS_THRESHOLD[15:8]
0x00
R/W
0x319
PHY_PRBS_TEST_
THRESHOLD_
HIBITS
PHY_PRBS_THRESHOLD[23:16]
0x00
R/W
PHY_SRC_ERR_CNT
RESERVED
PHY_PRBS_PAT_SEL
PHY_TEST_
START
PHY_TEST_
RESET
Data Sheet
AD9144
Reg.
Name
Reset
R/W
0x31A
PHY_PRBS_TEST_
ERRCNT_LOBITS
Bit 7
Bit 6
Bit 5
PHY_PRBS_ERR_CNT[7:0]
0x00
0x31B
PHY_PRBS_TEST_
ERRCNT_MIDBITS
PHY_PRBS_ERR_CNT[15:8]
0x00
0x31C
PHY_PRBS_TEST_
ERRCNT_HIBITS
PHY_PRBS_ERR_CNT[23:16]
0x00
0x31D
PHY_PRBS_TEST_
STATUS
PHY_PRBS_PASS
0xFF
0x32C
SHORT_TPL_
TEST_0
0x32D
SHORT_TPL_
TEST_1
0x32E
Bit 3
Bit 1
SHORT_TPL_REF_SP_LSB
0x00
R/W
SHORT_TPL_
TEST_2
SHORT_TPL_REF_SP_MSB
0x00
R/W
0x32F
SHORT_TPL_
TEST_3
RESERVED
0x00
0x333
DEVICE_CONFIG_
REG_13
DEVICE_CONFIG_13
0x00
R/W
0x334
JESD_BIT_
INVERSE_CTRL
JESD_BIT_INVERSE
0x00
R/W
0x400
DID_REG
0x401
BID_REG
0x402
LID0_REG
0x403
SCR_L_REG
SCR_RD
0x404
F_REG
K_REG
M_REG
0x407
CS_N_REG
0x408
NP_REG
0x409
S_REG
SHORT_TPL_DAC_SEL
Bit 0
R/W
0x406
SHORT_TPL_SP_SEL
Bit 2
SHORT_TPL_ 0x00
TEST_EN
0x405
RESERVED
Bit 4
SHORT_TPL_
TEST_RESET
SHORT_
TPL_FAIL
DID_RD
0x00
0x00
LID0_RD
0x00
L-1_RD
0x00
0x00
ADJCNT_RD
BID_RD
RESERVED
F-1_RD
RESERVED
K-1_RD
0x00
0x00
N-1_RD
0x00
SUBCLASSV_RD
NP-1_RD
0x00
JESDV_RD
S-1_RD
0x00
CF_RD
M-1_RD
CS_RD
HD_RD
RESERVED
0x40A
HD_CF_REG
0x00
0x40B
RES1_REG
RESERVED
RES1_RD
0x00
0x40C
RES2_REG
RES2_RD
0x00
R
R
0x40D
CHECKSUM_REG
FCHK0_RD
0x00
0x40E
COMPSUM0_REG
FCMP0_RD
0x00
0x412
LID1_REG
0x00
0x415
CHECKSUM1_REG
FCHK1_RD
0x00
0x416
COMPSUM1_REG
FCMP1_RD
0x00
0x41A
LID2_REG
0x00
0x41D
CHECKSUM2_REG
FCHK2_RD
0x00
0x41E
COMPSUM2_REG
FCMP2_RD
0x00
0x422
LID3_REG
0x00
0x425
CHECKSUM3_REG
FCHK3_RD
0x00
0x426
COMPSUM3_REG
FCMP3_RD
0x00
0x42A
LID4_REG
0x00
0x42D
CHECKSUM4_REG
0x00
0x42E
COMPSUM4_REG
0x432
LID5_REG
0x435
CHECKSUM5_REG
0x436
COMPSUM5_REG
0x43A
LID6_REG
0x43D
CHECKSUM6_REG
RESERVED
LID1_RD
RESERVED
LID2_RD
RESERVED
LID3_RD
RESERVED
LID4_RD
FCHK4_RD
FCMP4_RD
RESERVED
LID5_RD
FCHK5_RD
FCMP5_RD
RESERVED
LID6_RD
FCHK6_RD
Rev. A | Page 91 of 125
0x00
0x00
0x00
0x00
0x00
0x00
AD9144
Data Sheet
Reg.
Name
0x43E
COMPSUM6_REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x442
LID7_REG
0x445
CHECKSUM7_REG
0x446
COMPSUM7_REG
0x450
ILS_DID
DID
Bit 2
Bit 1
Bit 0
Reset
R/W
0x00
0x00
FCHK7_RD
0x00
FCMP7_RD
0x00
0x00
R/W
0x00
R/W
0x00
R/W
FCMP6_RD
RESERVED
0x451
ILS_BID
0x452
ILS_LID0
RESERVED ADJDIR
0x453
ILS_SCR_L
SCR
0x454
ILS_F
0x455
ILS_K
0x456
ILS_M
0x457
ILS_CS_N
0x458
ILS_NP
0x459
ILS_S
0x45A
ILS_HD_CF
LID7_RD
ADJCNT
BID
PHADJ
LID0
RESERVED
L-1
F-1
RESERVED
K-1
M-1
CS
RESERVED
0x83
R/W
0x00
R/W
0x1F
R/W
0x01
R/W
N-1
0x0F
R/W
SUBCLASSV
NP-1
0x2F
R/W
JESDV
S-1
0x20
R/W
CF
0x80
R/W
HD
RESERVED
0x45B
ILS_RES1
RES1
0x00
R/W
0x45C
ILS_RES2
RES2
0x00
R/W
0x45D
ILS_CHECKSUM
FCHK0
0x45
R/W
0x46B
ERRCNTRMON_RB
0x00
0x46B
ERRCNTRMON
0x46C
LANEDESKEW
0x46D
BADDISPARITY_RB
0x46D
BADDISPARITY
0x46E
NIT_RB
0x46E
NIT_W
0x46F
UNEXPECTEDCONTROL_RB
0x46F
UNEXPECTEDCONTROL_W
READERRORCNTR
RESERVED
LANESEL
RESERVED
CNTRSEL
LANEDESKEW
BADDIS
RST_IRQ_ DISABLE_ RST_ERR_
DIS
ERR_CNTR_ CNTR_DIS
DIS
RESERVED
RESERVED
LANE_ADDR_DIS
NIT
LANE_ADDR_NIT
UCC
RESERVED
LANE_ADDR_UCC
0x00
R/W
0x0F
R/W
0x00
0x00
R/W
0x00
0x00
R/W
0x00
0x00
R/W
0x470
CODEGRPSYNCFLG
0x471
FRAMESYNCFLG
CODEGRPSYNC
0x00
R/W
FRAMESYNC
0x00
R/W
0x472
0x473
GOODCHKSUMFLG
GOODCHECKSUM
0x00
R/W
INITLANESYNCFLG
INITIALLANESYNC
0x00
0x476
CTRLREG1
R/W
0x01
R/W
0x477
CTRLREG2
0x00
R/W
0x478
KVAL
0x01
R/W
0x47A
IRQVECTOR_MASK BADDIS_
MASK
NIT_MASK
UCC_
MASK
RESERVED
INITIALLANESYNC_
MASK
BADCHECK
SUM_MASK
0x00
CODEGRP
SYNC_MASK
R/W
0x47A
IRQVECTOR_FLAG BADDIS_
FLAG
NIT_FLAG
UCC_FLAG
RESERVED
INITIALLANESYNC_
FLAG
BADCHECKSUM FRAMESYNC_
_FLAG
FLAG
0x47B
SYNCASSERTIONMASK
UCC_S
CMM
CMM_ENABLE
RESERVED
0x47C
ERRORTHRES
ETH
0xFF
R/W
0x47D
LANEENABLE
LANE_ENA
0x0F
R/W
0x47E
RAMP_ENA
ENA_RAMP_ 0x00
CHECK
R/W
RESERVED
ILAS_
MODE
RESERVED
THRESHOLD_
MASK_EN
KSYNC
BADDIS_S NIT_S
RESERVED
FRAMESYNC_
MASK
CODEGRP
SYNC_FLAG
0x00
0x008
R/W
Data Sheet
AD9144
Reg.
Name
0x520
DIG_TEST0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x521
DC_TEST_VALUEI0
DC_TEST_VALUEI[7:0]
0x522
DC_TEST_VALUEI1
DC_TEST_VALUEI[15:8]
0x00
R/W
0x523
DC_TEST_
VALUEQ0
DC_TEST_VALUEQ[7:0]
0x00
R/W
0x524
DC_TEST_
VALUEQ1
DC_TEST_VALUEQ[15:8]
0x00
R/W
RESERVED
Bit 2
Bit 1
Bit 0
Reset
R/W
DC_TEST_
MODE
RESERVED
0x1C
R/W
0x00
R/W
AD9144
Data Sheet
Name
SPI_INTFCONFA
Bit No.
7
6
5
4
3
2
Bit Name
SOFTRESET_M
LSBFIRST_M
ADDRINC_M
SDOACTIVE_M
SDOACTIVE
ADDRINC
Settings
1
0
1
LSBFIRST
1
0
SOFTRESET
1
0x003
CHIPTYPE
[7:0]
CHIPTYPE
0x004
0x005
0x006
PRODIDL
PRODIDH
CHIPGRADE
0x008
SPI_PAGEINDX
[7:0]
[7:0]
[7:4]
[3:0]
[7:2]
[1:0]
PRODIDL
PRODIDH
PROD_GRADE
DEV_REVISION
RESERVED
DUAL_PAGE
0b01
0b10
0b11
0x00A
SCRATCH_PAD
[7:0]
SCRATCHPAD
0x011
PWRCNTRL0
PD_BG
PD_DAC_0
PD_DAC_1
Description
Soft Reset (Mirror).
LSB First (Mirror).
Address Increment (Mirror).
SDO Active (Mirror).
SDO Active.
Address Increment. Controls whether
addresses are incremented or decremented
during multibyte data transfers.
Addresses are incremented during multibyte
data transfers
Addresses are decremented during
multibyte data transfers
LSB First. Controls whether input and output
data are oriented as LSB first or MSB first.
Shift LSB in first
Shift MSB in first
Soft Reset. Setting this bit initiates a reset.
This bit is autoclearing after the soft reset is
complete.
Assert soft reset
The product type is High Speed DAC, which
is represented by a code of 0x04.
Product Identification Low.
Product Identification High.
Product Grade.
Device Revision.
Reserved.
Dual Paging. Selects which dual DAC pair is
accessed and written to when changing
digital features, such as digital gain, dc offset,
NCO FTW, and others. This paging affects
Register 0x013 to Register 0x014,
Register 0x034 to Register 0x03d,
Register 0x050 to Register 0x064,
Register 0x110 to Register 0x124, and
Register 0x135 to Register 0x14D.
Read and write Dual A
Read and write Dual B
Write both duals; read Dual A
This register does not affect any functions in
the device and can be used for testing SPI
communication with the part. Any value
written to this register will be read back to
reflect the change unless a reset or powercycle occurs.
Reference Power-Down. Powers down the
band gap reference for the entire chip.
Circuits will not be provided with bias
currents.
Power down reference
Powers Down DAC0. Powers down the Ichannel DAC of Dual A.
Powers down DAC0
Powers Down DAC1. Powers down the Qchannel DAC of Dual A.
Powers down DAC 1
Reset
0x0
0x0
0x0
0x0
0x0
0x0
Access
R
R
R
R
R/W
R/W
0x0
R/W
0x0
R/W
0x4
0x44
0x91
0x0
0x6
0x0
0x3
R
R
R
R
R
R/W
0x00
R/W
0x0
R/W
0x1
R/W
0x1
R/W
Data Sheet
Address
Name
AD9144
Bit No.
4
Bit Name
PD_DAC_2
Settings
PD_DAC_3
PD_DACM
[1:0]
[7:2]
1
RESERVED
RESERVED
DUALB_MASK
DUALA_MASK
7
6
RESERVED
PDP_PROTECT_
OUT
5
4
3
TX_PROTECT_OUT
RESERVED
SPI_PROTECT_
OUT
SPI_PROTECT
RESERVED
RESERVED
GROUP_DLY
1
0x012
TXENMASK
1
0x013
PWRCNTRL3
0x014
GROUP_DLY
0x01F
IRQEN_
STATUSMODE0
2
[1:0]
[7:4]
[3:0]
IRQEN_SMODE_
CALPASS
1
1
1
1
0
IRQEN_SMODE_
CALFAIL
1
0
IRQEN_SMODE_
DACPLLLOST
1
0
IRQEN_SMODE_
DACPLLLOCK
1
0
IRQEN_SMODE_
SERPLLLOST
1
0
Description
Powers Down DAC2. Powers down the Ichannel DAC of Dual B.
Powers down DAC 2
Powers Down DAC3. Powers down the Qchannel DAC of Dual B.
Powers down DAC 3
Powers Down the DAC Master Bias. The
master bias cell provides currents and DAC
full-scale adjustments to the four DACs. With
the DAC master bias powered down, the
DACs are inoperative.
Powers down the DAC master bias
Reserved.
Reserved.
Dual B TXEN1 Mask. Power down Dual B on a
falling edge of TXEN1.
If TXEN1 is low, power down DAC2 and DAC3
Dual A TXEN0 Mask. Power down Dual A on a
falling edge of TXEN0.
If TXEN0 is low, power down DAC0 and DAC1
Reserved.
PDP_PROTECT triggers PROTECT_OUTx.
Reset
0x1
Access
R/W
0x1
R/W
0x1
R/W
0x0
0x0
0x0
R
R
R/W
0x0
R/W
0x0
0x0
R
R/W
0x1
0x0
0x0
R/W
R
R/W
SPI_PROTECT
Reserved.
Reserved.
Group Delay Control. Delays the I and Q
channel outputs together. 0 = minimum
delay. 15 = maximum delay. The range of the
delay is 4 to +3.5 DAC clock periods, and
the resolution is 1/2 DAC clock period.
Calibration Pass Detection Status Mode.
If CALPASS goes high, it latches and pulls IRQ
low
CALPASS shows current status
Calibration Fail Detection Status Mode.
If CALFAIL goes high, it latches and pulls IRQ
low
CALFAIL shows current status
DAC PLL Lost Detection Status Mode.
If DACPLLLOST goes high, it latches and pulls
IRQ low
DACPLLLOST shows current status
DAC PLL Lock Detection Status Mode.
If DACPLLLOCK goes high, it latches and
pulls IRQ low
DACPLLLOCK shows current status
SERDES PLL Lost Detection Status Mode.
If SERPLLLOST goes high, it latches and pulls
IRQ low
SERPLLLOST shows current status
0x0
0x0
0x8
0x8
R/W
R
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
AD9144
Address
Name
Data Sheet
Bit No.
2
Bit Name
IRQEN_SMODE_
SERPLLLOCK
Settings
1
0
IRQEN_SMODE_
LANEFIFOERR
1
0
0x020
IRQEN_
STATUSMODE1
0
[7:4]
RESERVED
RESERVED
IRQEN_SMODE_
PRBS3
1
0
IRQEN_SMODE_
PRBS2
1
0
IRQEN_SMODE_
PRBS1
1
0
IRQEN_SMODE_
PRBS0
1
0
0x021
IRQEN_
STATUSMODE2
IRQEN_SMODE_
PDPERR0
1
0
6
5
RESERVED
IRQEN_SMODE_
BLNKDONE0
1
0
IRQEN_SMODE_
NCO_ALIGN0
1
0
IRQEN_SMODE_
SYNC_LOCK0
1
0
IRQEN_SMODE_
SYNC_ROTATE0
1
0
IRQEN_SMODE_
SYNC_WLIM0
1
0
IRQEN_SMODE_
SYNC_TRIP0
1
0
Description
SERDES PLL Lock Detection Status Mode.
If SERPLLLOCK goes high, it latches and pulls
IRQ low
SERPLLLOCK shows current status
Lane FIFO Error Detection Status Mode.
If LANEFIFOERR goes high, latches and pulls
IRQ low
LANEFIFOERR shows current status
Reserved.
Reserved.
DAC3 PRBS Error Status Mode.
If PRBS3 goes high, it latches and pulls IRQ
low
PRBS3 shows current status
DAC2 PRBS Error Status Mode.
If PRBS2 goes high, it latches and pulls IRQ
low
PRBS2 shows current status
DAC1 PRBS Error Status Mode.
If PRBS1 goes high, it latches and pulls IRQ
low
PRBS1 shows current status
DAC0 PRBS Error Status Mode.
If PRBS0 goes high, it latches and pulls IRQ
low
PRBS0 shows current status
Dual A PDP Error.
If PDPERR0 goes high, it latches and pulls IRQ
low
PDPERR0 shows current status
Reserved.
Dual A Blanking Done Status Mode.
If BLNKDONE0 goes high, it latches and pulls
IRQ low
BLNKDONE0 shows current status
Dual A NCO Align Tripped Status Mode
If NCO_ALIGN0 goes high, it latches and pulls
IRQ low
NCO_ALIGN0 shows current status
Dual A Alignment Locked Status Mode.
If SYNC_LOCK0 goes high, it latches and pulls
IRQ low
SYNC_LOCK0 shows current status
Dual A Alignment Rotate Status Mode.
If SYNC_ROTATE0 goes high, it latches and
pulls IRQ low
SYNC_ROTATE0 shows current status
Dual A Outside Window Status Mode.
If SYNC_WLIM0 goes high, it latches and
pulls IRQ low
SYNC_WLIM0 shows current status
Dual A Alignment Tripped Status Mode.
If SYNC_TRIP0 goes high, it latches and pulls
IRQ low
SYNC_TRIP0 shows current status
Reset
0x0
Access
R/W
0x0
R/W
0x0
0x0
R
R
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Data Sheet
Address
0x022
Name
IRQEN_
STATUSMODE3
AD9144
Bit No.
7
Bit Name
IRQEN_SMODE_
PDPERR1
Settings
1
0
6
5
RESERVED
IRQEN_SMODE_
BLNKDONE1
1
0
IRQEN_SMODE_
NCO_ALIGN1
1
0
IRQEN_SMODE_
SYNC_LOCK1
1
0
IRQEN_SMODE_
SYNC_ROTATE1
1
0
IRQEN_SMODE_
SYNC_WLIM1
1
0
IRQEN_SMODE_
SYNC_TRIP1
1
0
0x023
IRQ_STATUS0
CALPASS
CALFAIL
DACPLLLOST
DACPLLLOCK
SERPLLLOST
Description
Dual B PDP Error.
If PDPERR1 goes high, it latches and pulls IRQ
low
PDPERR1 shows current status
Reserved.
Dual B Blanking Done Status Mode.
If BLNKDONE1 goes high, it latches and pulls
IRQ low
BLNKDONE1 shows current status
Dual B NCO Align Tripped Status Mode
If NCO_ALIGN1 goes high, it latches and pulls
IRQ low
NCO_ALIGN1 shows current status
Dual B Alignment Locked Status Mode.
If SYNC_LOCK1 goes high, it latches and pulls
IRQ low
SYNC_LOCK1 shows current status
Dual B Alignment Rotate Status Mode.
If SYNC_ROTATE1 goes high, it latches and
pulls IRQ low
SYNC_ROTATE1 shows current status
Dual B Outside Window Status Mode.
If SYNC_WLIM1 goes high, it latches and
pulls IRQ low
SYNC_WLIM1 shows current status
Dual B Alignment Tripped Status Mode.
If SYNC_TRIP1 goes high, it latches and pulls
IRQ low
SYNC_TRIP1 shows current status
Calibration Pass Status. If
IRQEN_SMODE_CALPASS is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
Calibration passed
Calibration Fail Detection Status. If
IRQEN_SMODE_CALFAIL is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
Calibration failed
DAC PLL Lost Status. If
IRQEN_SMODE_DACPLLLOST is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
DAC PLL lock was lost
DAC PLL Lock Status. If
IRQEN_SMODE_DACPLLLOCK is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
DAC PLL locked
SERDES PLL Lost Status. If
IRQEN_SMODE_SERPLLLOST is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
SERDES PLL lock was lost
Reset
0x0
Access
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
0x0
0x0
0x0
AD9144
Address
Name
Data Sheet
Bit No.
2
Bit Name
SERPLLLOCK
LANEFIFOERR
0
[7:4]
3
RESERVED
RESERVED
PRBS3
PRBS2
PRBS1
PRBS0
PDPERR0
6
5
RESERVED
BLNKDONE0
NCO_ALIGN0
Settings
1
0x024
IRQ_STATUS1
1
0x025
IRQ_STATUS2
Description
SERDES PLL Lock Status. If
IRQEN_SMODE_SERPLLLOCK is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
SERDES PLL locked
Lane FIFO Error Status. If
IRQEN_SMODE_LANEFIFOERR is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low.
A lane FIFO error occurs when there is a full
or empty condition on any of the FIFOs
between the deserializer block and the core
digital. This error requires a link disable and
reenable to remove it. The status of the lane
FIFOs can be found in Register 0x30C (FIFO
full), and Register 0x30D (FIFO empty).
Lane FIFO error
Reserved.
Reserved.
DAC3 PRBS Error Status. If
IRQEN_SMODE_PRBS3 is low, this bit shows
current status. If not, this bit latches on a
rising edge and pull IRQ low. When latched,
write a 1 to clear this bit.
DAC3 failed PRBS
DAC2 PRBS Error Status. If
IRQEN_SMODE_PRBS2 is low, this bit shows
current status. If not, this bit latches on a
rising edge and pull IRQ low. When latched,
write a 1 to clear this bit.
DAC2 failed PRBS
DAC1 PRBS Error Status. If
IRQEN_SMODE_PRBS1 is low, this bit shows
current status. If not, this bit latches on a
rising edge and pull IRQ low. When latched,
write a 1 to clear this bit.
DAC1 failed PRBS
DAC0 PRBS Error Status. If
IRQEN_SMODE_PRBS0 is low, this bit shows
current status. If not, this bit latches on a
rising edge and pull IRQ low. When latched,
write a 1 to clear this bit.
DAC0 failed PRBS
Dual A PDP Error. If IRQEN_SMODE_PAERR0
is low, this bit shows current status. If not,
this bit latches on a rising edge and pull IRQ
low. When latched, write a 1 to clear this bit.
Data into Dual A over power threshold
Reserved.
Dual A Blanking Done Status. If
IRQEN_SMODE_BLNKDONE0 is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
Dual A blanking done
Dual A NCO Align Tripped Status. If
IRQEN_SMODE_NCO_ALIGN0 is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
Dual A NCO align tripped
Reset
0x0
Access
R
0x0
0x0
0x0
0x0
R
R
R
0x0
0x0
0x0
0x0
0x0
0x0
R
R
0x0
Data Sheet
Address
Name
AD9144
Bit No.
3
Bit Name
SYNC_LOCK0
SYNC_ROTATE0
SYNC_WLIM0
SYNC_TRIP0
PDPERR1
6
5
RESERVED
BLNKDONE1
NCO_ALIGN1
SYNC_LOCK1
Settings
1
0x026
IRQ_STATUS3
1
2
SYNC_ROTATE1
SYNC_WLIM1
Description
Dual A LMFC Alignment Locked Status. If
IRQEN_SMODE_SYNC_LOCK0 is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
Dual A LMFC alignment locked
Dual A LMFC Alignment Rotate Status. If
IRQEN_SMODE_SYNC_ROTATE0 is low, this
bit shows current status. If not, this bit
latches on a rising edge and pull IRQ low.
When latched, write a 1 to clear this bit.
Dual A LMFC alignment rotated
Dual A Outside Window Status. If
IRQEN_SMODE_SYNC_WLIM0 is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
Dual A LMFC phase outside of window
Dual A LMFC Alignment Tripped Status. If
IRQEN_SMODE_SYNC_TRIP0 is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
Dual A LMFC alignment tripped
Dual B PDP Error. If IRQ_SMODE_PDPERR1 is
low, this bit shows current status. If not, this
bit latches on a rising edge and pull IRQ low.
When latched, write a 1 to clear this bit.
Data into Dual B over power threshold
Reserved.
Dual B Blanking Done Status. If
IRQEN_SMODE_BLNKDONE1 is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
Dual B blanking done
Dual B NCO Align Tripped Status. If
IRQEN_SMODE_NCO_ALIGN1 is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
Dual B NCO align tripped
Dual B LMFC Alignment Locked Status. If
IRQEN_SMODE_SYNC_LOCK1 is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
Dual B LMFC alignment locked
Dual B LMFC Alignment Rotate Status. If
IRQEN_SMODE_SYNC_ROTATE1 is low, this
bit shows current status. If not, this bit
latches on a rising edge and pull IRQ low.
When latched, write a 1 to clear this bit.
Dual B LMFC alignment rotated
Dual B Outside Window Status. If
IRQEN_SMODE_SYNC_WLIM1 is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
Dual B LMFC phase outside of window
Reset
0x0
Access
R
0x0
0x0
0x0
0x0
0x0
0x0
R
R
0x0
0x0
0x0
0x0
AD9144
Data Sheet
Address
Name
Bit No.
0
Bit Name
SYNC_TRIP1
0x030
JESD_CHECKS
[7:6]
5
RESERVED
ERR_DLYOVER
ERR_WINLIMIT
Settings
1
1
3
ERR_JESDBAD
1
ERR_KUNSUPP
ERR_SUBCLASS
ERR_INTSUPP
1
0x034
SYNC_ERRWINDOW
[7:2]
[1:0]
RESERVED
ERRWINDOW
0x038
SYNC_LASTERR_L
[7:4]
[3:0]
RESERVED
LASTERROR
0x039
SYNC_LASTERR_H
LASTUNDER
1
LASTOVER
1
0x03A
SYNC_CONTROL
[5:0]
7
RESERVED
SYNCENABLE
1
0
SYNCARM
1
SYNCCLRSTKY
SYNCCLRLAST
[3:0]
SYNCMODE
0b0001
0b0010
0b1000
0b1001
Description
Dual B LMFC Alignment Tripped Status. If
IRQEN_SMODE_SYNC_TRIP1 is low, this bit
shows current status. If not, this bit latches
on a rising edge and pull IRQ low. When
latched, write a 1 to clear this bit.
Dual B LMFC alignment tripped
Reserved.
Error: LMFC_Delay > JESD_K Parameter.
LMFC_Delay > JESD_K
Unsupported Window Limit.
Unsupported SYSREF window limit
Unsupported M/L/S/F Selection.
This JESD combination is not supported
Unsupported K Values. 16 and 32 are
supported.
K value unsupported
Unsupported Subclass Value. 0 and 1 are
supported.
Unsupported subclass value
Unsupported Interpolation Rate Factor. 1, 2,
4, 8 are supported.
Unsupported interpolation rate factor
Reserved.
LMFC Sync Error Window. The error window
allows the SYSREF sample phase to vary
within the confines of the window without
triggering a clock adjustment. This is useful if
SYSREF cannot be guaranteed to always
arrive in the same period of the device clock
associated with the target phase.
Error window tolerance = ERRWINDOW
Reserved.
LMFC Sync Last Alignment Error. 4-bit twos
complement value that represents the phase
error (in number of DAC clock cycles) when the
clocks were last adjusted.
LMFC Sync Last Error Under Flag.
Last phase error was beyond lower window
tolerance boundary
LMFC Sync Last Error Over Flag.
Last phase error was beyond upper window
tolerance boundary
Reserved.
LMFC Sync Logic Enable.
Enable sync logic
Disable sync logic
LMFC Sync Arming Strobe.
Sync one-shot armed
LMFC Sync Sticky Bit Clear. On a rising edge,
this bit clears SYNC_ROTATE and SYNC_TRIP.
LMFC Sync Clear Last Error. On a rising edge,
this bit clears LASTERROR, LASTUNDER,
LASTOVER.
LMFC Sync Mode.
Sync one-shot mode
Sync continuous mode
Sync monitor only mode
Sync one-shot, then monitor
Reset
0x0
Access
R
0x0
0x0
R
R
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R
R/W
0x0
R
R
0x0
0x0
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Data Sheet
Address
0x03B
Name
SYNC_STATUS
AD9144
Bit No.
7
Bit Name
SYNC_BUSY
[6:4]
3
RESERVED
SYNC_LOCK
SYNC_ROTATE
Settings
1
1
1
1
SYNC_WLIM
1
SYNC_TRIP
1
0x03C
SYNC_CURRERR_L
[7:4]
[3:0]
RESERVED
CURRERROR
0x03D
SYNC_CURRERR_H
CURRUNDER
1
CURROVER
1
[5:0]
[7:2]
[1:0]
RESERVED
RESERVED
DACFSC_0[9:8]
DACGAIN0_0
DACGAIN1_1
[7:0]
[7:2]
[1:0]
DACFSC_0[7:0]
RESERVED
DACFSC_1[9:8]
0x043
0x044
DACGAIN1_0
DACGAIN2_1
[7:0]
[7:2]
[1:0]
DACFSC_1[7:0]
RESERVED
DACFSC_2[9:8]
0x045
DACGAIN2_0
[7:0]
DACFSC_2[7:0]
0x040
DACGAIN0_1
0x041
0x042
Description
LMFC Sync Machine Busy.
Sync logic SM is busy
Reserved.
LMFC Sync Alignment Locked.
Sync logic aligned within window
LMFC Sync Rotated.
Sync logic rotated with SYSREF (sticky)
LMFC Sync Alignment Limit Range.
Phase error outside window threshold
LMFC Sync Tripped After Arming.
Sync received SYSREF pulse (sticky)
Reserved.
LMFC Sync Alignment Error. 4-bit twos
complement value that represents the phase
error in number of DAC clock cycles (that is,
number of DAC clocks between LMFC edge and
SYSREF edge).
When an adjustment of the clocks is made
on any given SYSREF, the value of the phase
error is placed into SYNC_ LASTERR, and
SYNC_CURRERR is forced to 0.
LMFC Sync Current Error Under Flag.
Current phase error is beyond lower window
tolerance boundary
LMFC Sync Current Error Over Flag.
Current phase error is beyond upper window
tolerance boundary
Reserved.
Reserved.
2 MSBs of I-Channel DAC Gain Dual A. A 10bit twos complement value that is mapped
to analog full-scale current for DAC 0 as
shown:
01111111111 = 27.0 mA
0000000000 = 20.48 mA
1000000000 = 13.9 mA
8 LSBs of I-Channel DAC Gain Dual A.
Reserved.
2 MSBs of Q-Channel DAC Gain Dual A. A 10bit twos complement value that is mapped
to analog full-scale current for DAC 1 as
shown in Register 0x040.
01111111111 = 27.0 mA
0000000000 = 20.48 mA
1000000000 = 13.9 mA
8 LSBs of Q-Channel DAC Gain Dual A.
Reserved.
2 MSBs of I-Channel DAC Gain Dual B. A 10bit twos complement value that is mapped
to analog full-scale current for DAC as shown
in Register 0x040.
01111111111 = 27.0 mA
0000000000 = 20.48 mA
1000000000 = 13.9 mA
8 LSBs of I-Channel DAC Gain Dual B.
Reset
0x0
Access
R
0x0
0x0
R
R
0x0
0x0
0x0
0x0
0x0
R
R
0x0
0x0
0x0
0x0
0x0
R
R
R/W
0x0
0x0
0x0
R/W
R
R/W
0x0
0x0
0x0
R/W
R
R/W
0x0
R/W
AD9144
Data Sheet
Address
0x046
Name
DACGAIN3_1
Bit No.
[7:2]
[1:0]
Bit Name
RESERVED
DACFSC_3[9:8]
Settings
0x047
0x050
DACGAIN3_0
NCOALIGN_MODE
[7:0]
7
DACFSC_3[7:0]
NCO_ALIGN_ARM
6
5
RESERVED
NCO_ALIGN_
MTCH
Description
Reserved.
2 MSBs of Q-Channel DAC Gain Dual B. A 10bit twos complement value that is mapped
to analog full-scale current for DAC 3 as
shown in Register 0x40.
01111111111 = 27.0 mA
0000000000 = 20.48 mA
1000000000 = 13.9 mA
8 LSBs of Q-Channel DAC Gain Dual B.
Arm NCO Align. On a rising edge, arms the
NCO align operation.
Reserved.
NCO Align Data Match.
1
0
NCO_ALIGN_PASS
1
0
NCO_ALIGN_FAIL
1
0
2
[1:0]
RESERVED
NCO_ALIGN_
MODE
00
10
01
0x051
0x052
0x053
0x054
0x060
NCOKEY_ILSB
NCOKEY_IMSB
NCOKEY_QLSB
NCOKEY_QMSB
PDP_THRES0
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
NCOKEYI[7:0]
NCOKEYI[15:8]
NCOKEYQ[7:0]
NCOKEYQ[15:8]
PDP_THRESHOLD[7:0]
0x061
PDP_THRES1
[7:5]
[4:0]
0x062
PDP_AVG_TIME
7
[6:4]
[3:0]
RESERVED
PDP_
THRESHOLD[12:8]
PDP_ENABLE
RESERVED
PDP_AVG_TIME
0x063
PDP_POWER0
[7:0]
PDP_POWER[7:0]
0x064
PDP_POWER1
[7:5]
[4:0]
RESERVED
PDP_POWER[12:8]
Reset
0x0
0x0
Access
R
R/W
0x0
0x0
R/W
R/W
0x0
0x0
R
R
0x0
0x0
0x0
0x0
R
R/W
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
0x0
0x0
R
R/W
0x0
0x0
0x0
R/W
R
R/W
0x0
0x0
0x0
R
R
Data Sheet
Address
0x080
0x081
Name
CLKCFG0
SYSREF_ACTRL0
AD9144
Bit No.
7
Bit Name
PD_CLK01
Settings
PD_CLK23
PD_CLK_DIG
PD_SERDES_PCLK
PD_CLK_REC
[2:0]
[7:5]
4
RESERVED
RESERVED
PD_SYSREF
HYS_ON
SYSREF_RISE
0
1
0x082
0x083
0x084
SYSREF_ACTRL1
DACPLLCNTRL
DACPLLSTATUS
[1:0]
HYS_CNTRL1
[7:0]
7
HYS_CNTRL0
RECAL_DACPLL
[6:5]
4
RESERVED
ENABLE_DACPLL
[3:0]
7
RESERVED
DACPLL_
OVERRANGE_H
DACPLL_
OVERRANGE_L
DACPLL_CAL_
VALID
[4:2]
1
RESERVED
DACPLL_LOCK
RESERVED
Description
Power-Down Clock for Dual A. This bit
disables the digital and analog clocks for
Dual A.
Power-Down Clock for Dual B. This bit
disables the digital and analog clocks for
Dual B.
Power-Down Clocks to all DACs. This bit
disables the digital and analog clocks for
both duals. This includes all reference clocks,
PCLK, DAC clocks, and digital clocks.
Serdes PLL Clock Power-Down. This bit
disables the reference clock to the SERDES
PLL, which is needed to have an operational
serial interface.
Clock Receiver Power-Down. This bit powers
down the analog DAC clock receiver block.
With this bit set, clocks are not passed to
internal nets.
Reserved.
Reserved.
Power-Down SYSREF Buffer. This bit powers
down the SYSREF receiver. For Subclass 1
operation to work, this buffer must be enabled.
Hysteresis Enabled. This bit enables the
programmable hysteresis control for the
SYSREF receiver. Using hysteresis gives some
noise resistance, but delays the SYSREF
edge an amount depending on HYS_CNTRL
and the SYSREF edge rate. The SYSREF
KOW is not guaranteed when using hysteresis.
Select DAC Clock Edge to Sample SYSREF.
Use falling edge of DAC clock to sample
SYSREF for alignment
Use rising edge of DAC clock to sample
SYSREF for alignment
Hysteresis Control Bits[9:8]. HYS_CNTRL is a
10-bit thermometer-coded number. Each bit
set adds 10 mV of differential hysteresis to
the SYSREF receiver.
Hysteresis Control Bits[7:0].
Recalibrate DAC PLL. On a rising edge of this bit,
recalibrate the DAC PLL.
Reserved.
Synthesizer Enable. This bit enables and
calibrates the DAC PLL.
Reserved.
DAC PLL High Overrange. This bit indicates
that the DAC PLL hit the upper edge of its
operating band. Recalibrate.
DAC PLL Low Overrange. This bit indicates
that the DAC PLL hit the lower edge of its
operating band. Recalibrate.
DAC PLL Calibration Valid. This bit indicates
that the DAC PLL has been successfully
calibrated.
Reserved.
DAC PLL Lock Bit. This bit is set high by the PLL
when it has achieved lock.
Reserved.
Reset
0x1
Access
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x0
0x0
0x1
R
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R/W
R/W
0x0
0x0
R
R/W
0x0
0x0
R
R
0x0
0x0
0x0
0x0
R
R
0x0
AD9144
Data Sheet
Address
0x085
Name
DACINTEGERWORD0
Bit No.
[7:0]
Bit Name
B_COUNT
0x087
DACLOOPFILT1
[7:4]
LF_C2_WORD
[3:0]
LF_C1_WORD
[7:4]
LF_R1_WORD
[3:0]
LF_C3_WORD
LF_BYPASS_R3
LF_BYPASS_R1
LF_BYPASS_C2
LF_BYPASS_C1
[3:0]
LF_R3_WORD
0x088
0x089
DACLOOPFILT2
DACLOOPFILT3
0x08A
DACCPCNTRL
[7:6]
[5:0]
RESERVED
CP_CURRENT
0x08B
DACLOGENCNTRL
[7:2]
[1:0]
RESERVED
LO_DIV_MODE
Settings
01
10
11
Description
Integer Division Word. This bit controls the
integer feedback divider for the DAC PLL.
Determine the frequency of the DAC clock by
the following equations (see the DAC PLL
Fixed Register Writes section for more
details):
fDAC = fREF/(REF_DIVRATE) 2 B_COUNT
fVCO = fREF/(REF_DIVRATE) 2 B_COUNT
LO_DIV_MODE
Minimum value is 6.
C2 Control Word. Set this control to 0x6 for
optimal performance.
C1 Control Word. Set this control to 0x2 for
optimal performance.
R1 Control Word. Set this control to 0xC for
optimal performance.
C3 Control Word. Set this control to 0x9 for
optimal performance.
Bypass R3 Resistor. When this bit is set,
bypass the R3 capacitor (set to 0 pF) when
R3_WORD is set to 0. Set this control to 0x0 for
optimal performance.
Bypass R1 Resistor. When this bit is set,
bypass the R1 capacitor (set to 0 pF) when
R1_WORD is set to 0. Set this control to 0x0 for
optimal performance.
Bypass C2 Capacitor. When this bit is set,
bypass the C2 capacitor (set to 0 pF) when
C2_WORD is set to 0. Set this control to 0x0 for
optimal performance.
Bypass C1 Capacitor. When this bit is set,
bypass the C1 capacitor (set to 0 pF) when
C1_WORD is set to 0. Set this control to 0x0 for
optimal performance.
R3 Control Word. Set this control to 0xE for
optimal performance.
Reserved.
Charge Pump Current Control. Set this control
to 0x12 for optimal performance.
Reserved.
This range controls the RF clock divider
between the VCO and DAC clock rates. The
options are 4, 8, or 16 division. Choose
the LO_DIV_MODE so that 6 GHz < fVCO < 12
GHz (see the DAC PLL Fixed Register Writes
section for more details):
DAC clock = VCO/4
DAC clock = VCO/8
DAC clock = VCO/16
Reset
0x8
Access
R/W
0x8
R/W
0x8
R/W
0x8
R/W
0x8
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x8
R/W
0x0
0x20
R
R/W
0x0
0x2
R
R/W
Data Sheet
Address
0x08C
Name
DACLDOCNTRL1
AD9144
Bit No.
[7:3]
[2:0]
Bit Name
RESERVED
REF_DIV_MODE
Settings
000
001
010
011
100
0x08D
DACLDOCNTRL2
[7:0]
DAC_LDO
0x0E2
CAL_CTRL_GLOBAL
[7:2]
1
RESERVED
CAL_START_AVG
CAL_EN_AVG
[7:4]
RESERVED
CAL_CLK_EN
1
0x0E7
CAL_CLKDIV
1
0
0x0E8
CAL_PAGE
[2:0]
[7:4]
[3:0]
RESERVED
RESERVED
CAL_PAGE
0x0E9
CAL_CTRL
CAL_FIN
CAL_ACTIVE
Description
Reserved.
Reference Clock Division Ratio. This field
controls the amount of division that is done
to the input clock at the CLK+/CLK pins
before it is presented to the PLL as a reference
clock. The reference clock frequency must be
between 35 MHz and 80 MHz, but the
CLK+/CLK input frequency can range from
35 MHz to 1 GHz. The user sets this division
to achieve a 35 MHz to 80 MHz PLL reference
frequency. For more details see the DAC PLL
Fixed Register Writes section.
1
2
4
8
16
DAC PLL LDO setting. This register must be
written to 0x7B for optimal performance.
Reserved.
Averaged Calibration Start. On rising edge,
calibrate the DACs. Only use if calibrating all
DACs.
Averaged Calibration Enable. Set prior to
starting calibration with CAL_START_AVG.
While this bit is set, calibration can be
performed, and the results are applied.
Enable averaged calibration
Must write the default value for proper
operation.
Enable Self Calibration Clock.
Enable calibration clock
Disable calibration clock
Reserved.
Reserved.
DAC Calibration Paging. Selects which of the
DACs are being accessed for calibration or
calibration readback. This paging affects
Register 0x0E9 and Register 0x0ED.
Calibration: any number of DACs can be
accessed simultaneously to write and
calibrate. Write a 1 to Bit x to include DAC x.
Readback: only one DAC at a time can be
accessed when reading back CAL_CTRL
(Register 0x0E9). Write a 1 to Bit x to read
from DAC x (the other bits must be 0).
Calibration finished. This bit is high when the
calibration has completed. If the calibration
completes and either CAL_ERRHI or CAL_
ERRLO is high, then the calibration cannot be
considered valid and are considered a timeout
event.
Calibration ran and is finished
Calibration Active. This bit is high while the
calibration is in progress.
Calibration is running
Reset
0x0
0x1
Access
R
R/W
0x2B
R/W
0x0
0x0
R
R/W
0x0
R/W
0x3
R/W
0x0
R/W
0x0
0x0
0xF
R
R
R/W
0x0
0x0
AD9144
Address
Name
Data Sheet
Bit No.
5
Bit Name
CAL_ERRHI
CAL_ERRLO
[3:2]
1
RESERVED
CAL_START
Settings
0
1
0
CAL_EN
0
1
0x0ED
CAL_INIT
[7:0]
CAL_INIT
0x110
DATA_FORMAT
BINARY_FORMAT
0
1
0x111
DATAPATH_CTRL
[6:0]
7
RESERVED
INVSINC_ENABLE
1
0
6
5
RESERVED
DIG_GAIN_ENABLE
1
0
PHASE_ADJ_
ENABLE
1
0
[3:2]
MODULATION_TYPE
00
01
10
11
SEL_SIDEBAND
I_TO_Q
Description
SAR Data Error: Too High. This bit is set at the
end of a calibration cycle if any of the calibration DACs has overranged to the high side.
This typically means that the algorithm adjusts
the calibration preset of the calibration DACs
and runs another cycle.
Data saturated high
SAR Data Error: Too Low. This bit is set at the
end of a calibration cycle if any of the calibration DACs has overranged to the low side.
This typically means that the algorithm adjusts
the calibration preset of the calibration DACs
and runs another cycle.
Data saturated low
Reserved.
Calibration Start. The rising edge of this bit
kicks off a calibration sequence for the DACs
that have been selected in the CAL_INDX
register.
Normal operation
Start calibration state machine
Calibration Enable. Enable the calibration
DAC of the converter. Enable to calibration
engine and machines. Prepare for a calibration
start. For calibration coefficients to be applied
to the calibrated DACs, this bit must be high.
Do not use calibration DACs
Use calibration DACs
Initialize Calibration. Must be written to 0xA2
before starting calibration or averaged
calibration.
Binary or Twos Complementary Format on
the Data Bus.
Input data is twos complement
Input data is offset binary
Reserved.
Enable Inverse Sinc Filter.
Enable inverse sinc filter
Disable inverse sinc filter
Reserved.
Enable Digital Gain.
Enable digital gain function
Disable digital gain function
Enable Phase Compensation.
Enable phase adjust compensation
Disable phase adjust compensation
Selects Type Of Modulation Operation.
No modulation
Fine modulation (uses FTW)
fS/4 coarse modulation
fS/8 coarse modulation
Spectrum Inversion Control. Can only be
used with fine modulation. This causes the
negative sideband to be selected and is
equivalent to changing the sign of FTW.
Send I Data into Q DAC datapath. Occurs at
the end of the digital datapath prior to
entering DACs.
Reset
0x0
Access
R
0x0
0x0
0x0
R
R/W
0x0
R/W
0xA6
R/W
0x0
R/W
0x0
0x1
R
R/W
0x0
0x1
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Data Sheet
Address
0x112
Name
INTERP_MODE
AD9144
Bit No.
[7:3]
[2:0]
Bit Name
RESERVED
INTERP_MODE
Settings
000
001
011
100
0x113
NCO_FTW_UPDATE
[7:2]
1
RESERVED
FTW_UPDATE_ACK
FTW_UPDATE_REQ
0x114
0x115
0x116
0x117
0x118
0x119
0x11A
FTW0
FTW1
FTW2
FTW3
FTW4
FTW5
NCO_PHASE_
OFFSET0
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
FTW[7:0]
FTW[15:8]
FTW[23:16]
FTW[31:24]
FTW[39:32]
FTW[47:40]
NCO_PHASE_
OFFSET[7:0]
0x11B
[7:0]
0x11C
NCO_PHASE_
OFFSET1
PHASE_ADJ0
[7:0]
NCO_PHASE_
OFFSET[15:8]
PHASE_ADJ[7:0]
0x11D
PHASE_ADJ1
0x11F
TXEN_SM_0
[7:5]
[4:0]
[7:6]
RESERVED
PHASE_ADJ[12:8]
FALL_COUNTERS
[5:4]
RISE_COUNTERS
3
2
RESERVED
PROTECT_OUT_
INVERT
[1:0]
RESERVED
Description
Reserved.
Interpolation Mode.
1 mode
2 mode
4 mode
8 mode
Reserved.
Frequency tuning word update acknowledge.
This readback is high when an FTW has been
updated.
Frequency tuning word update request from
SPI. Unlike most registers, those relating to
fine NCO modulation (Register 0x114 to
Register 0x11B) are not updated immediately
upon writing to them. Once the desired FTW
and phase offset values are written, set this
bit. These registers update on the rising edge
of this bit. It is only after this update that the
internal state matches Register 0x114 to
Register 0x11B. Confirmation that this
update has occurred can be made by reading
back bit 1 of this register and ensuring it is
set high for the update acknowledge.
NCO Frequency Tuning Word.
NCO Frequency Tuning Word.
NCO Frequency Tuning Word.
NCO Frequency Tuning Word.
NCO Frequency Tuning Word.
NCO Frequency Tuning Word.
8 LSBs of NCO Phase Offset.
NCO_PHASE_OFFSET changes the phase of
both I and Q data, and is only functional
when using NCO fine modulation. It is a 16bit twos complement number ranging from
180 to+180 degrees in steps of .0055.
8 MSBs of NCO Phase Offset.
Reset
0x0
0x1
Access
R
R/W
0x0
0x0
R
R
0x0
R/W
0x0
0x0
0x0
0x0
0x0
0x10
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0
R/W
0x0
R/W
0x0
0x0
0x2
R
R/W
R/W
0x0
R/W
0x0
0x0
R
R/W
0x3
R/W
AD9144
Data Sheet
Address
0x121
Name
TXEN_RISE_
COUNT_0
Bit No.
[7:0]
Bit Name
RISE_COUNT_0
0x122
TXEN_RISE_
COUNT_1
[7:0]
RISE_COUNT_1
0x123
TXEN_FALL_
COUNT_0
[7:0]
FALL_COUNT_0
0x124
TXEN_FALL_
COUNT_1
[7:0]
FALL_COUNT_1
0x12D
DEVICE_CONFIG_
REG_0
DIE_TEMP_CTRL0
[7:0]
DEVICE_CONFIG_0
[7:1]
RESERVED
AUXADC_ENABLE
0x12F
Settings
0
1
0x132
0x133
0x134
DIE_TEMP0
DIE_TEMP1
DIE_TEMP_UPDATE
[7:0]
[7:0]
[7:1]
0
0x135
DC_OFFSET_CTRL
[7:1]
0
DIE_TEMP[7:0]
DIE_TEMP[15:8]
RESERVED
DIE_TEMP_
UPDATE
RESERVED
DC_OFFSET_ON
0x136
IPATH_DC_OFFSET_
1PART0
[7:0]
LSB_OFFSET_I[7:0]
0x137
IPATH_DC_OFFSET_
1PART1
[7:0]
LSB_OFFSET_I[15:8]
0x138
QPATH_DC_OFFSET_
1PART0
[7:0]
LSB_OFFSET_
Q[7:0]
0x139
QPATH_DC_OFFSET_
1PART1
[7:0]
LSB_OFFSET_
Q[15:8]
0x13A
IPATH_DC_OFFSET_
2PART
[7:5]
RESERVED
[4:0]
SIXTEENTH_
OFFSET_I
[7:5]
RESERVED
[4:0]
SIXTEENTH_
OFFSET_Q
x
0x13B
QPATH_DC_OFFSET_
2PART
x
0x13C
IDAC_DIG_GAIN0
[7:0]
IDAC_DIG_
GAIN[7:0]
0x13D
IDAC_DIG_GAIN1
[7:4]
[3:0]
RESERVED
IDAC_DIG_
GAIN[11:8]
Description
First counter used to delay TX_PROTECT rise
from TXENx rising edge. Delays by 32
RISE_COUNT_0 DAC clock cycles.
Second counter used to delay TX_PROTECT
rise from TXENx rising edge. Delays by 32
RISE_COUNT_1 DAC clock cycles.
First counter used to delay TX_PROTECT fall
from TXENx falling edge. Delays by 32
FALL_COUNT_0 DAC clock cycles. Must be
set to a minimum of 0x12.
Second counter used to delay TX_PROTECT
fall from TXENx falling edge. Delays by 32
FALL_COUNT_1 DAC clock cycles.
Must be set to 0x8B for proper digital
datapath configuration.
Must write the default value for proper
operation.
Enables the AUX ADC Block.
AUX ADC disable
AUX ADC enable
Aux ADC Readback Value.
Aux ADC Readback Value.
Reserved.
Die Temperature Update. On a rising edge, a
new temperature code is generated.
Reserved.
DC Offset On.
Enables dc offset module
8 LSBs of IPath DC Offset. LSB_OFFSET_I is a
16-bit twos complement number that is
added to incoming data.
8 MSBs of IPath DC Offset. LSB_OFFSET_I is a
16-bit twos complement number that is
added to incoming I data.
8 LSBs of QPath DC Offset. LSB_OFFSET_Q is a
16-bit twos complement number that is
added to incoming Q data.
8 MSBs of QPath DC Offset. LSB_OFFSET_Q is
a 16-bit twos complement number that is
added to incoming Q data.
Reserved.
SIXTEENTH_OFFSET_I is a 5-bit twos
complement number in 16ths of an LSB that
is added to incoming I data.
x/16 LSB DC offset
Reserved.
SIXTEENTH_OFFSET_Q is a 5-bit twos
complement number in 16ths of an LSB that
is added to incoming Q data.
x/16 LSB DC offset
8 LSBs of I DAC Digital Gain. IDAC_DIG_GAIN
is the digital gain of the IDAC. The digital
gain is a multiplier from 0 to 4095/2048 in
steps of 1/2048.
Reserved.
4 MSBs of I DAC Digital Gain
Reset
0xF
Access
R/W
0x0
R/W
0xFF
R/W
0xFF
R/W
0x46
R/W
0x10
R/W
0x0
R/W
0x0
0x0
0x0
0x0
R
R
R
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R/W
0x0
0x0
R/W
0xEA
R/W
0x0
0xA
R
R/W
Data Sheet
AD9144
Address
0x13E
Name
QDAC_DIG_GAIN0
Bit No.
[7:0]
Bit Name
QDAC_DIG_
GAIN[7:0]
Settings
0x13F
QDAC_DIG_GAIN1
[7:4]
[3:0]
0x140
GAIN_RAMP_UP_
STEP0
[7:0]
RESERVED
QDAC_DIG_
GAIN[11:8]
GAIN_RAMP_UP_
STEP[7:0]
0x0
0xFFF
0x141
0x142
GAIN_RAMP_UP_
STEP1
GAIN_RAMP_DOWN_
STEP0
[7:4]
RESERVED
[3:0]
GAIN_RAMP_UP_
STEP[11:8]
GAIN_RAMP_
DOWN_STEP[7:0]
[7:0]
0
0xFFF
0x143
0x146
0x147
GAIN_RAMP_
DOWN_STEP1
DEVICE_CONFIG_
REG_1
BSM_STAT
[7:4]
RESERVED
[3:0]
[7:0]
GAIN_RAMP_
DOWN_STEP[11:8]
DEVICE_CONFIG_1
[7:6]
SOFTBLANKRB
00
01
10
11
0x14B
PRBS
[5:0]
7
RESERVED
PRBS_GOOD_Q
0
1
PRBS_GOOD_I
0
1
[5:3]
2
RESERVED
PRBS_MODE
0
1
PRBS_RESET
0
1
PRBS_EN
0
1
0x14C
0x14D
0x1B0
PRBS_ERROR_I
PRBS_ERROR_Q
DACPLLT0
[7:0]
[7:0]
[7:0]
PRBS_COUNT_I
PRBS_COUNT_Q
DAC_PLL_PWR
Description
8 LSBs of Q DAC Digital Gain.
QDAC_DIG_GAIN is the digital gain of the
QDAC. The digital gain is a multiplier from 0
to 4095/2048 in steps of 1/2048.
Reserved.
4 MSBs of Q DAC Digital Gain.
Reset
0xEA
Access
R/W
0x0
0xA
R
R/W
0x4
R/W
0x0
0x0
R/W
0x9
R/W
0x0
0x0
R/W
0x0
R/W
0x0
0x0
0x0
R
R
0x0
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
0x0
0xFA
R
R
R/W
AD9144
Address
0x1B5
Name
DACPLLT5
Data Sheet
Bit No.
[7:4]
Bit Name
RESERVED
[3:0]
VCO_VAR
0x1B9
DACPLLT9
[7:0]
DAC_PLL_CP1
0x1BB
DACPLLTB
[7:5]
[4:3]
RESERVED
VCO_BIAS_TCF
[2:0]
VCO_BIAS_REF
Settings
0x1BC
DACPLLTC
[7:0]
DAC_PLL_VCO_
CTRL
0x1BE
DACPLLTE
[7:0]
DAC_PLL_VCO_
PWR
0x1BF
DACPLLTF
[7:0]
DAC_PLL_VCOCAL
0x1C0
DACPLLT10
[7:0]
0x1C1
DACPLLT11
[7:0]
DAC_PLL_LOCK_
CNTR
DAC_PLL_CP2
0x1C4
DACPLLT17
[7:0]
DAC_PLL_VAR1
0x1C5
DACPLLT18
[7:0]
DAC_PLL_VAR2
0x200
MASTER_PD
[7:1]
0
RESERVED
SPI_PD_MASTER
0x201
PHY_PD
[7:0]
SPI_PD_PHY
0x203
GENERIC_PD
[7:2]
1
RESERVED
SPI_SYNC1_PD
0x206
CDR_RESET
Description
Must write the default value for proper
operation.
Varactor KVO Setting. See Table 83 for
optimal settings based on the fVCO being used.
DAC PLL Charge Pump settings. This register
must be written to 0x24 for optimal
performance.
Reserved.
Temperature Coefficient for VCO Bias. See
Table 83 for optimal settings based on the
fVCO being used.
VCO Bias Control. See Table 83 for optimal
settings based on the fVCO being used.
DAC PLL VCO control settings. This register
must be written to 0x0D for optimal
performance.
DAC PLL VCO power control settings. This
register must be written to 0x02 for optimal
performance.
DAC PLL VCO calibration settings. This
register must be written to 0x8E for optimal
performance.
This register must be written to 0x2A for
optimal performance.
This register must be written to0x2A for
optimal performance.
DAC PLL Varactor setting. Must be set to
0x7E for proper DAC PLL configuration.
DAC PLL Varactor setting. See Table 83 for
optimal settings based on the fVCO being used.
Reserved.
Power Down the Entire JESD Receiver Analog
(All Eight Channels Plus Bias).
SPI Override to Power Down the Individual
PHYs.
Set Bit x to power down the corresponding
SERDINx PHY
Reserved.
Power down LVDS buffer for SYNCOUT0.
0x232
CDR_OPERATING_
MODE_REG_0
DEVICE_CONFIG_
REG_3
Access
R/W
0x3
R/W
0x34
R/W
0x0
0x1
R
R/W
0x4
R/W
0x00
R/W
0x00
R/W
0x8D
R/W
0x2E
R/W
0x24
R/W
0x33
R/W
0x08
R/W
0x0
0x1
R
R/W
0x0
R/W
0x0
0x0
R
R/W
SPI_SYNC2_PD
0x0
R/W
[7:1]
0
RESERVED
SPI_CDR_RESETN
Reserved.
Resets the Digital Control Logic for All PHYs.
Hold CDR in reset
Enable CDR
Reserved.
0x0
0x1
R
R/W
0x0
0x1
R/W
0x2
R/W
0x0
R/W
0x0
0x0
R
R/W
0
1
0x230
Reset
0x8
[7:6]
RESERVED
ENHALFRATE
[4:2]
RESERVED
CDR_OVERSAMP
0
[7:0]
RESERVED
DEVICE_CONFIG_3
Data Sheet
Address
0x268
Name
EQ_BIAS_REG
AD9144
Bit No.
[7:6]
Bit Name
EQ_POWER_
MODE
Settings
00
01
0x280
0x281
SERDESPLL_
ENABLE_CNTRL
PLL_STATUS
[5:0]
RESERVED
[7:3]
RESERVED
RECAL_SERDESPLL
1
0
RESERVED
ENABLE_
SERDESPLL
RESERVED
SERDES_PLL_
OVERRANGE_H
[7:6]
5
SERDES_PLL_
OVERRANGE_L
SERDES_PLL_CAL_
VALID_RB
[2:1]
0
0x284
LOOP_FILTER_1
[7:0]
RESERVED
SERDES_PLL_
LOCK_RB
LOOP_FILTER_1
0x285
LOOP_FILTER_2
[7:0]
LOOP_FILTER_2
0x286
LOOP_FILTER_3
[7:0]
LOOP_FILTER_3
0x287
SERDES_PLL_CP1
[7:0]
SERDES_PLL_CP1
0x289
REF_CLK_DIVIDER_
LDO
[7:3]
RESERVED
DEVICE_CONFIG_4
[1:0]
SERDES_PLL_DIV_
MODE
00
01
10
0x28A
VCO_LDO
[7:0]
SERDES_PLL_
VCO_LDO
0x28B
SERDES_PLL_PD1
[7:0]
SERDES_PLL_PD1
0x290
SERDESPLL_VAR1
[7:0]
SERDES_PLL_VAR1
Description
Control the Equalizer Power/Insertion Loss
Capability.
Normal mode
Low power mode
Must write the default value for proper
operation.
Reserved.
Reset
0x1
Access
R/W
0x22
R/W
0x0
0x0
R/W
0x0
0x0
R
R/W
0x0
0x0
R
R
0x0
0x0
0x0
0x0
R
R
0x77
R/W
0x87
R/W
0x08
R/W
0x3F
R/W
0x0
0x0
R/W
0x0
R/W
0x2B
R/W
0x7F
R/W
0x83
R/W
AD9144
Data Sheet
Address
0x294
Name
SERDES_PLL_CP2
Bit No.
[7:0]
Bit Name
SERDES_PLL_CP2
0x296
SERDESPLL_VCO1
[7:0]
0x297
SERDESPLL_VCO2
[7:0]
0x299
SERDES_PLL_PD2
[7:0]
SERDES_PLL_
VCO1
SERDES_PLL_
VCO2
SERDES_PLL_PD2
0x29A
SERDESPLL_VAR2
[7:0]
SERDES_PLL_VAR2
0x29C
SERDES_PLL_CP3
[7:0]
SERDES_PLL_CP3
0x29F
SERDESPLL_VAR3
[7:0]
SERDES_PLL_VAR3
0x2A0
SERDESPLL_VAR4
[7:0]
SERDES_PLL_VAR4
0x2A4
DEVICE_CONFIG_
REG_8
SYNCOUTB_SWING
[7:0]
DEVICE_CONFIG_8
[7:1]
0
RESERVED
SYNCOUTB_
SWING_MD
0x2A5
Settings
0
1
0x2A7
TERM_BLK1_
CTRLREG0
[7:1]
0
RESERVED
RCAL_TERMBLK1
0x2AA
DEVICE_CONFIG_
REG_9
DEVICE_CONFIG_
REG_10
TERM_BLK2_
CTRLREG0
[7:0]
[7:1]
DEVICE_CONFIG_
9
DEVICE_CONFIG_
10
RESERVED
RCAL_TERMBLK2
[7:0]
DEVICE_CONFIG_
11
DEVICE_CONFIG_
12
RESERVED
CHECKSUM_MODE
0x2AB
0x2AE
0x2B1
0x2B2
0x300
DEVICE_CONFIG_
REG_11
DEVICE_CONFIG_
REG_12
GENERAL_JRX_
CTRL_0
[7:0]
[7:0]
7
6
[5:4]
RESERVED
Description
SERDES PLL Charge Pump setting. This
register must be set to 0x24 for optimal
performance.
SERDES PLL VCO setting. This register must
be set to 0x03 for optimal performance.
SERDES PLL VCO setting. This register must
be set to 0x0D for optimal performance.
SERDES PLL PD setting. This register must be
set to 0x02 for optimal performance.
SERDES PLL Varactor setting. This register
must be set to 0x8E for optimal performance.
SERDES PLL Charge Pump setting. Must be
set to 0x2A for proper SERDES PLL
configuration.
SERDES PLL varactor setting. Must be set to
0x78 for proper SERDES PLL configuration.
SERDES PLL varactor setting. This register
must be set to 0x06 for optimal performance.
Must be set to 0xFF for proper clock
configuration.
Reserved.
SYNCOUTx Swing Mode. Sets the output
differential swing mode for the SYNCOUTx
pins. See Table 8 for details.
Normal Swing Mode
High Swing Mode
Reserved.
Termination Calibration. The rising edge of
this bit calibrates PHY0, PHY1, PHY6, and PHY7
terminations to 50 .
Must be set to 0xB7 for proper JESD interface
termination configuration.
Must be set to 0x87 for proper JESD interface
termination configuration.
Reserved.
Terminal Calibration. The rising edge of this
bit calibrates PHY2, PHY3, PHY4 and PHY5
terminations to 50 .
Must be set to 0xB7 for proper JESD interface
termination configuration.
Must be set to 0x87 for proper JESD interface
termination configuration.
Reserved.
Checksum Mode. This bit controls the locally
generated JESD204B link parameter checksum
method. The value is stored in the FCMP
registers (Register 0x40E, Register 0x416,
Register 0x41E, Register 0x426, Register
0x42E, Register 0x436, Register 0x43E, and
Register 0x446).
Checksum is calculated by summing the
individual fields in the link configuration
table as defined in Section 8.3, Table 20 of
the JESD204B standard
Checksum is calculated by summing the registers containing the packed link configuration
fields ([0x450:0x45A] modulo 256).
Reserved.
Reset
0xB0
Access
R/W
0x0C
R/W
0x00
R/W
0x00
R/W
0xFE
R/W
0x17
R/W
0x33
R/W
0x08
R/W
0x4B
R/W
0x0
0x0
R
R/W
0x0
0x0
R
R/W
0xC3
R/W
0x93
R/W
0x0
0x0
R/W
0xC3
R/W
0x93
R/W
0x0
0x0
R
R/W
0x0
Data Sheet
Address
Name
AD9144
Bit No.
3
Bit Name
LINK_MODE
Settings
0
1
2
LINK_PAGE
0
1
[1:0]
LINK_EN
0b00
0b01
0b10
0b11
0x301
GENERAL_JRX_CTRL_1
[7:3]
[2:0]
RESERVED
SUBCLASSV_
LOCAL
000
001
0x302
DYN_LINK_LATENCY_0
[7:5]
[4:0]
RESERVED
DYN_LINK_
LATENCY_0
0x303
DYN_LINK_LATENCY_1
[7:5]
[4:0]
RESERVED
DYN_LINK_
LATENCY_1
0x304
LMFC_DELAY_0
[7:5]
[4:0]
RESERVED
LMFC_DELAY_0
0x305
LMFC_DELAY_1
[7:5]
[4:0]
RESERVED
LMFC_DELAY_1
0x306
LMFC_VAR_0
[7:5]
[4:0]
RESERVED
LMFC_VAR_0
0x307
LMFC_VAR_1
[7:5]
[4:0]
RESERVED
LMFC_VAR_1
Description
Link Mode. This register selects either singlelink or dual-link mode.
Single-link mode
Dual-link mode
Link Paging. Selects which links register map
is used. This paging affects Registers 0x401
to 0x47E.
Use Link 0 register map
Use Link 1 register map
Link Enable. These bits bring up the JESD204B
receiver digital circuitry: Bit 0 for Link 0 and
Bit 1 for Link 1. Enable the link only after the
following has occurred: all JESD204B parameters are set, the DAC PLL is enabled and
locked (Register 0x084[1] = 1), and the
JESD204B PHY is enabled (Register 0x200 =
0x00) and calibrated (Register 0x281[2] = 0).
Disable both JESD Link 1 and JESD Link 0
Disable JESD Link 1, enable JESD Link 0
Enable JESD Link 1, disable JESD Link 0
Enable both JESD Link 1 and JESD Link 0
Reserved.
JESD204B Subclass.
Subclass 0
Subclass 1
Reserved.
Dynamic Link Latency: Link 0. Latency
between the LMFCRx for link 0 and the last
arriving LMFC boundary in units of PCLK
cycles. See the Deterministic Latency section.
Reserved.
Dynamic Link Latency: Link 1. Latency
between the LMFCRx for link 1 and the last
arriving LMFC boundary in units of PCLK
cycles. See the Deterministic Latency section.
Reserved.
LMFC Delay: Link 0 Delay from the LMFC to
LMFCRx for Link 0. In units of frame clock
cycles for subclass 1 and PCLK cycles for
subclass 0. See the Deterministic Latency
section.
Reserved.
LMFC Delay: Link 1. Delay from the LMFC to
LMFCRx for Link 1. In units of frame clock
cycles for subclass 1 and PCLK cycles for
subclass 0. See the Deterministic Latency
section.
Reserved.
Variable Delay Buffer: Link 0. Sets when data is
read from a buffer to be consistent across links
and power cycles. In units of PCLK cycles. See
the Deterministic Latency section.
This setting must not be more than 10.
Reserved.
Variable Delay Buffer: Link 1. Sets when data is
read from a buffer to be consistent across links
and power cycles. In units of PCLK cycles. See
the Deterministic Latency section.
This setting must not be more than 10.
Reset
0x0
Access
R/W
0x0
R/W
0x0
R/W
0x0
0x1
R
R/W
0x0
0x0
R
R
0x0
0x0
R
R
0x0
0x0
R
R/W
0x0
0x0
R
R/W
0x0
0x6
R
R/W
0x0
0x6
R
R/W
AD9144
Address
0x308
Name
XBAR_LN_0_1
Data Sheet
Bit No.
[7:6]
[5:3]
Bit Name
RESERVED
LOGICAL_LANE1_
SRC
[2:0]
LOGICAL_LANE0_
SRC
[7:6]
[5:3]
RESERVED
LOGICAL_LANE3_
SRC
[2:0]
LOGICAL_LANE2_
SRC
[7:6]
[5:3]
RESERVED
LOGICAL_LANE5_
SRC
[2:0]
LOGICAL_LANE4_
SRC
[7:6]
[5:3]
RESERVED
LOGICAL_LANE7_
SRC
[2:0]
LOGICAL_LANE6_
SRC
Settings
x
0x309
XBAR_LN_2_3
x
0x30A
XBAR_LN_4_5
x
0x30B
XBAR_LN_6_7
x
0x30C
FIFO_STATUS_REG_0
[7:0]
LANE_FIFO_FULL
0x30D
FIFO_STATUS_REG_1
[7:0]
LANE_FIFO_EMPTY
0x312
SYNCB_GEN_1
[7:6]
[5:4]
RESERVED
SYNCB_ERR _DUR
0
1
2
0x314
SERDES_SPI_REG
[3:0]
[7:0]
0x315
PHY_PRBS_TEST_EN
[7:0]
RESERVED
SERDES_SPI_
CONFIG
PHY_TEST_EN
Description
Reserved.
Logical Lane 1 Source. Selects a physical lane
to be mapped onto Logical Lane 1.
Data is from SERDINx
Logical Lane 0 Source. Selects a physical lane
to be mapped onto Logical Lane 0.
Data is from SERDINx
Reserved.
Logical Lane 3 Source. Selects a physical lane
to be mapped onto Logical Lane 3.
Data is from SERDINx
Logical Lane 2 source. Selects a physical lane
to be mapped onto Logical Lane 2.
Data is from SERDINx
Reserved.
Logical Lane 5 Source. Selects a physical lane
to be mapped onto Logical Lane 5.
Data is from SERDINx
Logical Lane 4 Source. Selects a physical lane
to be mapped onto Logical Lane 4.
Data is from SERDINx
Reserved.
Logical Lane 7 Source. Selects a physical lane
to be mapped onto Logical Lane 7.
Data is from SERDINx
Logical Lane 6 Source. Selects a physical lane
to be mapped onto Logical Lane 6.
Data is from SERDINx
FIFO Full Flags for Each Logical Lane. A full
FIFO indicates an error in the JESD204B
configuration or with a system clock.
If the FIFO for Lane x is full, Bit x in this
register will be high.
FIFO Empty Flags for Each Logical Lane. An
empty FIFO indicates an error in the JESD204B
configuration or with a system clock.
If the FIFO for Logical Lane x is empty, Bit x in
this register will be high.
Reserved.
Duration of SYNCOUTx Low for Error. The
duration applies to both SYNCOUT0 and
SYNCOUT1. A sync error is asserted at the
end of a multiframe whenever one or more
disparity, not in table or unexpected control
character errors are encountered.
PCLK cycle
1 PCLK cycle
2 PCLK cycles
Reserved.
SERDES SPI Configuration. Must be written to
0x01 as part of the Physical Layer setup step.
PHY Test Enable. Enables the PHY BER test.
Set Bit x to enable the PHY test for Lane x.
Reset
0x0
0x1
Access
R
R/W
0x0
R/W
0x0
0x3
R
R/W
0x2
R/W
0x0
0x5
R
R/W
0x4
R/W
0x0
0x7
R
R/W
0x6
R/W
0x0
0x0
0x0
R/W
0x0
0x0
R/W
R/W
0x0
R/W
Data Sheet
Address
0x316
Name
PHY_PRBS_TEST_CTRL
AD9144
Bit No.
7
[6:4]
Bit Name
RESERVED
PHY_SRC_ERR_CNT
[3:2]
PHY_PRBS_PAT_SEL
Settings
00
01
10
1
PHY_TEST_START
0
1
PHY_TEST_RESET
0
1
0x317
0x318
0x319
0x31A
0x31B
0x31C
0x31D
0x32C
PHY_PRBS_TEST_
THRESHOLD_LOBITS
PHY_PRBS_TEST_
THRESHOLD_
MIDBITS
PHY_PRBS_TEST_
THRESHOLD_HIBITS
PHY_PRBS_TEST_
ERRCNT_LOBITS
[7:0]
PHY_PRBS_TEST_
ERRCNT_MIDBITS
PHY_PRBS_TEST_
ERRCNT_HIBITS
PHY_PRBS_TEST_
STATUS
[7:0]
SHORT_TPL_TEST_0
[7:6]
[5:4]
RESERVED
SHORT_TPL_SP_
SEL
[3:2]
SHORT_TPL_DAC_
SEL
SHORT_TPL_TEST_
RESET
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
PHY_PRBS_
THRESHOLD[7:0]
PHY_PRBS_
THRESHOLD[15:8]
PHY_PRBS_
THRESHOLD[23:16]
PHY_PRBS_ERR_
CNT[7:0]
PHY_PRBS_ERR_
CNT[15:8]
PHY_PRBS_ERR_
CNT[23:16]
PHY_PRBS_PASS
0
1
0
SHORT_TPL_TEST_
EN
0
1
0x32D
SHORT_TPL_TEST_1
[7:0]
SHORT_TPL_REF_
SP_LSB
Description
Reserved.
PHY Error Count Source. Selects which PHY
errors are being reported in Register 0x31A
to Register 0x31C.
Report Lane x error count
PHY PRBS Pattern Select. Selects the PRBS
pattern for PHY BER test.
PRBS7
PRBS15
PRBS31
PHY PRBS Test Start. Starts and stops the PHY
PRBS test.
Test stopped
Test in progress
PHY PRBS Test Reset. Resets the PHY PRBS
test state machine and error counters.
Enable PHY PRBS test state machine
Hold PHY PRBS test state machine in reset
8 LSBs of PHY PRBS Error Threshold.
Reset
0x0
0x0
Access
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
0x0
0xFF
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
AD9144
Data Sheet
Address
0x32E
Name
SHORT_TPL_TEST_2
Bit No.
[7:0]
Bit Name
SHORT_TPL_REF_
SP_MSB
0x32F
SHORT_TPL_TEST_3
[7:1]
0
RESERVED
SHORT_TPL_FAIL
Settings
0
1
0x333
[7:0]
DEVICE_CONFIG_
13
JESD_BIT_INVERSE
0x400
DEVICE_CONFIG_
REG_13
JESD_BIT_INVERSE_
CTRL
DID_REG
[7:0]
DID_RD
0x401
BID_REG
[7:4]
ADJCNT_RD
[3:0]
BID_RD
7
6
RESERVED
ADJDIR_RD
PHADJ_RD
[4:0]
LID0_RD
SCR_RD
0x334
0x402
0x403
LID0_REG
SCR_L_REG
[7:0]
0
1
[6:5]
[4:0]
RESERVED
L-1_RD
0
1
3
0x404
F_REG
[7:0]
F-1_RD
0
1
3
Description
Short Transport Layer Test Reference, Sample
MSB. This is the upper eight bits of the
expected DAC sample. It is used to compare
with the received DAC sample at the output
of the JESD204B receiver.
Reserved.
Short Transport Layer Test Fail. This bit shows
whether the selected DAC sample matches
the reference sample. If they match, it is a
test pass, otherwise it is a test fail.
Test pass
Test fail
Must be set to 0x01 for proper JESD interface
configuration.
Logical Lane Invert. Set Bit x high to invert
the JESD deserialized data on Logical Lane x.
Device Identification Number. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
Adjustment Resolution to DAC LMFC. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
Must be 0.
Bank Identification: Extension to DID. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
Reserved.
Direction to Adjust DAC LMFC. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B. Must be 0.
Phase Adjustment Request to DAC Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B. Must be 0.
Lane Identification for Lane 0. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
Transmit Scrambling Status.
Link information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
Scrambling is disabled
Scrambling is enabled
Reserved.
Number of Lanes per Converter Device. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
One lane per converter
Two lanes per converter
Four lanes per converter
Number of Octets per Frame. Settings of 1, 2
and 4 octets per frame are valid. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
(One octet per frame) per lane
(Two octets per frame) per lane
(Four octets per frame) per lane
Reset
0x0
Access
R/W
0x0
0x0
R
R
00
R/W
0x0
R/W
0x0
0x0
0x0
0x0
0x0
R
R
0x0
0x0
0x0
0x0
0x0
R
R
0x0
Data Sheet
Address
0x405
Name
K_REG
AD9144
Bit No.
[7:5]
[4:0]
Bit Name
RESERVED
K-1_RD
Settings
0x0F
0x1F
0x406
M_REG
[7:0]
M-1_RD
0
1
3
0x407
CS_N_REG
[7:6]
CS_RD
5
[4:0]
RESERVED
N-1_RD
[7:5]
SUBCLASSV_RD
[4:0]
NP-1_RD
[7:5]
JESDV_RD
0x0F
0x408
NP_REG
0x0F
0x409
S_REG
000
001
[4:0]
S-1_RD
0
1
0x40A
HD_CF_REG
HD_RD
0
1
0x40B
RES1_REG
[6:5]
[4:0]
RESERVED
CF_RD
[7:0]
RES1_RD
Description
Reserved.
Number of Frames per Multiframe. Settings
of 16 or 32 are valid. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B.
16 frames per multiframe
32 frames per multiframe
Number of converters per device. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B. Must be
0, 1, or 3.
One converter per device
Two converters per device
Four converters per device
Number of Control Bits per Sample. Link
information received on Link Lane 0 as specified
in Section 8.3 of JESD204B. CS must be 0.
Reserved.
Converter Resolution. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B. Converter
resolution must be 16.
Converter resolution of 16
Device Subclass Version. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B.
Total Number of Bits per Sample. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B. Must be
16 bits per sample.
16 bits per sample.
JESD204 Version. Link information received
on Link Lane 0 as specified in Section 8.3 of
JESD204B.
JESD204A
JESD204B
Number of Samples per Converter per Frame
Cycle. Settings of one and two are valid. See
Table 35 and Table 36. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B.
One sample per converter per frame
Two samples per converter per frame
High Density Format. See Section 5.1.3 of the
JESD294B standard. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B.
Low density mode
High density mode: link information received
on Lane 0 as specified in Section 8.3 of
JESD204B
Reserved.
Number of Control Words per Frame Clock
Period per Link. Link information received on
Link Lane 0 as specified in Section 8.3 of
JESD204B. Bits[4:0] must be 0.
Reserved Field 1. Link information received on
Link Lane 0 as specified in Section 8.3 of
JESD204B.
Reset
0x0
0x0
Access
R
R
0x0
0x0
0x0
0x0
R
R
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R
R
0x0
AD9144
Data Sheet
Address
0x40C
Name
RES2_REG
Bit No.
[7:0]
Bit Name
RES2_RD
0x40D
CHECKSUM_REG
[7:0]
FCHK0_RD
0x40E
COMPSUM0_REG
[7:0]
FCMP0_RD
0x412
LID1_REG
[7:5]
[4:0]
RESERVED
LID1_RD
0x415
CHECKSUM1_REG
[7:0]
FCHK1_RD
0x416
COMPSUM1_REG
[7:0]
FCMP1_RD
0x41A
LID2_REG
0x41D
0x41E
CHECKSUM2_REG
COMPSUM2_REG
[7:5]
[4:0]
[7:0]
[7:0]
RESERVED
LID2_RD
FCHK2_RD
FCMP2_RD
0x422
LID3_REG
0x425
0x426
CHECKSUM3_REG
COMPSUM3_REG
[7:5]
[4:0]
[7:0]
[7:0]
RESERVED
LID3_RD
FCHK3_RD
FCMP3_RD
0x42A
LID4_REG
0x42D
0x42E
CHECKSUM4_REG
COMPSUM4_REG
[7:5]
[4:0]
[7:0]
[7:0]
RESERVED
LID4_RD
FCHK4_RD
FCMP4_RD
0x432
LID5_REG
0x435
0x436
CHECKSUM5_REG
COMPSUM5_REG
[7:5]
[4:0]
[7:0]
[7:0]
RESERVED
LID5_RD
FCHK5_RD
FCMP5_RD
0x43A
LID6_REG
0x43D
0x43E
CHECKSUM6_REG
COMPSUM6_REG
[7:5]
[4:0]
[7:0]
[7:0]
RESERVED
LID6_RD
FCHK6_RD
FCMP6_RD
0x442
LID7_REG
0x445
0x446
CHECKSUM7_REG
COMPSUM7_REG
[7:5]
[4:0]
[7:0]
[7:0]
RESERVED
LID7_RD
FCHK7_RD
FCMP7_RD
0x450
ILS_DID
[7:0]
DID
Settings
Description
Reserved Field 2. Link information received on
Link Lane 0 as specified in Section 8.3 of
JESD204B.
Checksum for Link Lane 0. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B.
Computed Checksum for Link Lane 0. The
JESD204B receiver computes the checksum
of the link information received on Lane 0 as
specified in Section 8.3 of JESD204B. The
computation method is set by the
CHECKSUM_MODE bit (Address 0x300[6])
and must match the likewise calculated
checksum in Register 0x40D.
Reserved.
Lane Identification for Link Lane 1.Link
information received on Lane 0 as specified
in section 8.3 of JESD204B.
Checksum for Link Lane 1. Link information
received on Lane 0 as specified in Section 8.3
of JESD204B.
Computed Checksum for Link Lane 1. See the
description for Register 0x40E.
Reserved.
Lane Identification for Link Lane 2.
Checksum for Link Lane 2.
Computed Checksum for Link Lane 2 (see the
description for Register 0x40E).
Reserved.
Lane Identification for Link Lane 3.
Checksum for Link Lane 3.
Computed Checksum for Link Lane 3 (see the
description for Register 0x40E).
Reserved.
Lane Identification for Link Lane 4.
Checksum for Link Lane 4.
Computed Checksum for Link Lane 4 (see the
description for Register 0x40E).
Reserved.
Lane Identification for Link Lane 5.
Checksum for Link Lane 5.
Computed Checksum for Link Lane 5 (see the
description for Register 0x40E).
Reserved.
Lane Identification for Link Lane 6.
Checksum for Link Lane 6.
Computed Checksum for Link Lane 6 (see the
description for Register 0x40E).
Reserved.
Lane Identification for Link Lane 7.
Checksum for Link Lane 7.
Computed Checksum for Link Lane 7 (see the
description for Register 0x40E).
Device Identification Number. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B. Must be set to value
read in Register 0x400.
Reset
0x0
Access
R
0x0
0x0
0x0
0x0
R
R
0x0
0x0
0x0
0x0
0x0
0x0
R
R
R
R
0x0
0x0
0x0
0x0
R
R
R
R
0x0
0x0
0x0
0x0
R
R
R
R
0x0
0x0
0x0
0x0
R
R
R
R
0x0
0x0
0x0
0x0
R
R
R
R
0x0
0x0
0x0
0x0
R
R
R
R
0x0
R/W
Data Sheet
Address
0x451
0x452
0x453
Name
ILS_BID
ILS_LID0
ILS_SCR_L
AD9144
Bit No.
[7:4]
Bit Name
ADJCNT
[3:0]
BID
7
6
5
RESERVED
ADJDIR
PHADJ
[4:0]
LID0
SCR
Settings
0
1
[6:5]
[4:0]
RESERVED
L-1
0
1
3
7
0x454
ILS_F
[7:0]
F-1
0
1
3
0x455
ILS_K
[7:5]
[4:0]
RESERVED
K-1
0x0F
0x1F
0x456
ILS_M
[7:0]
M-1
0
1
3
0x457
ILS_CS_N
[7:6]
CS
5
[4:0]
RESERVED
N-1
[7:5]
SUBCLASSV
0xF
0x458
ILS_NP
0
1
[4:0]
NP-1
[7:5]
JESDV
0xF
0x459
ILS_S
000
001
[4:0]
S-1
0
1
Description
Adjustment Resolution to DAC LMFC Must
be set to 0.
Bank Identification: Extension to DID Must be
set to value read in Register 0x401[3:0].
Reserved.
Direction to Adjust DAC LMFC. Must be set to 0.
Phase Adjustment Request to DAC. Must be
set to 0.
Lane Identification for Link Lane 0. Must be set
to the value read in Register 0x402[4:0].
Receiver Descrambling Enable.
Descrambling is disabled
Descrambling is enabled
Reserved.
Number of Lanes per Converter Device. See
Table 35 and Table 36.
One lane per converter
Two lanes per converter
Four lanes per converter
Eight lanes per converter (single link only)
Number of Octets per Lane per Frame. Settings
of 1, 2, and 4 (octets per lane) per frame are
valid. See Table 35 and Table 36.
(One octet per lane) per frame
(Two octets per lane) per frame
(Four octets per lane) per frame
Reserved.
Number of Frames per Multiframe. Settings
of 16 or 32 are valid. Must be set to 32 when
F = 1 (Register 0x476).
16 frames per multiframe
32 frames per multiframe
Number of Converters per Device. See Table 35
and Table 36.
One converter per link
Two converters per link
Four converters per link (single link only)
Number of Control Bits per Sample. Must be
set to 0. Control bits are not supported.
Zero control bits per sample
Reserved.
Converter Resolution. Must be set to 16 bits
of resolution.
Converter resolution of 16.
Device Subclass Version.
Subclass 0
Subclass 1
Total Number of Bits per Sample. Must be set
to 16 bits per sample.
16 bits per sample.
JESD204 Version.
JESD204A
JESD204B
Number of Samples per Converter per Frame
Cycle. Settings of one and two are valid. See
Table 35 and Table 36.
One sample per converter per frame
Two samples per converter per frame
Reset
0x0
Access
R/W
0x0
R/W
0x0
0x0
0x0
R
R/W
R/W
0x0
R/W
0x1
R/W
0x0
0x3
R
R/W
0x0
R/W
0x0
0x1F
R
R/W
0x1
R/W
0x0
R/W
0x0
0xF
R
R/W
0x1
R/W
0xF
R/W
0x1
R/W
0x0
R/W
AD9144
Address
0x45A
Name
ILS_HD_CF
Data Sheet
Bit No.
7
Bit Name
HD
Settings
0
1
[6:5]
[4:0]
RESERVED
CF
0x45B
0x45C
0x45D
ILS_RES1
ILS_RES2
ILS_CHECKSUM
[7:0]
[7:0]
[7:0]
RES1
RES2
FCHK0
0x46B
ERRCNTRMON_RB
[7:0]
READERRORCNTR
0x46B
ERRCNTRMON
7
[6:4]
RESERVED
LANESEL
[3:2]
[1:0]
RESERVED
CNTRSEL
00
01
10
0x46C
0x46D
LANEDESKEW
BADDISPARITY_RB
[7:0]
[7:0]
LANEDESKEW
BADDIS
0x46D
BADDISPARITY
RST_IRQ_DIS
DISABLE_ERR_
CNTR_DIS
RST_ERR_CNTR_DIS
[4:3]
[2:0]
RESERVED
LANE_ADDR_DIS
0x46E
NIT_RB
[7:0]
NIT
0x46E
NIT_W
RST_IRQ_NIT
DISABLE_ERR_
CNTR_NIT
RST_ERR_CNTR_NIT
[4:3]
[2:0]
RESERVED
LANE_ADDR_NIT
Description
High Density Format. If F = 1, HD must be set
to 1. Otherwise, HD must be set to 0. See
Section 5.1.3 of JESD204B standard.
Low density mode
High density mode
Reserved.
Number of Control Words per Frame Clock
Period per Link. Must be set to 0. Control bits
are not supported.
Reserved Field 1.
Reserved Field 2.
Checksum for Link Lane 0. Calculated
checksum. Calculation depends on 0x300[6].
Read JESD204B Error Counter. After selecting
the lane and error counter by writing to
LANESEL and CNTRSEL (both in this same
register), the selected error counter is read
back here.
Reserved.
Link Lane select for JESD204B error counter.
Selects the lane whose errors are read back
in this register.
Selects Link Lane x
Reserved.
JESD204B Error Counter Select. Selects the
type of error that are read back in this
register.
BADDISCNTR: bad running disparity counter
NITCNTR: not in table error counter
UCCCNTR: Unexpected control character counter
Lane Deskew. Setting Bit x deskews Link Lane x
Bad Disparity Character Error (BADDIS). Bit x
is set when the bad disparity error count for
Link Lane x reaches the threshold in
Register 0x47C.
BADDIS IRQ Reset. Reset BADDIS IRQ for lane
selected via Bits[2:0] by writing 1 to this bit.
BADDIS Error Counter Disable. Disable the
BADDIS error counter for lane selected via
Bits[2:0] by writing 1 to this bit.
BADDIS Error Counter Reset. Reset BADDIS
error counter for lane selected via Bits[2:0] by
writing 1 to this bit.
Reserved.
Link Lane Address for Functions Described in
Bits[7:5].
Not in table Character Error (NIT). Bit x is set
when the NIT error count for Link Lane x
reaches the threshold in Register 0x47C.
IRQ Reset. Reset IRQ for lane selected via
Bits[2:0] by writing 1 to this bit.
Disable Error Counter. Disable the error
counter for lane selected via Bits[2:0] by
writing 1 to this bit.
Reset Error Counter. Reset error counter for lane
selected via Bits[2:0] by writing 1 to this bit.
Reserved.
Link Lane Address for Functions Described in
Bits[7:5].
Reset
0x1
Access
R/W
0x0
0x0
R
R/W
0x0
0x0
0x45
R/W
R/W
R/W
0x0
0x0
0x0
R
W
0x0
0x0
R
W
0xF
0x0
R/W
R
0x0
0x0
0x0
0x0
0x0
R
W
0x0
0x0
0x0
0x0
0x0
0x0
R
W
Data Sheet
AD9144
Address
0x46F
Name
UNEXPECTEDCONTROL_RB
Bit No.
[7:0]
Bit Name
UCC
0x46F
UNEXPECTEDCONTROL_W
RST_IRQ_UCC
DISABLE_ERR_
CNTR_UCC
5
[4:3]
[2:0]
RST_ERR_CNTR_
UCC
RESERVED
LANE_ADDR_UCC
[7:0]
CODEGRPSYNC
0x470
CODEGRPSYNCFLG
Settings
0
1
0x471
FRAMESYNCFLG
[7:0]
FRAMESYNC
0
1
0x472
GOODCHKSUMFLG
[7:0]
GOODCHECKSUM
0
1
0x473
INITLANESYNCFLG
[7:0]
INITIALLANESYNC
0x476
CTRLREG1
[7:0]
F
1
2
4
0x477
CTRLREG2
ILAS_MODE
1
0
[6:4]
3
0x478
KVAL
[2:0]
[7:0]
RESERVED
THRESHOLD_
MASK_EN
RESERVED
KSYNC
Description
Unexpected Control Character Error (UCC).
Bit x is set when the UCC error count for Link
Lane x reaches the threshold in Register 0x47C.
IRQ Reset. Reset IRQ for lane selected via
Bits[2:0] by writing 1 to this bit.
Disable Error Counter. Disable the error
counter for lane selected via Bits[2:0] by
writing 1 to this bit.
Reset Error Counter. Reset error counter for
lane selected via Bits[2:0] by writing 1 to this bit.
Reserved.
Link Lane Address for Functions Described in
Bits[7:5].
Code Group Sync Flag (from Each
Instantiated Lane). Writing 1 to Bit 7 resets
the IRQ. The associated IRQ flag is located in
Register 0x47A[0]. A loss of CODEGRPSYNC
triggers sync request assertion. See the
SYNCOUT and SYSREF Signals section and
the Deterministic Latency section.
Synchronization is lost
Synchronization is achieved
Frame Sync Flag (from Each Instantiated
Lane). This register indicates the live status
for each lane. Writing 1 to Bit 7 resets the
IRQ. A loss of frame sync automatically
initiates a synchronization sequence.
Synchronization is lost
Synchronization is achieved
Good Checksum Flag (from Each Instantiated
Lane). Writing 1 to Bit 7 resets the IRQ. The
associated IRQ flag is located in
Register 0x47A[2].
Last computed checksum is not correct
Last computed checksum is correct
Initial Lane Sync Flag (from Each Instantiated
Lane). Writing 1 to Bit 7 resets the IRQ. The
associated IRQ flag is located in Register
0x47A[3]. Loss of synchronization is also
reported on SYNCOUT1 or SYNCOUT0. See
the SYNCOUT and SYSREF Signal section
and the Deterministic Latency section.
Number of Octets per Frame. Settings of 1, 2,
and 4 are valid. See Table 35 and Table 36.
One octet per frame
Two octets per frame
Four octets per frame
ILAS Test Mode. Defined in Section 5.3.3.8 of
JESD204B specification.
JESD204B receiver is constantly receiving
ILAS frames
Normal link operation
Reserved.
Threshold Mask Enable. Set this bit if using
SYNC_ASSERTION_MASK (Register 0x47B[7:5]).
Reserved.
Number of K Multiframes During ILAS
(Divided by Four). Sets the number of
multiframes to send initial lane alignment
sequence. Cannot be set to 0.
4x multiframes during ILAS
Reset
0x0
Access
R
0x0
0x0
0x0
0x0
0x0
R
W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x0
R/W
0x0
0x0
R
R/W
0x0
0x1
R
R/W
AD9144
Address
0x47A
Name
IRQVECTOR_MASK
Data Sheet
Bit No.
7
Bit Name
BADDIS_MASK
Settings
1
NIT_MASK
1
UCC_MASK
1
4
3
0x47A
IRQVECTOR_FLAG
RESERVED
INITIALLANESYNC_
MASK
BADCHECKSUM_
MASK
FRAMESYNC_
MASK
CODEGRPSYNC_
MASK
BADDIS_FLAG
1
NIT_FLAG
1
UCC_FLAG
1
4
3
RESERVED
INITIALLANESYNC_
FLAG
BADCHECKSUM_
FLAG
FRAMESYNC_
FLAG
CODEGRPSYNC_
FLAG
Description
Bad Disparity Mask.
If the bad disparity count reaches
ERRORTHRESH on any lane, IRQ is pulled low.
Not in table Mask.
If the not in table character count reaches
ERRORTHRESH on any lane, IRQ is pulled low.
Unexpected Control Character Mask.
If the unexpected control character count
reaches ERRORTHRESH on any lane, IRQ is
pulled low.
Reserved.
Initial Lane Sync Mask.
If initial lane sync (0x473) fails on any lane,
IRQ is pulled low.
Bad Checksum Mask.
If there is a bad checksum (0x472) on any
lane, IRQ is pulled low.
Frame Sync Mask
If frame sync (0x471) fails on any lane, IRQ is
pulled low.
Code Group Sync Machine Mask.
If code group sync (0x470) fails on any lane,
IRQ is pulled low.
Bad Disparity Error Count.
Bad disparity character count reached
ERRORTHRESH (0x47C) on at least one lane.
Read Register 0x46D to determine which
lanes are in error.
Not in table Error Count
Not in table character count reached
ERRORTHRESH (0x47C) on at least one lane.
Read Register 0x46E to determine which
lanes are in error.
Unexpected Control Character Error Count
Unexpected control character count reached
ERRORTHRESH (0x47C) on at least one lane.
Read Register 0x46F to determine which
lanes are in error.
Reserved.
Initial Lane Sync Flag.
Initial lane sync failed on at least one lane.
Read Register 0x473 to determine which
lanes are in error
Bad Checksum Flag.
Bad checksum on at least one lane. Read
Register 0x472 to determine which lanes are in
error.
Frame Sync Flag.
Frame sync failed on at least one lane. Read
Register 0x471 to determine which lanes are
in error.
Code Group Sync Flag.
Code group sync failed on at least one lane.
Read Register 0x470 to determine which
lanes are in error
Reset
0x0
Access
W
0x0
0x0
0x0
0x0
R
W
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R
R
0x0
0x0
0x0
Data Sheet
Address
0x47B
Name
SYNCASSERTIONMASK
AD9144
Bit No.
7
Bit Name
BADDIS_S
Settings
1
NIT_S
1
UCC_S
1
CMM
CMM_ENABLE
1
0
0x47C
ERRORTHRES
[2:0]
[7:0]
RESERVED
ETH
0x47D
LANEENABLE
[7:0]
LANE_ENA
0x47E
RAMP_ENA
[7:1]
0
RESERVED
ENA_RAMP_
CHECK
0
1
0x520
DIG_TEST0
[7:2]
RESERVED
0x521
DC_TEST_VALUEI0
1
0
[7:0]
0x522
DC_TEST_VALUEI1
[7:0]
0x523
DC_TEST_VALUEQ0
[7:0]
0x524
DC_TEST_VALUEQ1
[7:0]
DC_TEST_MODE
RESERVED
DC_TEST_
VALUEI[7:0]
DC_TEST_
VALUEI [15:8]
DC_TEST_
VALUEQ[7:0]
DC_TEST_
VALUEQ[15:8]
Description
Bad Disparity Error on Sync.
Asserts a sync request on SYNCOUTx when
the bad disparity character count reaches the
threshold in Register 0x47C
Not in table Error on Sync.
Asserts a sync request on SYNCOUTx when
the not in table character count reaches the
threshold in Register 0x47C
Unexpected Control Character Error on Sync.
Asserts a sync request on SYNCOUTx when
the unexpected control character count
reaches the threshold in Register 0x47C
Configuration Mismatch IRQ. If
CMM_ENABLE is high, this bit latches on a
rising edge and pull IRQ low. When latched,
write a 1 to clear this bit. If CMM_ENABLE is
low, this bit is non-functional.
Link Lane 0 configuration registers (Register
0x450 to Register 0x45D) do not match the
JESD204B transmit settings (Register 0x400
to Register 0x40D)
Configuration Mismatch IRQ Enable.
Enables IRQ generation if a configuration
mismatch is detected
Configuration mismatch IRQ disabled
Reserved.
Error Threshold. Bad disparity, not in table,
and unexpected control character errors are
counted and compared to the error
threshold value. When the count reaches the
threshold, either an IRQ is generated or the
SYNCOUTx signal is asserted per the mask
register settings, or both. Function is
performed in all lanes.
Lane Enable. Setting Bit x enables Link Lane x.
This register must be programmed before
receiving the code group pattern for proper
operation.
Reserved.
Enable Ramp Checking at the Beginning of
ILAS.
Disable ramp checking at beginning of ILAS;
ILAS data need not be a ramp
Enable ramp checking; ILAS data needs to be
a ramp starting at 00-01-02; otherwise, the
ramp ILAS fails and the device does not start up
Must write default value for proper
operation.
DC Test Mode
Reserved.
DC Value LSB of DC Test Mode for I DAC.
Reset
0x0
Access
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x0
0xFF
R
R/W
0xF
R/W
0x0
0x0
R
W
0x7
R/W
0x0
0x0
0x0
R/W
R/W
R/W
0x0
R/W
0x0
R/W
0x0
R/W
AD9144
Data Sheet
OUTLINE DIMENSIONS
12.10
12.00 SQ
11.90
0.28
0.23
0.18
0.60 MAX
0.60
MAX
67
66
88
PIN 1
INDICATOR
1
PIN 1
INDICATOR
11.85
11.75 SQ
11.65
0.50
BSC
0.50
0.40
0.30
22
23
45
44
TOP VIEW
BOTTOM VIEW
10.50
REF
0.70
0.65
0.60
0.045
0.025
0.005
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
08-10-2012-A
12 MAX
0.90
0.85
0.80
7.55
7.40 SQ
7.25
EXPOSED PAD
12.10
12.00 SQ
11.90
0.30
0.25
0.20
0.60 MAX
0.60
MAX
67
88
66
PIN 1
INDICATOR
PIN 1
INDICATOR
0.50
BSC
7.55
7.40 SQ
5.25
EXPOSED
PAD
0.65
0.55
0.45
22
44
TOP VIEW
0.90
0.85
0.80
PKG-004598
SEATING
PLANE
0.70
0.65
0.60
12 MAX
0.190~0.245 REF
0.50
0.40
0.30
45
0.045
0.025
0.005
COPLANARITY
0.08
23
BOTTOM VIEW
10.50
REF
Figure 89. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] (Variable Lead Length)
12 mm 12 mm Body, Very Thin Quad
(CP-88-9)
Dimensions shown in millimeters
1.00
0.90
0.80
0.80
0.70
0.60
08-04-2014-A
11.85
11.75 SQ
11.65
Data Sheet
AD9144
ORDERING GUIDE
Model1
AD9144BCPZ
AD9144BCPZRL
AD9144BCPAZ
AD9144BCPAZRL
AD9144-EBZ
AD9144-FMC-EBZ
AD9144-M6720-EBZ
1
Temperature Range
40C to +85C
40C to +85C
40C to +85C
40C to +85C
Package Description
88-Lead LFCSP_VQ
88-Lead LFCSP_VQ
88-Lead LFCSP_VQ (Variable Lead Length)
88-Lead LFCSP_VQ (Variable Lead Length)
DPG3 Evaluation Board
FMC Evaluation Board
DPG3 Evaluation Board with ADRF6720 Modulator
Package Option
CP-88-6
CP-88-6
CP-88-9
CP-88-9