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Hugo Ribeiro1,3
Andr Pinto1,2
Beatriz Borges1,2
Senior Member
Instituto de Telecomunicaes, 2Instituto Superior Tcnico, Av. Rovisco Pais, 1049-001 Lisboa, Portugal
3
Instituto Politcnico de Tomar, Escola Superior de Tecnologia, Estrada da Serra, 2300 Tomar, Portugal
hugo@ipt.pt, bborges@lx.it.pt, coelho_pinto@hotmail.com
I.
INTRODUCTION
II.
604
VCP VCF
State S11
diLP LP
=
dt
VCP
States S10 , S01 , S00
LP
+ VCF vR
LR
diLR VCF vR
=
dt
LR
vR
LR
State S10
State S01
State S00
or
(1)
S11
(2)
(a)
(b)
Fig.3. Proposed circuit operating modes considering the different states: (a)
boost modes; (b) bridge modes.
T2 / T4
vAB
States
di LP
dt
di LR
; vR > 0
dt
di LR
;vR < 0
dt
on/off
on/off
off/on
off/on
on/off
off/on
off/on
on/off
0
+VCF
0
-VCF
S00
S01
S11
S10
>0
>0
<0
>0
<0
>0
<0
<0
>0
>0
>0
<0
Fig.4. Voltage vAB and current iLR time diagrams for the different transistor
states evidencing the iLP control time intervals.
605
vR<0
0
0
0
0
TABLE II
CONTROL POWER TRANSISTORS SWITCHING STATES
State Control action T1 T2 T3
Variables states
iLP K I < iLPREF 2
S00
1 1 0
0 0
iLP iLR
iLR K I < iLREF 1
iLP K I < iLPREF 2
iLP iLR
S01
0 1
1 0 0
iLR K I > iLREF + 1
iLP K I > i LPREF + 2
iLP iLR
0 0 1
S11
1 0
iLR K I < i LREF 1
iLP K I > i LPREF + 2
iLP iLR
1 1
S01
1 0 0
iLR K I > i LREF + 1
1 0 0
vR>0
1 0 1
1 1 0
1 1 1
T4
0
1
1
1
S10
iLP iLR
0 1 1 0
S00
iLP iLR
1 1 0 0
S10
iLP iLR
0 1 1 0
S11
iLP iLR
0 0 1 1
There are two vectors, (0,1,1) and (1,1,0) (marked with gray
in the table) where is impossible to obtain the ideal transistor
gate vector, which means that it is only possible to control
one of the two variables. For these vectors, it was adopted to
control iLR instead the iLP to avoid perturbations on the grid
current which results in a significant harmonic distortion
increase. In the other hand, as will be demonstrated further,
the iLP perturbations are very small and do not compromise
the converter operation.
The design of the linear control for the VCF voltage is based
in the average model, presented in Fig.7. In the model the
100Hz voltage ripple is not considered because the controller
is designed to present a reduced gain at 100Hz, < -30db.
i LR K I > i LREF + 1 = 1
i LR K I < i LREF 1 = 0
i LP K I > i LPREF + 2 = 1
i LP K I < i LPREF 2 = 0
vR > 0 = 1
vR < 0 = 0
(3)
(4)
I FB VCF =
VI I LR
V I
I FB = I LREF vCTR
2
2 K VCF
I
(6)
KG
(5)
606
VCP
ILP
VCF
(7)
v AB = VCF DFB
VCF =
VCP
1 DB
(8)
(9)
VCP max
1 DB min
(10)
(11)
(12)
PO max
2 VCF VCF f R
(13)
b)
Fig.9. (a) Open loop gain and phase of the VCF voltage controller; (b)
dynamic response for a boost power variation of 30W to 150W and vice
versa.
607
t P max =
VCF VR max
(18)
i LR =
VCF VR
V
t1 = R t 2
LR
LR
(14)
i LP =
V VP
VP
t1 = CF
t2
LP
LP
(15)
i LPP =
VP
VP i LR LR
t P max i LPP =
LP
LP (VCF VR max )
(19)
D ) Design of LP and LR
1
1
TSR = iLR LR
+
VCF VR VR
iLR LR
f SR =
1
1
TSP = iLP LP
+
VCF VP VP
f SP =
1
TSR
(16)
1
TSP
(17)
(12)
608
iLP
iLR
a)
a)
vgrid
b)
b)
vCF
iLR
c)
c)
Fig.12. Experimental results: a) iLR (blue trace) with a gain of 1A/div, iLP
(green trace) with a gain of 1A/div; b) grid voltage (magenta trace) with a
gain of 50 V/div; c) vCF voltage (red trace) with a gain of 100V/div and iLR
(blue trace) with a gain of 1A/div.
VI. ACKNOWLEDGMENT
This work was supported in part by Instituto de
Telecomunicaes and by the Fundao para a Cincia e para
a Tecnologia, FCT, under the Grant SFRH/BD/40220/2007.
VII.
CONCLUSIONS
Fig.13. Simulation results: a) iLR (blue trace) with a gain of 1A/div, iLP (green
trace) with a gain of 1A/div; b) Obsetvation of iLP perturbations; c)
verification of the maximum iLR switching frequency value, fSRmax.
609
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
REFERENCES
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