Académique Documents
Professionnel Documents
Culture Documents
Aamodh K (15VL01f )
Arjun S Kumar (15VL04f )
Vikas Bhardwaj (15VL26f )
I Semester M.Tech VLSI Design
As part of
VL720: Digital IC Design
Abstract
The objective of this project is to design and implement 16 bit SRAM with supply
voltage of 3.3V. The total number of address lines needed for accessing 16 locations is
four. 6T (6 transistors) cell is used to store one bit data. The design blocks required
are Precharge circuit, Sense amplier, 2x4 Decoders, Write enable circuit and CMOS
SRAM cell.
Post layout simulations are performed and the outputs are analysed for correct functionality using open source tools - Magic, NG Spice, IRSIM, Electronics Workbench
and Netgen. Characterization of the SRAM cell is done in term of read 0, read 1,
write0 and write 1 delays, power dissipation and Area.
Contents
1
Introduction
Design
2.4 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
11
12
12
13
13
14
14
15
15
Observations
17
REFERENCES
19
List of Figures
1
10
Precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
12
10
13
11
13
12
14
13
14
14
15
15
16
16
17
17
17
. . . . . . . . . . . . . . . .
List of Tables
1
10
18
18
Introduction
Design
The transistor M3 is in saturation whereas M1 is linear , equating the current equations we get
N 3
2
(VDD V1 VT N ) = N2 1 2 (V DD VT N ) V1 V12
2
> 4.051
(0 VDD VT P ) = N2 3 2 (V DD VT N ) V1 V12
2
and V1max VT 2
In level 49 NG Spice model le, oxide thickness of both PMOS and NMOS is equal.
Substituting V T P = 0.411V , V T N = 0.3121V (as in level 49 NG Spice model le)
and V DD = 3.3V we get
(W/L)5
(W/L)3
< 0.4814
Ratio = 4.2
and Pullup
Ratio = 0.4
which
2.4 Decoder
Table 2:
A2
0
0
1
1
In decoder circuit of Figure 6, A2 and A1 are the inputs to the decoder and R4,
R3, R2 and R1 are the outputs out of the decoder. It's truth table is shown in
Table 2.
The purpose of the decoder is to select a single SRAM cell among the array of
16 SRAM cells.
decoder.
Active high decoder is used because the pass transistors within SRAM cell are
NMOS.
The purpose of sense amplier is to increase logic detection speed during read
operation.
10
11
Vdd
Vdd
presel
Q97
presel
Q100
Q98
Q104
presel
Q106
Q105
Q102
Q99
Vdd
presel
Q103
Q101
Q107
Q108
Vdd
Q109
B0
Vdd
Q110
Q111
Q169
Q8
Q5
Q14
Q10
Q11
Q6
Q7
Vdd
Q16
Q20
Q17
Q12
Q3
Q1
Vdd
Vdd
Q4
Q2
Q18
Q13
Q9
Q22
Q23
Q24
Q15
Q19
Q21
Vdd
B1
Q112
Vdd
Q113
Vdd
Vdd
Q170
Q114
Q26
Q28
Q32
Q38
Q34
Vdd
Q40
Q44
Q46
Vdd
Q29
Q30
Q35
Q41
Q36
Q42
Q115
Q25
Q27
Q31
Q37
Q33
Q47
Q48
Q39
Q43
Q45
B2
Q171
Q116
Q117
Vdd
Q50
Vdd
Vdd
Q52
Q56
Q62
Q58
Vdd
Q64
Q68
Q70
Vdd
Q53
Q118
Q54
B3
Q120
Q119
Q49
Q59
Q65
Q60
Q51
Q55
Q66
Q61
Q57
Q71
Q72
Q63
Q67
Q69
Q172
Vdd
U2
U1
Q74
Q80
Q77
Q78
A0 dec_dsbl
A1
Q73
Q86
Q82
Q83
Q79
Q131
Q130
Vdd
Q149
Q151
Vdd
Q141
Q148
Q143
SE
Q175
Q135
Q150
Q152
SE
Q174
Q126
Q93
Vdd
Q139
Q132
SE
Q173
Q91
Q142
Q134
SE
Q96
Q87
Vdd
Q123
Q94
Q95
Vdd
Q140
Q133
Q125
writebar
Q85
Q81
Vdd
Q121
Q92
Q90
Vdd
Q124
Vdd
Q88
Q89
Q84
Q75
Vdd
Q122
Vdd
Vdd
Q76
Q144
Q176
Q153
U5
Q127
Vdd
Q136
Q145
Q154
U6
Q157
Data
Q128
Q158
Q137
Q146
Q155
Q159
D0
Vdd
Q129
Q138
Q147
Q156
Q160
Q161
D1
Q162
Vdd
Q163
Q164
Q165
D2
Vdd
Q166
D3
Q168
Q167
U3
C1
U4
C0
12
13
14
15
Figure 15: Layout of 16 bit SRAM array along with peripheral circuits
16
Observations
17
Table 4 is a tabulation of our observations of power dissipation during various operations in SRAM cell for a supply voltage of 3.3V in NG Spice.
Table 4: Power dissipation during Read, Write and Hold operations
State
Power dissipation type Current Maximum instantaneous Power
Hold
Static
10 uA
33 uW
Read/Write
Dynamic
300 uA
990 uW
The area occupied by single SRAM cell shown in Figure 10 is 62 x 57 2 .
The area occupied by the entire circuit shown in Figure 15 is 443 x 565 2 , where
is the size of the grid in Magic.
18
REFERENCES
[1] S.M. Kang and Y. Leblebici, CMOS Integrated Circuits Analysis and Design, 2nd
Edition, McGraw Hill, 2003.
[2] J.M. Rabaey, A. Chandrakasan and B. Nikolic, Digital
Design Perspective, 2nd Edition, Pearson Education, 2003.
Integrated Circuits - A
19