FD-SOI

Sphere: Technologies | back-bias, bonded wafer, FD-SOI, multi-Vt design, partially depleted
SOI, Soitec, ST-Ericsson

What is FD-SOI and why is it useful?

Fully depleted silicon-on-insulator (FD-SOI), also known as ultra-thin or extremely
thin silicon-on-insulator (ET-SOI), is an alternative to bulk silicon as a substrate for
building CMOS devices. SOI wafers have a shallow layer of epitaxial silicon grown on
top of an oxide layer that acts as an insulator. The top silicon layer is fully depleted,
that is, it doesnt have any intrinsic charge carriers, which has a number of
advantages when building deep submicron devices.
Transistors built on FD-SOI have a very thin (shallow) channel, which improves the
gates ability to remove carriers from that channel when the device needs to be
switched Off. In principle, FD-SOI offers better performance than conventional bulk
silicon on deep submicron process technologies, with particular benefits for lowpower circuits. Proponents of FD-SOI argue that, although the resultant devices
current drive is poorer than in bulk processes, the drain-induced barrier lowering
(DIBL) that plagues deep submicron processes by making it more difficult to turn
devices Off is greatly reduced by the presence of the insulating oxide layer directly
beneath the channel.
According to the SOI Industry Consortium, benchmarks show that using FD-SOI
makes it possible to reduce the operating voltage in SRAM cells by 100-150mV.
Cutting the voltage in regular CMOS has proved difficult because of concerns over
variability, as it slashes the static noise margin and so increases the probability of
errors in the memory array. The Consortium claims that the operating-voltage
reduction afforded by FD-SOI enables a 40 per cent reduction in memory-array
power consumption.
Another potential advantage of FD-SOI over the finFET, its nearest competitor for
sub-28nm processes, is that the approach makes it possible to back-bias the
channel and so gain greater control over the charge carriers flowing through it.
What effect does FD-SOI have on design?
The use of a very thin channel deals with one of the main design problems of
previous, partially depleted SOI implementations that used thicker silicon channels.
This is the tendency for electrical charge to remain under the gate once a transistor
has been turned Off. This history effect complicates design because circuits need
to take account of the possible changes in voltage that the effect causes. FD-SOI
transistors do not, in general, exhibit this behavior.

In principle, it is possible to directly port a cell library from a bulk process on to an

FD-SOI process. However, the results will not be as good as dedicated cell libraries
designed to take advantage of the different balance of capacitances in FD-SOI
devices and the reduced variability of undoped channels, which should improve
static noise margin in SRAMs. Subthreshold leakage should be greatly reduced with
FD-SOI and the SOI Consortium claims that criteria important to analog design, such
as transconductance, also benefit from undoped channels.
The SOI Consortium has proposed that a safe way to adopt FD-SOI is to start by
using hybrid FD-SOI/bulk co-integration. In this approach, IP cores that are deemed
too risky to redesign are placed on to areas of the wafer that expose the bulk
silicon, while synthesized logic optimized to use FD-SOI structures and design rules
is placed on to areas of the wafer that expose FD-SOI.
Basic models are available for simulating FD-SOI designs in Spice although more
advanced models that take into account surface effects are still in development,
with industrialization expected in the near future.
The biggest impact on design will come from a proposed advantage of FD-SOI: the
ability to dynamically back-bias the channel, which gives better control and so
improves device switching speed. One advantage of using back-bias in FD-SOI is
that its effect does not diminish with decreasing device size in the way that it does
for bulk silicon.
Multi-Vt circuitry is more complicated to implement on FD-SOI than with bulk silicon
processes because channel doping cannot be used to alter the threshold voltage.
Instead, the threshold voltage is controlled by tuning the gate stack materials.
However, a combination of doping and active biasing can be used to alter the
threshold of a target group of transistors that have a common sub-oxide backplane.
The contacts and implant regions for these groups have to be defined at design
time. One further possibility is to use channel-length modulation, similar to that
used in bulk processes to reduce leakage in slower transistors. However, the Vt
rolloff is less pronounced in FD-SOI than with comparable bulk-silicon devices.
One potential issue with designing for FD-SOI is that of self-heating, similar to that
encountered with finFETs, because the ultra-thin narrow channel lies on top of a
poor thermal conductor. However, this is not expected to affect low-power circuits,
which remain the primary target for proponents of FD-SOI-based designs.
When and where can I use FD-SOI?
Following a deal between GlobalFoundries and STMicroelectronics, which said at the
beginning of 2012 it would buy suitable wafers from bonded-wafer specialist Soitec
for 28nm FD-SOI mobile-phone devices, foundry users will be able to access the
technology at GlobalFoundries fabs from 2013. ST will run its own devices either at

its relatively small Crolles plant, where its FD-SOI process was developed, or at the
GlobalFoundries 28nm and 20nm-capable fabs.
What are the risks and downsides of FD-SOI?
The primary problems with FD-SOI lie in the supply chain. Although it is possible to
create the oxide layers on bulk silicon wafers and then use epitaxy to define silicon
channels on the surface, the surface quality needed for nanometer processes is best
supported through the use of specialized, bonded SOI wafers. As with any nonmainstream process, these wafers are more expensive although some cost savings
could be achieved through simpler processing at the transistor-building stage. For
example, the channel does not need to be doped, which causes fewer problems
with variability and, therefore, device yield.
Although basic models are available and research efforts have generated
increasingly accurate device-level models, some of the effects seen in nanometrescale FD-SOI devices are not yet taken into account in industrial-grade models.

Double patterning for sub-28nm ICs

Sphere: Technologies | double patterning, lithography
What is it?
Double patterning is a technique used in the lithographic process that defines the
features of integrated circuits at advanced process nodes. It will enable designers to
develop chips for manufacture on sub-30nm process nodes using current optical
lithography systems. The alternative is to wait for the development of commercially
viable steppers using extreme ultraviolet illumination sources, masks and stepper
technologies.
The downsides of using double patterning include increased mask (reticle) and
lithography costs, and the imposition of further restrictions on the ways in which
circuits can be laid out on chip. This affects the complexity of the design process
and the performance, variability and density of the resultant devices.
What does double patterning do and why do we need it?
Double patterning counters the effects of diffraction in optical lithography, which
happens because the minimum dimensions of advanced process nodes are a
fraction of the 193nm wavelength of the illuminating light source. These diffraction
effects makes it difficult to produce accurately defined deep sub-micron patterns
using existing lighting sources and conventional masks: sharp corners and edges

become blurs, and some small features on the mask wont appear on the wafer at
all.
A number of reticle enhancement techniques have been introduced to counteract
the diffraction problem as it has become more acute with each new process node.
Phase-shift masks were introduced at the 180nm process node. They alter the
phase of the light passing through some areas of the mask, changing the way it is
diffracted and so reducing the defocusing effect of mask dimensions that are less
than the wavelength of the illuminating light. The downside of using phase-shift
techniques is that the masks are more difficult and expensive to make.
Optical-proximity correction (OPC) techniques work out how to distort the patterns
on a mask to counter diffraction effects, for example by adding small ears to the
corners of a square feature on the mask so that they remain sharply defined on the
wafer. The technique introduces layout restrictions, has a computational cost in
design, and means that it takes longer and costs more to make the corrected
masks.
There are useful insights into the way in which different reticle enhancement
techniques can interact in this article about lithography-friendly design.
Theres a discussion of how to optimise the parameters of the scripts used to
undertake OPC on a full chip design here, and a piece on using a simulated
annealing technique to optimise multiple script parameters here. Theres also a
discussion of reducing the impact of advanced OPC techniques on mask-making
costs, which rise with increasing complexity, here.
Optical equipment improvements, such as lenses with higher numerical apertures
that can bend the illuminating light more strongly, and immersion techniques that
put layers of liquid between the lens and the wafer to focus the light more strongly,
have also helped extend the lifetime of 193nm lithography. The gains available from
these techniques have been limited by the lack of significantly superior materials
for the lenses and the immersion fluids.
Alternative illumination techniques, such as off-axis illumination and the use of
multiple sources, give designers another way to make diffraction and interference
effects work to their advantage. The technique introduces complexity to the
illumination source in the wafer stepper and to the mask design.
Computational lithography, which blends OPC and alternative illumination by using
computation to start with the desired pattern on the wafer and work backwards to
define how to pre-distort the mask and configure multiple illumination sources to
achieve that pattern on the wafer. This approach takes large amounts of
computation power.

Theres a look at how computational lithography has evolved over the past 12
years here, and an interesting discussion of the potential of source-mask
optimisation and alternative illumination techniques in a paper here.
Double patterning is another technique used to extend the useful lifetime of 193nm
lithography. The process splits dense patterns into two interleaved patterns of lessdense features, defined by two masks. Given sufficiently accurate alignment, the
two patterns marry up on the wafer surface to create much denser features than
could be achieved with one mask.
Where can I use it?
Double patterning will be necessary to define the critical layers of designs being
built using 193nm illumination on process nodes below 30nm.
What are the risks of using double patterning?

Design restrictions. Double patterning will work best on designs whose critical
layers can be split into two separately defined but aligned patterns in a
predictable way. This means that producing a design layout that looks like a
diffraction grating is good, while a design littered with diagonal lines, jogs,
and vias between layers may be less easy to split effectively.

Cost. Double patterning is expensive because it uses two masks to define a

layer that was defined with one at previous process nodes. This means
buying more steppers to maintain a fabs throughput.

Variability. The emphasis on more regular layout with long linear tracks may
make designs more susceptible to the performance variability brought on by
limited control of the roughness of the edges of patterned .

Alignment issues. Double patterning brings alignment issues on to critical

layers, rather than between layers as before, with a potential impact on
design performance and production yield.

Who is involved in developing double patterning?

Successfully implementing double patterning means drawing on skills and insight
from across the semiconductor industry, including IC makers, equipment and
materials companies, mask makers, meteorologists, design-tools companies and
research organisations. For example, the European LENS project is a consortium of
12 companies working together to create the technological infrastructure and
supply chain for double patterning.