The simple LC3 computer was designed to increment the PC counter and

perform the instructions at the PCs location in the memory. Instructions can either
be read or written to the memory via the switches, which allows the user to control
what the CPU does. To operate the CPU the 16 switches can be changed to either
set the PC starting value if it is other than x0 or changed to whatever instruction the
user wishes to be written to memory. The CPU also has three buttons: a reset, run
and continue. The Reset button sets the PC back to x0 and clears the instruction
register, allowing computation to begin again. The Run button starts computation
based on the PC value loaded via the switches and skips to that address in memory.
Finally the continue button will move the PC value up by 1 which is needed to move
past pause statements in the memory which hold the PC value constant. To make
this simple CPU, we created a module for each of the modules and MUXs given in
the Appendix C of the microarchitecture book. The inputs and outputs of these
modules as well as their purpose are detailed below. (INSERT PICTURE OF PG
570???)
SLC3 Inputs: Switches, Clk, Reset, Run, Continue, Data Bus
Outputs: LEDs, Hex Displays, CE, UB, LB, OE, WE, Address Bus, Data Bus
This module was the top level of the CPU which controlled which output was on the
bidirectional data bus and which gates needed to be open to take this output. The
inputs from the switches are set to the PC when the run button is pressed and
written into memory when the WE (write enable) bit is high. The top level module
also initializes all other modules within this CPU which are used in conjunction with
the state machine to correctly compute all types of instructions passed from
memory.
ISDU The ISDU is the state machine of the CPU. It controls which bits need to be
high or low at a given state so that multiple values are never passed onto the bus at
the same time. See the state machine below for a more complete picture.
PC Inputs: 16-bit data in from the bus, 16 switch values and logic variables from
the Clock, Load and Reset signals
Output: 16-bit output to bus
This module will set the value of the switches as the starting PC value upon Reset
being HIGH. It will also load a PC value from memory or from a register if the load
bit is HIGH. This allows us to do BRANCH and JUMP commands.
IR/MAR/MDR Inputs: 16-bit input from the bus and the Clock, Reset and Load logic
variables
Output: 16-bit output to bus

These three modules function the same way by loading the data from the bus into
the IR/MAR/MDR register when the load bit goes HIGH from the ISDU. If the reset bit
goes HIGH from the ISDU, then the registers are set to 0.
Conditions Input: 16-bit data in (dataIn)
Outputs: N, Z, P logic variables
This module takes the value of the switches or the ALU that is on the bus and
determines if the most significant bit is a 1 or 0. If it is a 1, then the N (negative) bit
is set to HIGH. If the most significant bit is 0, then all bits are checked if they are 0.
If true, the Z (zero) bit is HIGH and if otherwise the P (positive) bit is set HIGH.
CPU_bus Inputs: 16-bit PC value, 16-bit MARMUX input, 16-bit MDR input and 16bit ALU input as well as single bit logic variables for the PC gate, MDR gate,
MARMUX gate, ALU gate
Output: 16-bit data register (busOut)
This module controls which locations the CPU should load the data from the bus
into. It waits for a signal from the four modules that take inputs from the bus to go
high and passes that data through. If no input is high, the bus will hold high
impedance and do nothing.
buffer Inputs: 16-bit data in register (dataIN), a gate logic bit
Output: 16-bit data out register
This is a universal tri-state buffer module that takes in the gate logic for when a
specific gate should be outputting to the bus or not. If it is supposed to be
outputting, the data out is passed the data in and if not, the data out is passed high
impedance.
RegisterFile Inputs: 16-bit data in from bus, 3-bit DR, SR1 and Sr2 registers, Load,
Clock and Reset logic variables
Outputs: 16-bit SR1 output and SR2 output
This module stores the values of each of the eight registers R0-R7. If the load bit is
HIGH from the ISDU, the value from the bus is loaded into the register given by the
value in DR. Finally, the register file is always outputting the registers given by SR1
and Sr2 respectively so that the ALU can access them. The DR, SR1 and SR2 are all
passed via the instruction register.
ALU Inputs: Two 16-bit data in registers (A and B), 2-bit ALUK select
Outputs: 16-bit data out register (dataOut)

This module outputs the addition of A and B if the ALUK is 00, the AND of A and B if
the ALUK is 01, the inverse of A if the ALUK is 10 or simply passes A through to the
output if the ALUK is 11. This completes all the types of functions the CPU can do
without also changing the PC value.
adder_unit Inputs: Two 16-bit data in registers (dataIn1, datain2)
Outputs: One 16-bit data out register (dataOut)
This module simply adds the two registers using the built in add function of System
Verilog and outputs the result.