Prime Time for ECO

Increasing design complexities and the rapidly increasing number of scenarios impede the timing closure
process. ECO techniques that have good single-pass fix rates can reduce the number of iterations through
the extraction, implementation, and final signoff loop for fastest timing closure.
PrimeTime ECO Guidance technology uses signoff-driven analysis to efficiently identify ECO changes for
DRC and timing fixes at block or chip level, shortening tape-out schedules by weeks.
PrimeTime ECO Guidance can take advantage of positive timing slack to identify leakage power reduction
changes to the netlist without creating new timing violations.
Physically-aware ECO Guidance works closely with IC Compilers Minimum Physical Impact (MPI)
technology, allowing routing and placement-aware fixes that maximize fix rates by minimizing disruption
to an existing layout.
Perform pessimism reduction techniques such as advanced on-chip variation (AOCV), parametric on-chip
variation (POCV), and path-based analysis (PBA) across all scenarios.
When performing an ECO, timing estimation methods cannot properly estimate signoff timing effects such
as signal integrity (SI), path-based analysis (PBA), waveform propagation, advanced on-chip variation
(AOCV), or parametric on-chip variation (POCV).
As a result, ECO solutions that rely on timing estimations or non-signoff timing engines are less
predictable and often require additional iterations to close timing.

Prime Time for ECO

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eInfochips Confidential Document - Copy right 2013-2015 eInfochips

Prime Time for ECO

eI/GL/ASIC/FORM/0017

eInfochips Confidential Document - Copy right 2013-2015 eInfochips

Prime Time

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eInfochips Confidential Document - Copy right 2013-2015 eInfochips

Prime Time

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Prime Time for ECO

PrimeTime ECO guidance uses the following patented technology:

1) Composite graph view.
2) Calibrated estimation.

In Composite Graph View: the composite graph view, is created from the individual timing graphs and
provides a global view of all violations across all scenarios. The ECO algorithms reference this composite
graph view to make fixing decisions for one scenario without affecting others.
Calibrated Estimation: This technique quickly evaluates all available fixing options for a given timing
violation and estimates the outcomes for all options without requiring a full timing analysis. It then
calibrates the results with the signoff-accurate timing data from the all-scenario timing view, accounting
for all analysis techniques including signal integrity, waveform propagation, and advanced on-chip
variation effects. Figure 4 depicts the fast identification and selection of the best guidance decision for the
device under consideration.

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Prime Time Advance On Chip Variation

On chip variation, the current standard model for variation in a designer's STA flow is the first order
approach that applies a blanket margin across the chip.
With increasing variations due to process, voltage and temperature, as well as increasing variations
across the same die and from die to die, arriving at a single blanket margin number is difficult.
Advanced OCV technology in PrimeTime is an easy to adopt solution that takes into consideration the
needs of todays designers to provide the right balance of accuracy and runtime for STA.
It uses intelligent techniques for context specific derating instead of a single global derate value, thus
reducing the excessive design margins and leading to fewer timing violations.
The Advanced OCV solution determines derate values as a function of logic depth and/or cell, and net
location.

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Prime Time Advance On Chip Variation

There are two kinds of variation:

1) Random
2) Systematic

Random variation is proportional to logic depth of each path being analyzed.

Systematic variation is proportional to the cell location of the path being analyzed.

The random component of variation occurs from lot to lot, wafer to wafer or die to die.

The systematic component of variation is predicted from the location on the wafer or the nature of the
surrounding pattern.

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Random Variation

Statistical analysis shows that the random variation is less for deeper timing paths and not all cells are
simultaneously fast or slow.

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Systematic Variation
Using silicon data from test chips, Advance OCV derate factors based on relative cell location are then
applied to further improve accuracy and reduce pessimism of the path, Advance OCV computes length
and diagonal of the bounding box.
The derate factors for systematic variation are based on silicon data, unlike random variation, which
generally assumes a type of distribution, modeling of this variation is based on detailed empirical
measurement of how variation relates to the geometric seperation between the devices.

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Customized On Chip Variation

There is added flexibility for customizing the Advanced OCV timing flow with the below mentioned
features.
1) Guard Banding :
In addition to Advance OCV, one can specify guard band timing derates, to model non process
related effects.
Ftotal = [Fprocess Variability] X [Firdrop X Fmargin X Ftoolerror...]
2) Cell Based Depth Coefficients:
By default, all cells count as 1 for depth computation. However, cells comprised of many
transistors can exhibit less variation than other standard cell library cells.

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Advance OCV Derate Table

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Prime Time Advanced OCV Flow

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Prime Time Advanced OCV Flow

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A clock network only analysis can simplify the

adoption of Advanced OCV. By limiting the analysis to
clocks the derate tables are typically required for
clock cells, which are typically a small portion of the
cell library.
The slack improvement by considering just clock data
is significant.
The next stage is to consider both clock and signal
data though it will need significant effort and
computation time.

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